JP2007335713A - Bidirectional thyristor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bidirectional thyristor wherein trade-off is improved between trigger sensitivity in second and third modes (mode II and mode III) and a critical voltage rising rate (dv/dt)c at commutation. <P>SOLUTION: First, second, third and fourth n-type semiconductor regions N1, N2, N3 and N4, and first and second p-type semiconductor regions P1, P2, are provided in a semiconductor substrate 1 for constituting a bidirectional thyristor. A first main electrode T1 and a gate electrode G are disposed in one surface 2 of the semiconductor substrate 1. A second main electrode T2 is provided to the other major surface 3 of the semiconductor substrate 1. A first portion N4a which is diffused shallow, and a second portion N4b which is diffused deep, are provided to the fourth n-type semiconductor region N4. The second portion N4b is disposed far from a center of first and second main thyristors. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a bidirectional thyristor or TRIAC in which the trade-off relationship between trigger sensitivity and commutation critical voltage increase rate (dv / dt) c is improved.

  A typical bidirectional thyristor (triac) known in Patent Document 1 includes first, second, third and fourth N-type semiconductor regions N1, N2, N3, N4 as shown in FIG. The semiconductor substrate 1 having the first and second P-type semiconductor regions P1 and P2, the first and second main electrodes T1 and T2, and the gate electrode G. The first main electrode T1 is disposed on one main surface 2 of the semiconductor substrate 1, and is connected to both the second N-type semiconductor region N2 and the first P-type semiconductor region P1. The second main electrode T2 is disposed on the other main surface 3 of the semiconductor substrate 1, and is connected to both the second P-type semiconductor region P2 and the third N-type semiconductor region N3. The gate electrode G is disposed on one main surface 2 of the semiconductor substrate 1 and is connected to both the fourth N-type semiconductor region N4 and the first P-type semiconductor region P1. 1A, 1B, 1C, and 1D respectively show portions corresponding to the line AA in FIG. 1A shows a first mode (mode I) described later, FIG. 1B shows a second mode (mode II) described later, and FIG. 1C shows a third mode described later. Mode (mode III) is shown, and FIG. 1D shows a fourth mode (mode IV) described later.

This bidirectional thyristor is composed of a first main thyristor portion composed of four semiconductor regions indicated by N2, P1, N1, and P2, and four semiconductor regions indicated by P1, N1, P2, and N3. It has a second main thyristor portion and a gate mechanism portion (auxiliary thyristor portion) composed of N4, P1, N1, P2, and N3, and can be turned on in the following four modes.
(1) A first mode (mode I) in which the gate electrode G is turned on with a positive potential when the second main electrode T2 is at a positive potential with reference to the first main electrode T1.
(2) A second mode (mode II) in which the gate electrode G is turned on with a negative potential when the second main electrode T2 is at a positive potential with reference to the first main electrode T1.
(3) A third mode (mode III) in which the gate electrode G is turned on with a negative potential when the second main electrode T2 is at a negative potential with reference to the first main electrode T1.
(4) A fourth mode (mode IV) in which the gate electrode G is turned on with a positive potential when the second main electrode T2 is at a negative potential with respect to the first main electrode T1.

Next, operations in the first to fourth modes will be described. In FIG. 1, the flow of electrons (E) is indicated by dotted lines, and the flow of holes (H) and gate trigger current I _GT and the main currents I _{1 and} I ₂ in the first and second directions are indicated by solid lines. Has been.

In the first mode (mode I), the first main thyristor portion is turned on by the following operation.
(1) A gate trigger current _IGT flows from the gate electrode G to the first main electrode T1. (2) As a result, a voltage drop occurs in the first P-type semiconductor region P1, and the PN junction between the second N-type semiconductor region N2 and the first P-type semiconductor region P1 is in a forward bias state. Electrons (E) are injected from the two N-type semiconductor regions N2 into the first P-type semiconductor region P1.
(3) A part of the electrons (E) injected into the first P-type semiconductor region P1 enters the first N-type semiconductor region N1, where electrons are accumulated.
(4) As a result, injection of holes (H) from the second P-type semiconductor region P2 to the first N-type semiconductor region N1 occurs.
(5) Part of the holes (H) injected into the first N-type semiconductor region N1 enters the first P-type semiconductor region P1, and the second P-type semiconductor region N2 to the first P-type semiconductor The injection of electrons (E) into the region P1 is promoted.
(6) The above operation is amplified, and finally the second main electrode T2, the second P-type semiconductor region P2, the first N-type semiconductor region N1, the first P-type semiconductor region P1, and the second A main current I ₁ in the first direction flows through a path between the N-type semiconductor region N2 and the first main electrode T1.

In the second mode (mode II), the first main thyristor portion is turned on by the following operation.
(1) A gate trigger current I _GT flows from the first main electrode T1 to the gate electrode G. (2) As a result, a voltage drop occurs in the first P-type semiconductor region P1, the PN junction between the fourth N semiconductor region N4 and the first P-type semiconductor region P1 becomes a forward bias state, and the fourth Electrons (E) are injected from the N-type semiconductor region N4 into the first P-type semiconductor region P1.
(3) A part of the electrons (E) injected into the first P-type semiconductor region P1 enters the first N-type semiconductor region N1, where electrons are accumulated.
(4) As a result, injection of holes (H) from the second P-type semiconductor region P2 to the first N-type semiconductor region N1 occurs.
(5) Part of the holes (H) injected into the first N-type semiconductor region N1 enters the first P-type semiconductor region P1, and the first N-type semiconductor region N4 to the first P-type semiconductor The injection of electrons (E) into the region P1 is promoted. Thereby, a gate mechanism portion (auxiliary thyristor portion) composed of the fourth N-type semiconductor region N4, the first P-type semiconductor region P1, the first N-type semiconductor region N1, and the second P-type semiconductor region P2 is formed. It becomes conductive.
(6) Since the gate mechanism portion (auxiliary thyristor portion) is close to the first main thyristor portion composed of four semiconductor regions indicated by N2, P1, N1, and P2, the gate mechanism portion (auxiliary portion) The electron and hole injection operation in the thyristor portion) is transferred to the first main thyristor portion, the first main thyristor portion is turned on, and the second main electrode T2 and the second main electrode T2 are turned on as in the first mode. Two P-type semiconductor regions P2, the first N-type semiconductor region N1, the first P-type semiconductor region P1, the second N-type semiconductor region N2, and the first main electrode T1 in the first direction. the main current I ₁ flows. The current in the gate mechanism portion (auxiliary thyristor portion) is limited to a predetermined value or less by the resistance of a gate circuit (not shown).

In the third mode (mode III), the second main thyristor portion is turned on by the following operation.
(1) A gate trigger current I _GT flows from the first main electrode T1 to the gate electrode G. (2) As a result, a voltage drop occurs in the first P-type semiconductor region P1, the PN junction between the fourth N semiconductor region N4 and the first P-type semiconductor region P1 becomes a forward bias state, and the fourth Electrons (E) are injected from the N-type semiconductor region N4 into the first P-type semiconductor region P1.
(3) A part of the electrons (E) injected into the first P-type semiconductor region P1 enters the first N-type semiconductor region N1, where electrons are accumulated.
(4) Thereby, the forward bias state of the PN junction between the first N-type semiconductor region N1 and the first P-type semiconductor region P1 is strengthened, and the first P-type semiconductor region P1 to the first N-type semiconductor region P1 are strengthened. Holes (H) flow into the type semiconductor region N1. This hole (H) reaches the second main electrode T2 through the first N-type semiconductor region N1 and the second P-type semiconductor region P2. As a result, a voltage drop occurs in the second P-type semiconductor region P2, the PN junction between the third N-type semiconductor region N3 and the second P-type semiconductor region P2 becomes a forward bias state, and the third Electrons (E) are injected from the N-type semiconductor region N3 into the second P-type semiconductor region P2, and the electrons (E) enter the first N-type semiconductor region N1. As a result, the five semiconductor regions indicated by N4, P1, N1, P2, and N3 in the gate mechanism portion (auxiliary thyristor portion) become conductive.
(5) Since the gate mechanism portion (auxiliary thyristor portion) in the conductive state is close to the second main thyristor portion including the four semiconductor regions indicated by P1, N1, P2, and N3, the gate mechanism portion ( The operation of injecting electrons and holes in the auxiliary thyristor portion) is transferred or spread to the second main thyristor portion, the second main thyristor portion is turned on, and the first main electrode T1 and the first P-type semiconductor region A main current I ₂ in the second direction flows through a path between P1, the first N-type semiconductor region N1, the second P-type semiconductor region P2, the third N-type semiconductor region N3, and the second main electrode T2. .

In the fourth mode (mode IV), the second main thyristor portion is turned on by the following operation.
(1) A gate trigger current I _GT flows from the gate electrode G to the first main electrode T1. (2) As a result, a voltage drop occurs in the first P-type semiconductor region P1, the PN junction between the second N-type semiconductor region N2 and the first P-type semiconductor region P1 enters a forward bias state, and Electrons (E) are injected from the second N-type semiconductor region N2 into the first P-type semiconductor region P1.
(3) A part of the electrons (E) injected into the first P-type semiconductor region P1 enters the first N-type semiconductor region N1, where electrons are accumulated.
(4) Thereby, the forward bias state of the PN junction between the first N-type semiconductor region N1 and the first P-type semiconductor region P1 is strengthened, and the first P-type semiconductor region P1 to the first N-type semiconductor region P1 are strengthened. Holes (H) flow into the type semiconductor region N1. This hole (H) reaches the second main electrode T2 through the first N-type semiconductor region N1 and the second P-type semiconductor region P2. As a result, a voltage drop occurs in the second P-type semiconductor region P2, the PN junction between the third N-type semiconductor region N3 and the second P-type semiconductor region P2 becomes a forward bias state, and the third Electrons (E) are injected from the N-type semiconductor region N3 into the second P-type semiconductor region P2, and the electrons (E) enter the first N-type semiconductor region N1. Accordingly, the second main thyristor portion is turned on as in the third mode, and the first main electrode T1, the first P-type semiconductor region P1, the first N-type semiconductor region N1, and the second P-type are turned on. A main current I ₂ in the second direction flows through the path of the semiconductor region P2, the third N-type semiconductor region N3, and the second main electrode T2.

  As can be seen from the operations in the first to fourth modes, the equivalent circuit of the bidirectional thyristor can be represented by a circuit in which two reverse blocking thyristors, that is, SCRs are connected in reverse parallel. In general, the bidirectional thyristor is used as an AC control switch such as a motor phase control. Therefore, when the bidirectional thyristor is used in the above AC circuit, the first main thyristor portion in which the current in the first direction flows in the bidirectional thyristor and the second main in which the current in the second direction flows. The thyristor portion is alternately conducted.

By the way, immediately after the gate trigger current decreases and becomes zero, the remaining carriers exist in the semiconductor substrate 1 for a while even if the first main thyristor portion is turned off due to the lifetime of the internal carriers of the semiconductor substrate 1. The first or second main thyristor portion may be erroneously turned on based on the remaining carrier. For example, when an inductive load or a capacitive load is connected to the bidirectional thyristor, when the current is turned ON / OFF by the bidirectional thyristor, a phase difference is generated between the current and the voltage, and the first of the bidirectional thyristors When the current in the first direction flowing through the main thyristor portion becomes zero, a voltage in the second direction opposite to the first direction (reverse voltage) is applied to the first main thyristor portion. There is also a possibility that a voltage in the second direction (reverse voltage) such as propagation noise, induction noise or external noise is applied to the first main thyristor portion. If the gate trigger current decreases and becomes zero, the voltage increase rate (dv / dt) of the voltage (reverse voltage) in the second direction, which is opposite to the direction in which the current is conducted immediately after the gate trigger current becomes zero, is greater than a predetermined value. If it is too high, the bi-directional thyristor may be accidentally ignited and accidentally turned on even though the gate trigger current I _GT is supplied to the bi-directional thyristor and the ON control is not performed. is there. This malfunction is more likely to occur as the voltage increase rate (dv / dt) of the reverse voltage when the bidirectional thyristor is turned off is higher. Therefore, the tolerance for the malfunction of the bi-directional thyristor, a bidirectional thyristor when the gate trigger current I _GT is applied to the reduced zero the direction opposite to the direction that has been turned immediately became bidirectional thyristor shoot through current The critical value of the voltage increase rate (dv / dt) to be used, that is, the critical voltage increase rate (dv / dt) c at the time of commutation is used. In order to prevent malfunction, it is desirable to increase the critical voltage increase rate (dv / dt) c during commutation.

The following three methods are known as a method of increasing the critical voltage increase rate (dv / dt) c during commutation, that is, a method of preventing malfunction.
(A) A method of reducing the malfunction of the bidirectional thyristor due to the remaining carriers by diffusing heavy metals such as gold into the semiconductor substrate 1 to shorten the lifetime of the carriers.
(B) The ratio Cn2 / Cp1 between the impurity concentration Cn2 of the second N-type semiconductor region N2 and the impurity concentration Cp1 of the first P-type semiconductor region P1, and the impurity concentration Cn3 of the third N-type semiconductor region N3 and the first A method of reducing current amplification and reducing malfunction by reducing the carrier injection efficiency by reducing the ratio Cn3 / Cp2 with the impurity concentration Cp2 of the P type semiconductor region P2 of 2.
(C) A method in which the first main thyristor portion and the second main thyristor portion are largely separated to reduce malfunctions due to residual carriers. For example, in Patent Document 1, the distance between the second N-type semiconductor region N2 and the third N-type semiconductor region N3, the distance between the second N-type semiconductor region N2 and the fourth N-type semiconductor region N4, and It is disclosed that the distance between one main electrode T1 and the fourth N-type semiconductor region N4 is equal to each other.

However, when using the method of the above (a) and (b), although the time of the commutation threshold voltage rise rate (dv / dt) c are improved, gate - Totoriga current I _GT increases. That is, the trigger sensitivity and the commutation critical voltage increase rate (dv / dt) c are in a trade-off relationship, and when one of the characteristics is improved, the other characteristic is deteriorated. In addition, when the methods (a) and (b) are used, other electrical characteristics of the bidirectional thyristor such as an increase in the on-resistance (on voltage) of the bidirectional thyristor are deteriorated.
When the method (c) is used, if the same rated current as in the conventional case is to be secured, the first and second main thyristor portions must be formed in the same size as in the conventional case. The size (chip size) of the semiconductor substrate is increased by a large distance between the thyristor portion and the second main thyristor portion, which hinders downsizing and cost reduction of the bidirectional thyristor. In the case of the bidirectional thyristor according to Patent Document 1, not only miniaturization and cost reduction of the bidirectional thyristor are inhibited, but the first main electrode T1 and the fourth N-type semiconductor region N4 face each other. The side becomes longer, the effective area of the portion through which the gate trigger current I _GT flows in the first P-type semiconductor region P1 becomes larger, and the voltage drop generated in the first P-type semiconductor region P1 becomes smaller. must be increased Totoriga current I _GT - sensitivity decreases, gate in order to ignite the bidirectional thyristor.

In order to improve the trigger sensitivity without involving a reduction in the time of the commutation threshold voltage rise rate (dv / dt) c, gate - a portion for suppressing Totoriga reactive current component which does not contribute to trigger within the current I _GT Patent Document 2 discloses that the first main electrode T1 is provided between the first main electrode T1 and the fourth N-type semiconductor region N4. However, it has been difficult to obtain both the desired critical voltage increase rate (dv / dt) c during commutation and the desired trigger sensitivity by the method of Patent Document 2.

By the way, among the first to fourth modes (modes I to IV), the fourth mode (mode IV) is hardly used. Therefore, it is desirable to improve the trade-off between the trigger sensitivity of the first to third modes (modes I to III) and the critical voltage increase rate (dv / dt) c during commutation. Further, since the second and third modes (modes II and III) are more difficult to turn on than the first mode (mode I), the gates in the second and third modes (modes II and III) are difficult to turn on. The to-trigger current I _GT had to be increased as compared with the first mode (mode I). Therefore, an improvement in the trade-off between trigger sensitivity and commutation critical voltage increase rate (dv / dt) c in the second and third modes (modes II and III) is particularly required.
JP-A-8-97407 JP 2005-26262 A

  The problem to be solved by the present invention is that it is difficult to improve the trade-off between the trigger sensitivity in the second and third modes (modes II and III) and the critical voltage increase rate (dv / dt) c at the time of commutation. It is. Accordingly, an object of the present invention is to provide a bidirectional thyristor with improved trade-off between trigger sensitivity and commutation critical voltage increase rate (dv / dt) c in the second and third modes (modes II and III). It is to provide.

To solve the above problems and achieve the above object, the present invention will be described with reference numerals in the drawings showing the embodiments. It should be noted, however, that the claims and the reference signs used herein are intended to assist the understanding of the present invention and are not intended to limit the present invention.
The present invention includes a semiconductor substrate (1), a first main electrode (T1) and a gate electrode (G) provided on one main surface (2) of the semiconductor substrate (1), and the semiconductor substrate (1). A second main electrode (T2) provided on the other main surface (3) of 1),
The semiconductor substrate (1) is arranged adjacent to a first semiconductor region (N1) of a first conductivity type and one main surface side of the first semiconductor region (N1), and the semiconductor substrate (1) Of the second conductivity type opposite to the first conductivity type having a portion exposed on the one main surface (2) of the second semiconductor region (P1), and the first semiconductor region (N1) ) Adjacent to the other main surface side and having a portion exposed to the other main surface (3) of the semiconductor substrate (1), a third semiconductor region (P2) of the second conductivity type And a fourth semiconductor of the first conductivity type having a portion that is disposed adjacent to the second semiconductor region (P1) and exposed to the one main surface (12) of the semiconductor substrate (1). A region (N2) and the other main surface of the semiconductor substrate (1) disposed adjacent to the third semiconductor region (P2) 3) a first conductivity type fifth semiconductor region (N3) having a portion exposed to 3), and the one of the semiconductor substrates (1) disposed adjacent to the second semiconductor region (P1) A sixth semiconductor region (N4) of the first conductivity type having a portion exposed to the main surface (2) of
The first main electrode (T1) is connected to both the second semiconductor region (P1) and the fourth semiconductor region (N2);
The second main electrode (T2) is connected to both the third semiconductor region (P2) and the fifth semiconductor region (N3);
In the bidirectional thyristor in which the gate electrode (G) is connected to both the second semiconductor region (P1) and the sixth semiconductor region (N4),
The sixth semiconductor region (N4) has a first portion (N4a) having a first interval (W1) with respect to the first semiconductor region (N1), and the first semiconductor region A second portion (N4b) having a second interval (W2) smaller than the first interval (W1) with respect to (N1),
The second portion (N4b) of the sixth semiconductor region (N4) and the fourth semiconductor region (N2) when viewed from a direction perpendicular to one surface (2) of the semiconductor substrate (1). ) Is shorter than the shortest distance (L1) between the first portion (N4a) of the sixth semiconductor region (N4) and the fourth semiconductor region (N2). The present invention relates to a bidirectional thyristor characterized by being largely determined.

In addition, as shown in Claim 2, the fifth semiconductor region (N3) has a first portion (W3) having a third interval (W3) with respect to the first semiconductor region (N1). N3a) and the second interval of the sixth semiconductor region (N4) having a fourth interval (W4) smaller than the third interval (W3) with respect to the first semiconductor region (N1). And a second portion (N3b) arranged to face the portion (N4b) of the semiconductor substrate (1) when viewed from a direction perpendicular to one main surface (2) of the semiconductor substrate (1). The shortest distance (L4) between the second portion (N3b) of the fifth semiconductor region (N3) and the fourth semiconductor region (N2) is the first of the fifth semiconductor region (N3). Is determined to be larger than the shortest distance (L3) between the portion (N3a) and the fourth semiconductor region (N2). It is desirable.
Further, as shown in claim 3, the bidirectional thyristor can be modified. The fifth semiconductor region (N3) of the modified bidirectional thyristor is opposed to the sixth semiconductor region (N4) and has a first interval with respect to the first semiconductor region (N1). The first portion (N3b ′) facing (W3) and the sixth semiconductor region (N4) are opposed to the first semiconductor region (N1). And a second portion (N3c) facing each other with a second interval (W4) smaller than the interval (W3). The second portion (N3c) and the fourth semiconductor region of the fifth semiconductor region (N3) when viewed from a direction perpendicular to the one surface (2) of the semiconductor substrate (1). The shortest distance (L4) to (N2) is the shortest distance (L3) between the first portion (N3b ′) of the fifth semiconductor region (N3) and the fourth semiconductor region (N2). ) Is larger than.
Moreover, as shown in claim 4, it is desirable that a portion (50) for suppressing an ineffective portion of the gate trigger current is disposed in the second semiconductor region (P1).
Further, as shown in claim 5, it is desirable that the gate electrode (G) is provided with a notch (60) for reducing the ineffective portion of the gate trigger current.
Further, as shown in claim 6, the first semiconductor region (N1) in the sixth semiconductor region (N4) of claim 1 has a first interval (W1) with respect to the first semiconductor region (N1). Instead of the first portion (N4a) and the second portion (N4b) having the second interval (W2), the first portion (N4a ′) having the first impurity concentration And a second portion (N4b ′) having a second impurity concentration higher than the first impurity concentration. Further, in the configuration of claim 6, a distance between the second portion (N4b ′) having the second impurity concentration in the sixth semiconductor region (N4) and the first semiconductor region (N1). Can be made larger than the distance between the first portion (N4a ′) having the first impurity concentration in the sixth semiconductor region (N4) and the first semiconductor region (N1). .
Further, as shown in claim 7, the first space (W3) with respect to the first semiconductor region (N1) in the fifth semiconductor region (N3) of claim 3 has a first interval (W3). Instead of the first portion (N3b ′) and the second portion (N3c) having the second interval (W4), the first portion (N3b ′) having the first impurity concentration is used. ) And a second portion (N3c ′) having a second impurity concentration higher than the first impurity concentration. Further, in the configuration of claim 7, a distance between the second portion (N3c ′) having the second impurity concentration in the fifth semiconductor region (N3) and the first semiconductor region (N1). (W4) is determined by the distance (W3) between the first semiconductor region (N1) and the first portion (N3b ′) having the first impurity concentration in the fifth semiconductor region (N3). Can also be increased.

The sixth semiconductor region (N4) of the bidirectional thyristor according to claim 1 of the present invention has a first portion (N4a) having a first interval (W1) with respect to the first semiconductor region (N1). ) And a second portion (N4b) having a second interval (W2) smaller than the first interval (W1) with respect to the first semiconductor region (N1). Yes. The second portion (N4b) of the sixth semiconductor region (N4) is further away from the first portion (N4a) than the fourth semiconductor region (N2). The first portion (N4a) of the sixth semiconductor region (N4) is a first main electrode (T1) connected to both the second semiconductor region (P1) and the fourth semiconductor region (N2). In contrast, in the second and third modes, the first portion (N4a) of the sixth semiconductor region (N4) functions as a gate trigger start point because it is closer to the second portion (N4b). However, since the second portion (N4b) of the sixth semiconductor region (N4) is closer to the first semiconductor region (N1) than the first portion (N4a), the gate mechanism portion (auxiliary thyristor portion) ) Spreads well from the first part (N4a) gradually to the second part (N4b). That is, the injection of minority carriers (electrons) from the sixth semiconductor region (N4) into the second semiconductor region (P1) first starts from the first portion (N4a) of the sixth semiconductor region (N4). Eventually, however, the second portion (N4b) is also performed, and the minority carrier injection amount from the second portion (N4b) is significantly larger than the minority carrier injection amount from the first portion (N4a). Become. Accordingly, the main ON operation region of the gate mechanism portion (auxiliary thyristor portion) is the second portion (N4b) of the sixth semiconductor region (N4) and the second semiconductor region (P1) in the second mode. It consists of a first semiconductor region (N1) and a third semiconductor region (P2). In the third mode, the second portion (N4b) of the sixth semiconductor region (N4) and the second semiconductor region ( P1), a first semiconductor region (N1), a third semiconductor region (P2), and a fifth semiconductor region (N3). When the gate mechanism portion (auxiliary thyristor portion) is turned on in the second mode, the on state is propagated to the first main thyristor portions (N2, P1, N1, P2). Further, when the gate mechanism portion (auxiliary thyristor portion) is turned on in the third mode, the on state is spread to the second main thyristor portions (P1, N1, P2, N3). If the second portion (N4b) is provided in the sixth semiconductor region (N4) according to the invention of claim 1, the auxiliary thyristor is easily turned on in the second and third modes, and the trigger sensitivity is improved. However, the rate of increase in critical voltage during commutation does not occur or is small.
By the way, the distance (W2) between the second portion (N4b) of the sixth semiconductor region (N4) and the first semiconductor region (N1) is equal to the first portion (N4a) and the first semiconductor region (N1). The trigger sensitivity of the bidirectional thyristor of the invention according to claim 1 is determined based on the second portion (N4b) of the sixth semiconductor region (N4), and is smaller than the interval (W1) between It is higher than the trigger sensitivity of the thyristor. That is, the trigger sensitivity of the bidirectional thyristor according to the present invention is such that the sixth semiconductor region (N4) and the first semiconductor region (N1) are provided without providing the second portion (N4b) in the sixth semiconductor region (N4). ) Is higher than the trigger sensitivity of the conventional bidirectional thyristor having the first interval (W1) as the minimum interval.
As described above, in the conventional bidirectional thyristor, the trigger sensitivity and the commutation critical voltage increase rate (dv / dt) c are in a trade-off relationship. On the other hand, the second portion (N4b) of the sixth semiconductor region (N4) that contributes to the improvement of the trigger sensitivity of the present invention is from the portion where the residual carriers that cause the malfunction of the bidirectional thyristor exist. It is formed at a distant position. Therefore, although the second portion (N4b) of the sixth semiconductor region (N4) contributing to the improvement of the trigger sensitivity is provided, the first or second main thyristor portion is based on the remaining carriers. Is less likely to malfunction. Accordingly, it is possible to improve the trigger sensitivity without the trade-off relationship between the trigger sensitivity and the commutation critical voltage increase rate (dv / dt) c or to suppress the increase of the gate current.
In addition, the mutual distance between the conventional first main thyristor portion and the second main thyristor portion is increased, and the trade-off relationship between the trigger sensitivity and the commutation critical voltage increase rate (dv / dc) c is improved. The bidirectional thyristor can be reduced in size as compared with the bidirectional thyristor having the structure.
The improvement in the trade-off relationship between the trigger sensitivity and the critical voltage increase rate (dv / dc) c at the time of commutation, as shown in claim 3, is the first semiconductor region (N4) of the first semiconductor region according to claim 1 This can also be achieved by providing the first semiconductor part (N3b ′) and the second part (N3c) corresponding to the part (N4a) and the second part (N4b) in the fifth semiconductor region (N3). As shown in claim 2, it is most desirable to have both the configuration of the sixth semiconductor region (N4) of claim 1 and the configuration of the fifth semiconductor region (N3) of claim 3.
The second portion (N4b ′) having a high impurity concentration in the sixth semiconductor region (N4) of the bidirectional thyristor according to claim 6 is formed in the sixth semiconductor region (N4) of the bidirectional thyristor according to claim 1. Similar to the second part (N4b), it contributes to the improvement of trigger sensitivity without or suppressing the decrease in the critical voltage increase rate (dv / dt) c during commutation.
Further, the second portion (N3c ′) having a high impurity concentration in the fifth semiconductor region (N3) of the bidirectional thyristor according to claim 7 is formed in the fifth semiconductor region (N3) of the bidirectional thyristor according to claim 3. Similar to the second part (N3c), it contributes to the improvement of trigger sensitivity without or suppressing a decrease in the critical voltage increase rate (dv / dt) c during commutation.

Next, an embodiment of the present invention will be described with reference to FIGS.

The bidirectional thyristor according to the first embodiment of the present invention shown in FIGS. 2 to 5 is provided with a first portion N4a and a second portion N4b formed deeper than this in a fourth N-type semiconductor region N4. Others are formed in the same manner as the conventional bidirectional thyristor of FIG. Accordingly, in FIGS. 2 to 5, the same reference numerals are given to the portions common to FIG. 1.

2 to 5, the bidirectional thyristor according to the first embodiment is similar to the conventional bidirectional thyristor of FIG. 1 in that the semiconductor substrate 1 made of, for example, silicon, the first and second main electrodes T1, T2, and the gate A gate electrode G and an insulating layer (not shown) disposed between the first main electrode T1 and the gate electrode G on one main surface of the semiconductor substrate 1 are provided.

The semiconductor substrate 1 includes first, second, third, and fourth N-type semiconductor regions N1, N2, N3, N4 and first and second P-type semiconductor regions P1, P2. The first to sixth semiconductor regions of the claims of the present application and the first, second, third and fourth N-type semiconductor regions N1, N2, N3, N4 and the first of the first embodiment of FIGS. The correspondence relationship with the second P-type semiconductor regions P1 and P2 is as follows. The first semiconductor region is the first N-type semiconductor region N1, the second semiconductor region is the first P-type semiconductor region P1, the third semiconductor region is the second P-type semiconductor region P2, and the fourth semiconductor region. Corresponds to the second N-type semiconductor region N2, the fifth semiconductor region corresponds to the third N-type semiconductor region N3, and the sixth semiconductor region corresponds to the fourth N-type semiconductor region N4.

The semiconductor substrate 1 is formed in a quadrangular shape when viewed from a direction perpendicular to one main surface 2 thereof, that is, in plan view, and has one flat main surface 2 and the other main surface 3 parallel thereto. Have Although one main surface 2 of the semiconductor substrate 1 of FIG. 2 is formed in a regular tetragon having first, second, third, and fourth sides 4, 5, 6, and 7 of equal length. It can also be transformed into a rectangle or another shape.

  The first N-type semiconductor region N1 is a region that can also be called an N-type base region, and is arranged in the center of the semiconductor substrate 1 in the thickness direction.

The first P-type semiconductor region P1 is a region that can also be referred to as a P-type base region, and is disposed between one main surface 2 of the semiconductor substrate 1 and the first N-type semiconductor region N1. One N-type semiconductor region N1 is adjacent and part of the main surface 2 is exposed. A PN junction between the first P-type semiconductor region P 1 and the first N-type semiconductor region N 1 extends in parallel to one main surface 2.

The second P-type semiconductor region P2 is disposed adjacent to the first N-type semiconductor region N1, and a part thereof is exposed on the other main surface 3. A PN junction between the second P-type semiconductor region P2 and the first N-type semiconductor region N1 extends parallel to the other main surface 3.

The second N-type semiconductor region N2 is a region formed by selectively diffusing N-type impurities in the first P-type semiconductor region P1, and is adjacent to the first P-type semiconductor region P1 and One main surface 2 is exposed. The second N-type semiconductor region N2 has a plurality of holes 8 for a short-circuit emitter structure, and the first P-type semiconductor region P1 is disposed in the holes 8. As apparent from FIG. 5, the outer shape of the second N-type semiconductor region N2 includes first and second sides 9 and 10 parallel to each other in plan view, and the first and second sides. 9 is a trapezoid having a third side 11 arranged at right angles to 9, 10 and a fourth side 12 which is inclined and opposed to the third side 11. The trapezoidal second N-type semiconductor region N2 is formed on one side of a diagonal line 15 connecting a pair of opposite corners 13 and 14 of one main surface 2 of the semiconductor substrate 1, that is, on the first and second sides of the semiconductor substrate 1. They are arranged in a triangle (above the diagonal line 15 of the semiconductor substrate 1) surrounded by the fourth sides 4 and 7 and the diagonal line 15. Further, the first side 9 of the trapezoidal second N-type semiconductor region N2 is arranged in parallel to the first side 4 of the semiconductor substrate 1 and the first side 4 of the semiconductor substrate 1 is more than the second side 10. Is located near. The third side 11 of the trapezoidal second N-type semiconductor region N2 is arranged in parallel to the fourth side 7 of the semiconductor substrate 1 and is closer to the fourth side 7 of the semiconductor substrate 1 than the fourth side 12 is. Is arranged.

The third N-type semiconductor region N3 is a region formed by selectively diffusing N-type impurities in the second P-type semiconductor region P2, and is adjacent to the second P-type semiconductor region P2. In addition, the other main surface 3 is exposed. As is apparent from FIG. 5, the third N-type semiconductor region N3 is composed of a combination of a trapezoidal portion N3a and a rectangular portion N3b, and includes first, second, third, fourth and fifth. Sides 16, 17, 18, 19, and 20. The trapezoidal portion N3a of the third N-type semiconductor region N3 is disposed symmetrically with respect to the second N-type semiconductor region N2 (below the diagonal 15 of the semiconductor substrate 1) about the diagonal 15 in FIG. N3b is on the diagonal 15 of the semiconductor substrate 1 at a position closer to the corner 14 (lower left side of the semiconductor substrate 1) of the second N-type semiconductor region N2 and the trapezoidal portion N3a of the third N-type semiconductor region N3. Is arranged. The first side 16 of the third N-type semiconductor region N3 is arranged in parallel to the second side 5 of the semiconductor substrate 1 and is closer to the second side 5 of the semiconductor substrate 1 than the fourth side 19 is. Is arranged. The second side 17 of the third N-type semiconductor region N3 is arranged in parallel with the third side 6 of the semiconductor substrate 1 and closer to the third side 6 of the semiconductor substrate 1 than the fifth side 20. Has been. The third side 18 of the third N-type semiconductor region N3 is arranged in parallel to the diagonal line 15 of the semiconductor substrate 1. The fourth side 19 of the third N-type semiconductor region N3 is arranged in parallel with the fourth side 7 of the semiconductor substrate 1. The fifth side 20 of the third N-type semiconductor region N3 is arranged in parallel to the second side 10 of the second N-type semiconductor region N2. Further, the rectangular portion N3b of the third N-type semiconductor region N3 as viewed in plan is formed so as to include the fourth N-type semiconductor region N4.

The fourth N-type semiconductor region N4 can also be referred to as a gate region or an auxiliary thyristor region, and is adjacent to the first P-type semiconductor region P1 as well as the second N-type semiconductor region N2. The main surface 2 is exposed. The fourth N-type semiconductor region N4 is formed by selectively diffusing N-type impurities in the first P-type semiconductor region P1. As is apparent from FIG. 5, the fourth N-type semiconductor region N4 is disposed in the quadrangular portion N3b of the third N-type semiconductor region N3 and viewed in plan, and the first, second, third, It has fourth, fifth and sixth sides 21, 22, 23, 24, 25, 26. The first side 21 of the fourth N-type semiconductor region N4 is arranged in parallel to the second side 5 of the semiconductor substrate 1 and is fourth of the semiconductor substrate 1 than the third and fifth sides 23 and 25. It is arranged away from the side 7. The second side 22 of the fourth N-type semiconductor region N4 is arranged parallel to the third side 6 of the semiconductor substrate 1 and the third side of the semiconductor substrate 1 is more than the fourth and sixth sides 24 and 26. 6 is arranged near. The third side 23 of the fourth N-type semiconductor region N4 is arranged in parallel to a part of the lower side of the first side 21. The fourth side 24 of the fourth N-type semiconductor region N4 is arranged in parallel with a part of the left side of the second side 22. The fifth side 25 of the fourth N-type semiconductor region N4 is arranged in parallel with a part of the upper side of the first side 21. The sixth side 26 of the fourth N-type semiconductor region N4 is arranged in parallel with a part on the right side of the second side 22.

As shown in FIGS. 3 and 4, the fourth N-type semiconductor region N4 has a first interval W1 with respect to the first N-type semiconductor region N1 and is the same as the second N-type semiconductor region N2. A first portion N4a formed to a depth and a second portion N4b having a second interval W2 smaller than the first interval W1 with respect to the first N-type semiconductor region N1. I have. The depth of the second portion N4b of the fourth N-type semiconductor region N4 with respect to the one main surface 2 of the semiconductor substrate 1 is deeper than the depth of the first portion N4a. The second portion N4b of the fourth N-type semiconductor region N4 is formed by diffusing N-type impurities deeper than the first portion N4a of the fourth N-type semiconductor region N4.
As apparent from FIG. 5, when viewed in a plane, that is, when viewed from a direction perpendicular to one main surface 2 of the semiconductor substrate 1, the second portion N4b is located at the lower left corner of the fourth N-type semiconductor region N4. It is arranged in the vicinity. The shortest distance L2 between the second portion N4b of the fourth N-type semiconductor region N4 and the second N-type semiconductor region N2 is the first portion N4a of the fourth N-type semiconductor region N4 and the second N The distance is determined to be greater than the shortest distance L1 between the type semiconductor region N2. Also, in plan view, the second portion N4b of the fourth N-type semiconductor region N4 includes the inclined fourth side 12 of the second N-type semiconductor region N2 and the third N-type semiconductor region N3. Is spaced apart from the first portion N4a of the fourth N-type semiconductor region N4 with respect to the opposite side of the inclined third side 18.
The second portion N4b of the fourth N-type semiconductor region N4 provided according to the present invention has a function of improving the trigger sensitivity without increasing or suppressing the malfunction of the bidirectional thyristor based on residual carriers.

  As is apparent from FIGS. 2 to 5, the second and third N-type semiconductor regions N2 and N3 are arranged so as not to overlap each other in plan view. Thus, the first main having the first polarity is constituted by the second N-type semiconductor region N2, the first P-type semiconductor region P1, the first N-type semiconductor region N1, and the second P-type semiconductor region P2. A thyristor portion is formed, and the first portion N3a, the second P-type semiconductor region P2, the first N-type semiconductor region N1, and the first P-type semiconductor region P1 of the third N-type semiconductor region N3 are the first. A second main thyristor portion having a polarity of 2 is constructed. The second N-type semiconductor region N4, the first P-type semiconductor region P1, the first N-type semiconductor region N1, the second P-type semiconductor region P2, and the second N-type semiconductor region N3 The portion N3b constitutes an auxiliary thyristor portion, that is, a gate mechanism portion.

  The first main electrode T1 made of metal has first, second, third, fourth, fifth and sixth sides 31, 32, 33, 34, 35, 36 as shown in FIG. As a whole, it is formed in an inverted L-shaped pattern, and is connected to both the first P-type semiconductor region P1 and the second N-type semiconductor region N2 on one main surface 2 of the semiconductor substrate 1. That is, the first main electrode T1 includes a trapezoidal first portion T1a substantially corresponding to the trapezoidal second N-type semiconductor region N2 constituting the first main thyristor portion, and the second main thyristor portion. And a trapezoidal second portion T1b substantially corresponding to the first portion N3a of the third N-type semiconductor region N3 to be formed. The first side 31 of the first main electrode T1 is arranged in parallel to the first side 9 of the second N-type semiconductor region N2, and the second side 32 is the first of the third N-type semiconductor region N3. The third side 33 is arranged in parallel to the second side 17 of the third N-type semiconductor region N3, and the fourth side 34 is arranged in the fourth N-type semiconductor region N4. The fifth side 35 is arranged on the right side in parallel with the second side 32 of the first main electrode T1, and the fifth side 35 is located on the second side 10 above the second side 10 of the second N-type semiconductor region N2. The sixth side 36 is arranged in parallel to the fourth side 11 on the right side of the fourth side 11 of the second N-type semiconductor region N2. Note that the first portion T1a of the first main electrode T1 is connected to the second N-type semiconductor region N2, and is formed on the semiconductor substrate 1 through the through hole 8 of the second N-type semiconductor region N2. It is also connected to a first P-type semiconductor region P1 exposed on one surface 2. The second portion T1b of the first main electrode T1 extends onto the third N-type semiconductor region N3 and is connected to the first P-type semiconductor region P1.

  The second main electrode T2 made of metal is disposed on the entire or substantially entire other main surface 3 of the semiconductor substrate 1 so as to oppose the entire first main electrode T1 and the gate electrode G, and the second P It is connected to both the type semiconductor region P2 and the third N type semiconductor region N3.

The gate electrode G made of metal is formed in a quadrilateral shape having first, second, third and fourth sides 41, 42, 43, 44 as shown in FIG. Is connected to both the fourth N-type semiconductor region N4 and the first P-type semiconductor region P1. The first side 41 of the gate electrode G is arranged in parallel to the first side 21 of the fourth N-type semiconductor region N4, and the second side 42 is the second side of the fourth N-type semiconductor region N4. The third side 43 is arranged in parallel to the side 22, the third side 43 is arranged in parallel to the third side 23 of the fourth N-type semiconductor region N 4, and the fourth side 44 is arranged in the fourth N-type semiconductor region N 4. The fourth and sixth sides 24 and 26 are arranged in parallel. As viewed in plan, most of the gate electrode G is disposed inside the fourth N-type semiconductor region N4, and only the upper left corner of the gate electrode G protrudes from the fourth N-type semiconductor region N4 to the first. Connected to the P-type semiconductor region P1. That is, the upper part of the third side 43 of the gate electrode G and the left part of the fourth side 44 protrude from the fourth N-type semiconductor region N4.

  Next, the operation of the bidirectional thyristor according to the first embodiment shown in FIGS. The basic operations of the first to fourth modes of the bidirectional thyristor according to the first embodiment are the same as those of the conventional bidirectional thyristor shown in FIG. Therefore, the description of the basic operation of the first to fourth modes of the bidirectional thyristor of Embodiment 1 is omitted. In the description of the operation of the bidirectional thyristor according to the first embodiment, FIG. In the following description of the operation, each semiconductor region and electrode may be indicated only by reference numerals in the drawings.

The bidirectional thyristor according to the first embodiment exhibits a special effect in the second and third modes (modes II and III).
In the second and third modes (modes II and III), the first portion N4a of the fourth N-type semiconductor region N4 of the bidirectional thyristor according to the first embodiment includes the first P-type semiconductor region P1 and the second portion Since the first main electrode T1 connected to both the N-type semiconductor region N2 is closer to the second portion N4b than the first main electrode T1, the first portion N4a of the fourth N-type semiconductor region N4 starts the gate trigger. Acts as a point. However, since the second portion N4b of the fourth N-type semiconductor region N4 is closer to the first N-type semiconductor region N1 than the first portion N4a, the ON operation in the gate mechanism portion (auxiliary thyristor portion). Gradually spreads favorably from the first portion N4a to the second portion N4b. That is, the injection of minority carriers (electrons) from the fourth N-type semiconductor region N4 into the first P-type semiconductor region P1 first starts from the first portion N4a of the fourth N-type semiconductor region N4. Eventually, the second portion N4b is also used, and the minority carrier injection amount from the second portion N4b is significantly larger than the minority carrier (electron) injection amount from the first portion N4a. Accordingly, the main on-operation region of the gate mechanism portion (auxiliary thyristor portion) is the second portion N4b of the fourth N-type semiconductor region N4, the first P-type semiconductor region P1, and the first in the second mode. The third mode includes an N-type semiconductor region N1 and a second P-type semiconductor region P2. In the third mode, the second portion N4b of the fourth N-type semiconductor region N4, the first P-type semiconductor region P1, and the first It consists of an N-type semiconductor region N1, a second P-type semiconductor region P2, and a third semiconductor region N3. When the gate mechanism portion (auxiliary thyristor portion) is turned on in the second mode, the on state is propagated to the first main thyristor portions (N2, P1, N1, P2). Further, when the gate mechanism portion (auxiliary thyristor portion) is turned on in the third mode, the on state is spread to the second main thyristor portions (P1, N1, P2, N3). When the ON operation in the gate mechanism portion (auxiliary thyristor portion) is satisfactorily achieved, the gate current can be reduced and the trigger sensitivity is improved.

The second interval W2 between the second portion N4b of the fourth N-type semiconductor region N4 and the first N-type semiconductor region N1 is the distance between the first portion N4a and the first N-type semiconductor region N1. The trigger sensitivity of the bidirectional thyristor is mainly determined based on the second portion N4b of the fourth N-type semiconductor region N4, and is smaller than the trigger sensitivity of the conventional bidirectional thyristor. high. That is, the trigger sensitivity of the bidirectional thyristor of the present embodiment is such that the fourth N-type semiconductor region N4 and the first N-type semiconductor region N1 are provided without providing the second portion N4b of the fourth N-type semiconductor region N4. Is higher than the trigger sensitivity of the conventional bidirectional thyristor having the first interval W1 as the minimum interval.

As described above, in the conventional bidirectional thyristor, the trigger sensitivity and the commutation critical voltage increase rate (dv / dt) c are in a trade-off relationship. On the other hand, in the second portion N4b of the fourth N-type semiconductor region N4 contributing to the improvement of the trigger sensitivity of the present embodiment, there are residual carriers (holes) that cause a malfunction of the bidirectional thyristor. It is formed at a position away from the part. Note that the portion where many residual carriers that cause malfunction of the bidirectional thyristor are present in the fourth N-type semiconductor region N2 inclined in the first N-type semiconductor region N1 as viewed in plan. This is a portion corresponding to the opposite side of the inclined third side 18 of the side 12 and the third N-type semiconductor region N3, that is, the central portion of the semiconductor substrate 1. In this way, if the second portion N4b of the fourth N-type semiconductor region N4 that contributes to the improvement of the trigger sensitivity is formed at a position away from the portion where the residual carriers that cause the malfunction exist, the trigger sensitivity. In spite of the improvement, the bidirectional thyristor is also prevented from malfunctioning by acting on the first main thyristor portion or the second main thyristor portion based on the remaining carriers. Therefore, it is possible to improve the trigger sensitivity without or suppressing the trade-off relationship between the trigger sensitivity and the commutation critical voltage increase rate (dv / dt) c.
In addition, the mutual sensitivity between the first main thyristor portion and the second main thyristor portion is not increased or suppressed, and the trigger sensitivity of the bidirectional thyristor and the critical voltage increase rate (dv / dt) c during commutation are set. The relationship can be improved.

More specifically, in the third mode (mode III), the bidirectional thyristor according to the first embodiment includes the second main electrode T2 based on the first main electrode T1 as in FIG. 1C. Negative potential, the gate electrode G becomes negative potential. When a gate trigger signal is applied to the gate electrode G, a gate trigger current I _GT flows from the first main electrode T1 to the gate electrode G. As a result, a voltage drop occurs in the first P-type semiconductor region P1, the PN junction between the fourth N-semiconductor region N4 and the first P-type semiconductor region P1 is in a forward bias state, and the fourth N-type Electrons are injected from the semiconductor region N4 into the first P-type semiconductor region P1, and part of the electrons enter the first N-type semiconductor region N1. As described above, the injection of electrons from the fourth N-type semiconductor region N4 into the first P-type semiconductor region P1 starts from the first portion 4a of the fourth N-type semiconductor region N4, and then the second It spreads to the part 4b. As a result, the auxiliary thyristor portion composed of N4b, P1, N1, P2, and N3 is turned on, and the on state is spread to the second main thyristor portion composed of P1, N1, P2, and N3. The ON state spillover from the auxiliary thyristor portion to the second main thyristor portion proceeds in the same manner as in FIG.

Even if the ON state of the second main thyristor portion in the third mode (mode III) ends and the main current I2 in the second direction becomes zero, carriers (holes) remain in the semiconductor substrate 1. To do. That is, many residual carriers exist mainly in the first N semiconductor region N1. A reverse voltage having a large voltage increase rate (dv / dt) in the presence of residual carriers, that is, a positive power supply voltage or noise with reference to the first main electrode T1 as in FIG. 1 (A) or (B). When applied to the second main electrode T2, the remaining carriers act as a trigger, and there is a possibility that the first main thyristor portion composed of N2, P1, N1, and P2 is turned on.

However, in this embodiment, in order to improve the trigger sensitivity, the trigger sensitivity is increased at a position away from the portion where the remaining carriers that cause malfunction are present without forming the entire fourth N semiconductor region N4 deeply. Since the second portion N4b for improving is provided and the on-operation of the auxiliary thyristor is started satisfactorily, the malfunction of the main thyristor portion based on the remaining carrier does not increase even though the trigger sensitivity is improved. .

The bidirectional thyristor according to the first embodiment is in the second mode (mode II), and the second main electrode T2 is set to a positive potential with reference to the first main electrode T1 as in FIG. When a negative gate trigger signal is applied to G, a gate trigger current I _GT flows from the first main electrode T1 to the gate electrode G. As a result, a voltage drop occurs in the first P-type semiconductor region P1, the PN junction between the fourth N-semiconductor region N4 and the first P-type semiconductor region P1 is in a forward bias state, and the fourth N-type Electrons are injected from the semiconductor region N4 into the first P-type semiconductor region P1, and part of the electrons enter the first N-type semiconductor region N1. As already described, the injection of electrons from the first portion N4a of the fourth N-type semiconductor region N4 into the first P-type semiconductor region P1 starts, and then the auxiliary thyristor portion comprising N4b, P1, N1, and P2 Turns on. The on-state of the auxiliary thyristor part spreads to the first main thyristor part composed of N2, P1, N1, and P2 by the same operation as in FIG.
Also in the second mode (mode II), the second portion N4b of the fourth N-type semiconductor region N4 contributes to the improvement of trigger sensitivity.

Even if the ON state of the first main thyristor portion in the second mode (mode II) ends and the main current I1 in the first direction becomes zero, carriers remain in the first N semiconductor region N1. A reverse voltage having a large voltage increase rate (dv / dt) in the presence of residual carriers (holes), that is, a negative power source with reference to the first main electrode T1 as in FIG. 1 (C) or (D). When voltage or noise is applied to the second main electrode T2, the remaining carriers act as a trigger, and the second main thyristor portion composed of P1, N1, P2, and N3 may be erroneously turned on. However, as described above, in this embodiment, the fourth N semiconductor region N4 is not formed to a uniform depth, and the trigger sensitivity is improved to a position away from the position where the residual carriers that cause a malfunction exist. Since the second portion N4b of the fourth N-type semiconductor region N4 is provided, the second mode (mode II) to the third mode (mode II) despite the increased trigger sensitivity. Malfunctions based on residual carriers when switching to mode III) are unlikely to occur. Incidentally, the same effect can be obtained when switching from the first mode (mode I) to the third mode (mode III).

  Next, the bidirectional thyristor according to the second embodiment will be described with reference to FIGS. However, in the bidirectional thyristor of the second embodiment, the third N-type semiconductor region N3 of the bidirectional thyristor of the first embodiment shown in FIGS. 2 to 5 is modified and a gate trigger current ineffective portion suppressing portion 50 is added. Others are the same as the bidirectional thyristor of the first embodiment. Therefore, in FIGS. 6 and 7, substantially the same parts as in FIGS.

The third N-type semiconductor region N3 of FIGS. 6 and 7 has a first portion N3b ′ formed relatively shallow and a second portion N3c formed relatively deep. The first portion N3b ′ of the third N-type semiconductor region N3 has a relatively wide third interval W3 with respect to the first N-type semiconductor region N1, and extends from the other main surface 3 of the semiconductor substrate 1. It is relatively shallow and diffused. The second portion N3c of the third N-type semiconductor region N3 has a fourth interval W3 smaller than the third interval W3 with respect to the first N-type semiconductor region N1, and the other portion of the semiconductor substrate 1 Diffused relatively deeply from the main surface 3. Further, in the cross section showing the portion corresponding to the line B′-B ′ of the bidirectional thyristor of Example 2, the second portion N3c of the third N-type semiconductor region N3 and the second N-type semiconductor region N2 The shortest distance L4 is determined to be larger than the shortest distance L3 between the first portion N3b ′ of the third N-type semiconductor region N3 and the second N-type semiconductor region N2. Further, the second portion N3c of the third N-type semiconductor region N3 is arranged so as to overlap (oppose) the second portion N4b of the fourth N-type semiconductor region N4 when viewed in plan, and the third portion The second side 17 and the fourth side 19 of the N-type semiconductor region N3 are arranged on the corner sides. In FIG. 7, the second portion N3c of the third N-type semiconductor region N3 is formed so as to include the second portion N4b of the fourth N-type semiconductor region N4 in plan view. It can also be formed in a shape included in the second portion N4b of the fourth N-type semiconductor region N4, the same as or opposite to the second portion N4b of the fourth N-type semiconductor region N4.

  The second portion N3c of the third N-type semiconductor region N3 is closer to the first N-type semiconductor region N1 than the first portion N3b ′. Accordingly, electrons injected from the second portion N3c of the third N-type semiconductor region N3 into the second P-type semiconductor region P2 are second to second electrons from the first portion N3b ′ of the third N-type semiconductor region N3. It enters the first N-type semiconductor region N1 more easily than the electrons injected into the P-type semiconductor region P2. Along with this, holes enter the first N-type semiconductor region N1 from the second P-type semiconductor region P2. Accordingly, the trigger sensitivity of the second portion N3c is higher than the trigger sensitivity of the first portion N3b ′. Furthermore, in Example 2, in addition to the entry of electrons injected from the second portion N4b of the fourth N-type semiconductor region N4 into the first P-type semiconductor region P1 into the first N-type semiconductor region N1. The electrons injected from the second portion N3c of the third N-type semiconductor region N3 into the second P-type semiconductor region P2 enter the first N-type semiconductor region N1. Therefore, according to the second embodiment, a bidirectional thyristor having a trigger sensitivity higher than that of the first embodiment can be provided. In addition, since the second portion N3c of the third N-type semiconductor region N3 that contributes to the improvement of the trigger sensitivity is away from the central portion of the semiconductor substrate 1 where residual carriers that cause malfunctions are present, the trigger sensitivity Despite the improvement, the malfunction of the main thyristor does not increase. That is, even if the trigger sensitivity is improved, the decrease in the critical voltage increase rate during commutation (dv / dt) c does not occur or decreases, and the trade between the trigger sensitivity and the critical voltage increase rate during commutation (dv / dt) c. The trigger sensitivity can be improved without or with an off relationship.

The reactive trigger suppression portion 50 of the gate trigger current of the second embodiment has the same function as the reactive trigger suppression portion of the gate trigger current disclosed in Patent Document 2, and reduces the reactive portion of the gate trigger current. Contribute. The gate trigger current reactive portion suppressing portion 50 is formed of an N-type semiconductor region, and the gate electrode G and the first electrode in the first P-type semiconductor region P1 are exposed to one main surface 2 of the semiconductor substrate 1. The first main electrode T1 is disposed between the second N-type semiconductor region N2 and the first P-type semiconductor region P1. The reactive portion suppressing portion 50 of the gate trigger current of the second embodiment is formed at the same depth as the second portion N4b of the fourth N-type semiconductor region N4 in order to simplify the manufacture. Alternatively, the reactive component suppression portion 50 can be formed deeper than the second portion N4b of the fourth N-type semiconductor region N4, or can be formed so as to reach the first N-type semiconductor region N1.

  The reactive part suppressing portion 50 of the gate trigger current has a rectangular planar shape and is disposed between the first main electrode T1 and the gate electrode G provided as shown in FIG. ing. In addition, the planar shape of the ineffective portion suppressing portion 50 can be transformed into another pattern such as an arc shape or a U shape.

  For example, in the first and fourth modes in the bidirectional thyristor of the first embodiment shown in FIGS. 2 to 5, the second N is applied from the portion where the gate electrode G is in contact with the first P-type semiconductor region P <b> 1. The active component Ia of the trigger current flowing under or in the semiconductor region N2 toward the first main electrode T1 and the portion where the gate electrode G is in contact with the first P-type semiconductor region P1 It flows toward the first main electrode T1 without passing under or inside the second N-type semiconductor region N2, such as flowing toward the first main electrode T1 through the exposed surface (surface) of the semiconductor region P1. A reactive component Ib of the trigger current is generated. On the other hand, in the bidirectional thyristor of the second embodiment shown in FIGS. 6 to 7, the reactive component suppression component 50 is provided in the path through which the reactive component Ib of the trigger current flows. Become.

  Further, in the second and third modes in the bidirectional thyristor of Embodiment 1 shown in FIGS. 2 to 5, the first main electrode T1 is changed from the portion in contact with the first P-type semiconductor region P1. The active component Ia of the trigger current flowing toward the gate electrode G through or under the four N-type semiconductor regions N4 and the portion where the first main electrode T1 is in contact with the first P-type semiconductor region P1 Of the trigger current that flows toward the gate electrode G without passing under or in the second N-type semiconductor region N2, such as flowing from the first through the exposed surface (surface) of the P-type semiconductor region P1 toward the gate electrode G. An ineffective component Ib is generated. In contrast, in the bidirectional thyristor according to the second embodiment shown in FIGS. 6 to 7, the reactive component suppression component 50 is provided in the path through which the reactive component Ib of the trigger current flows, so that the reactive component Ib of the trigger current is reduced.

The gate trigger current reactive portion suppressing portion 50 of the second embodiment contributes to the reduction of the reactive component Ib of the gate trigger current and contributes to the improvement of the trigger sensitivity. However, the rate of increase in the seaside voltage during commutation (dv / dt) c is not deteriorated. Therefore, according to the second embodiment, a bidirectional thyristor having a trigger sensitivity higher than that of the first embodiment can be provided. That is, the trigger sensitivity can be improved while suppressing malfunctions based on the remaining carriers.

  6 and 7 may be formed of an insulating material such as silicon oxide, or may be replaced with a hole formed in the semiconductor substrate 1. 6 and 7 can also be provided in the bidirectional thyristor shown in FIGS.

  Next, the bidirectional thyristor of Embodiment 3 will be described with reference to FIG. However, the bidirectional thyristor according to the third embodiment is provided with a notch 60 on the fourth side 44 of the gate electrode G of the bidirectional thyristor according to the first embodiment shown in FIGS. Since the configuration is the same as that of the thyristor, the same reference numerals in FIG. 8 denote the same parts as in FIGS. 2 to 5, and a description thereof will be omitted.

The cutout 60 provided in the gate electrode G in FIG. 8 is formed by cutting out the upper left (a part of the fourth side 44) of the square gate electrode G in FIG. The area where the gate electrode G having the notch 60 in FIG. 8 is in contact with the first P-type semiconductor region P1 is larger than the area where the square gate electrode G in FIG. 2 is in contact with the first P-type semiconductor region P1. small. Further, the gate electrode G having the notch 60 of FIG. 8 is formed in the first P-type semiconductor region P1 only in the vicinity of the intersection of the fourth and fifth sides 24 and 25 of the fourth N-type semiconductor region N4. In contact. Therefore, the gate flows from the gate electrode G in the direction of the second portion T1b of the first main electrode T1 through the first P-type semiconductor region P1 without passing through or under the second N-type semiconductor region N2. The reactive component Ib of the trigger current can be reduced. If the reactive component Ib of the gate trigger current is reduced, the trigger sensitivity is improved. In addition, the notch 60 does not deteriorate the coastal voltage increase rate (dv / dt) c during commutation. Therefore, according to the third embodiment, the trigger sensitivity can be improved while suppressing malfunctions based on the remaining carriers.
Note that the notch 60 provided on the fourth side 44 of the gate electrode G can be transformed into a recess or the like.

Next, the bidirectional thyristor of Embodiment 4 will be described with reference to FIG. However, the bidirectional thyristor according to the fourth embodiment is obtained by modifying a part of the bidirectional thyristor according to the second embodiment shown in FIG. 6 and the other configuration is the same as the bidirectional thyristor according to the second embodiment. In FIG. 6, substantially the same parts as those in FIG.

The bidirectional thyristor of Example 4 in FIG. 9 includes a second portion N4b having a higher N-type impurity concentration than the first portion N4a in the second portion N4b region of the fourth N-type semiconductor region N4 in FIG. ′ And a second portion N3c ′ having a higher N-type impurity concentration than the first portion N3b ′ is provided in the region of the second portion N3c of the third N-type semiconductor region N3 in FIG. Is the same as FIG.

As shown in FIG. 9, when the N-type impurity concentration of the second portion N4b ′ of the fourth N-type semiconductor region N4 is higher than that of the first portion N4a, the second P-type semiconductor starts from the second portion N4b ′. The efficiency of injecting minority carriers (electrons) into the region P1 is higher than that of the first portion N4a, and the trigger sensitivity is improved. The second portion N4b ′ that contributes to the improvement in trigger sensitivity is away from the second N-type semiconductor region N2 and the central portion of the semiconductor substrate 1 where residual carriers that cause malfunctions are present. Although the trigger sensitivity is improved as in the first to third embodiments, malfunction based on the remaining carriers is unlikely to occur.

As shown in FIG. 9, when the N-type impurity concentration of the second portion N3c ′ of the third N-type semiconductor region N3 is higher than that of the first portion N3b ′, the second portion N3c ′ to the second P-type The efficiency of injection of minority carriers (electrons) into the semiconductor region P2 is higher than that of the first portion N3b ′, and the trigger sensitivity is improved. The second portion N3c ′ that contributes to the improvement in trigger sensitivity is away from the second N-type semiconductor region N2 and the central portion of the semiconductor substrate 1 where residual carriers that cause malfunctions are present. Although the trigger sensitivity is improved as in the first to third embodiments, malfunction based on the remaining carriers is unlikely to occur.

In FIG. 9, the N-type impurity concentrations of both the second portion N4b ′ of the fourth N-type semiconductor region N4 and the second portion N3c ′ of the third N-type semiconductor region N3 are set to the respective first portions N4a. N3b ′, which is higher than N3b ′, but only in one of the second portion N4b ′ of the fourth N-type semiconductor region N4 and the second portion N3c ′ of the third N-type semiconductor region N3 The concentration can also be increased.
As shown in FIG. 9, when the N-type impurity concentration of the second portion N4b ′ of the fourth N-type semiconductor region N4 is higher than that of the first portion N4a, the fourth N-type semiconductor region N4 The interval W2 between the second portion N4b ′ and the first N-type semiconductor region N1 is the same as the interval W1 between the first portion N4a of the fourth N-type semiconductor region N4 and the first N-type semiconductor region N1. You can also Even when W2 = W1, since the N-type impurity concentration of the second portion N4b ′ of the fourth N-type semiconductor region N4 is increased, the trigger sensitivity is improved and the same effects as in the first to third embodiments are achieved. Can be obtained.
Similarly, when the N-type impurity concentration of the second portion N3c ′ of the third N-type semiconductor region N3 is made higher than that of the first portion N3b ′, the second N-type semiconductor region N3 second The interval W4 between the portion N4c ′ and the first N-type semiconductor region N1 is made equal to the interval W3 between the first portion N3b ′ of the third N-type semiconductor region N3 and the first N-type semiconductor region N1. You can also. Even if W4 = W3, since the N-type impurity concentration of the second portion N4c ′ of the third N-type semiconductor region N3 is increased, the trigger sensitivity is improved, and the same effects as in the first to third embodiments are achieved. Can get

The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) In each embodiment, the second portion N4b of the fourth N-type semiconductor region N4 is provided by changing the diffusion depth of the N-type impurity. Instead, one main surface 2 of the semiconductor substrate 1 is provided. A recess extending in the vertical direction (vertical direction) of the bidirectional thyristor is provided in advance in a portion corresponding to the second portion N4b, and the second portion N4b is formed by diffusing N-type impurities through the recess. A second interval W2 narrower than the interval W1 can be obtained.
(2) The second N-type semiconductor region N2 having a large number of holes 8 as a whole and formed in a mesh shape as viewed in a plane can be transformed into a lattice shape or a comb shape as viewed in a plane. . Further, the hole 8 can be omitted from the second N-type semiconductor region N2.
(3) The patterns of the semiconductor regions N1, N2, N3, N4, P1, P2, and the first and second main electrodes T1, T2 and the gate electrode G can be arbitrarily modified.
(4) Instead of changing the interval between the fourth N-type semiconductor region N4 and the first N-type semiconductor region N1 stepwise as shown in FIG. 3, the interval is changed from the second N-type semiconductor region N2. The distance can be gradually reduced continuously or stepwise as the distance increases. Similarly, instead of changing the interval between the third N-type semiconductor region N3 and the first N-type semiconductor region N1 stepwise as shown in FIG. 6, this interval is separated from the second N-type semiconductor region N2. Can be gradually reduced continuously or stepwise. Similarly, as shown in FIG. 9, the impurity concentration of the fourth N-type semiconductor region N4 and / or the third N-type semiconductor region N3 can be increased continuously or stepwise.

FIG. 3 is a cross-sectional view showing a portion corresponding to the line AA of FIG. 2 in order to explain first to fourth modes of the bidirectional thyristor. It is a top view which shows the bidirectional thyristor of Example 1 according to this invention. It is sectional drawing which shows the part corresponded to the BB line of FIG. It is sectional drawing which shows the part corresponded to CC line of FIG. FIG. 3 is a plan view showing one main surface of the semiconductor substrate of FIG. 2. It is sectional drawing which shows the bidirectional thyristor of Example 2 according to this invention in the same position as FIG. It is a top view which shows one main surface of the semiconductor substrate of FIG. It is a top view which shows the bidirectional thyristor of Example 3 according to this invention similarly to FIG. FIG. 7 is a cross-sectional view showing a bidirectional thyristor of Example 4 according to the present invention in the same manner as FIG. 6.

Explanation of symbols

1 semiconductor substrate T1 first main electrode T2 second main electrode G gate electrode N1 first N-type semiconductor region (first semiconductor region)
P1 First P-type semiconductor region (second semiconductor region)
P2 Second P-type semiconductor region (third semiconductor region)
N2 Second N-type semiconductor region (fourth semiconductor region)
N3 Third N-type semiconductor region (fifth semiconductor region)
N4 Fourth N-type semiconductor region (sixth semiconductor region)
N4a first part N4b second part

Claims (7)

A semiconductor substrate (1), a first main electrode (T1) and a gate electrode (G) provided on one main surface (2) of the semiconductor substrate (1), and the other of the semiconductor substrate (1) A second main electrode (T2) provided on the main surface (3) of
The semiconductor substrate (1) is arranged adjacent to a first semiconductor region (N1) of a first conductivity type and one main surface side of the first semiconductor region (N1), and the semiconductor substrate (1) Of the second conductivity type opposite to the first conductivity type having a portion exposed on the one main surface (2) of the second semiconductor region (P1), and the first semiconductor region (N1) ) Adjacent to the other main surface side and having a portion exposed to the other main surface (3) of the semiconductor substrate (1), a third semiconductor region (P2) of the second conductivity type And a fourth semiconductor of the first conductivity type having a portion that is disposed adjacent to the second semiconductor region (P1) and exposed to the one main surface (12) of the semiconductor substrate (1). A region (N2) and the other main surface of the semiconductor substrate (1) disposed adjacent to the third semiconductor region (P2) 3) a first conductivity type fifth semiconductor region (N3) having a portion exposed to 3), and the one of the semiconductor substrates (1) disposed adjacent to the second semiconductor region (P1) A sixth semiconductor region (N4) of the first conductivity type having a portion exposed to the main surface (2) of
The first main electrode (T1) is connected to both the second semiconductor region (P1) and the fourth semiconductor region (N2);
The second main electrode (T2) is connected to both the third semiconductor region (P2) and the fifth semiconductor region (N3);
In the bidirectional thyristor in which the gate electrode (G) is connected to both the second semiconductor region (P1) and the sixth semiconductor region (N4),
The sixth semiconductor region (N4) has a first portion (N4a) having a first interval (W1) with respect to the first semiconductor region (N1), and the first semiconductor region A second portion (N4b) having a second interval (W2) smaller than the first interval (W1) with respect to (N1),
The second portion (N4b) of the sixth semiconductor region (N4) and the fourth semiconductor region (N2) when viewed from a direction perpendicular to one surface (2) of the semiconductor substrate (1). ) Is shorter than the shortest distance (L1) between the first portion (N4a) of the sixth semiconductor region (N4) and the fourth semiconductor region (N2). A bi-directional thyristor characterized by being largely determined. A first portion (N3b ′) in which the fifth semiconductor region (N3) has a third interval (W3) with respect to the first semiconductor region (N1); and the first semiconductor The region (N1) has a fourth interval (W4) smaller than the third interval (W3) and faces the second portion (N4b) of the sixth semiconductor region (N4). A second portion (N3c) disposed in the
The second portion (N3c) and the fourth semiconductor region (N3c) of the fifth semiconductor region (N3) when viewed from a direction perpendicular to one main surface (2) of the semiconductor substrate (1). N2) is the shortest distance (L3) between the first portion (N3b ′) of the fifth semiconductor region (N3) and the fourth semiconductor region (N2). The bidirectional thyristor according to claim 1, wherein the bidirectional thyristor is determined to be larger than. A semiconductor substrate (1), a first main electrode (T1) and a gate electrode (G) provided on one main surface (2) of the semiconductor substrate (1), and the other of the semiconductor substrate (1) A second main electrode (T2) provided on the main surface (3) of
The semiconductor substrate (1) is arranged adjacent to a first semiconductor region (N1) of a first conductivity type and one main surface side of the first semiconductor region (N1), and the semiconductor substrate (1) Of the second conductivity type opposite to the first conductivity type having a portion exposed on the one main surface (2) of the second semiconductor region (P1), and the first semiconductor region (N1) ) Adjacent to the other main surface side and having a portion exposed to the other main surface (3) of the semiconductor substrate (1), a third semiconductor region (P2) of the second conductivity type And a fourth semiconductor of the first conductivity type having a portion that is disposed adjacent to the second semiconductor region (P1) and exposed to the one main surface (12) of the semiconductor substrate (1). A region (N2) and the other main surface of the semiconductor substrate (1) disposed adjacent to the third semiconductor region (P2) 3) a first conductivity type fifth semiconductor region (N3) having a portion exposed to 3), and the one of the semiconductor substrates (1) disposed adjacent to the second semiconductor region (P1) A sixth semiconductor region (N4) of the first conductivity type having a portion exposed to the main surface (2) of
The first main electrode (T1) is connected to both the second semiconductor region (P1) and the fourth semiconductor region (N2);
The second main electrode (T2) is connected to both the third semiconductor region (P2) and the fifth semiconductor region (N3);
In the bidirectional thyristor in which the gate electrode (G) is connected to both the second semiconductor region (P1) and the sixth semiconductor region (N4),
The fifth semiconductor region (N3) is opposed to the sixth semiconductor region (N4) and opposed to the first semiconductor region (N1) with a first interval (W3). The first portion (N3b ') facing the sixth semiconductor region (N4) and smaller than the first interval (W3) with respect to the first semiconductor region (N1) A second portion (N3c) facing each other with a second interval (W4),
The second portion (N3c) of the fifth semiconductor region (N3) and the fourth semiconductor region (N2) when viewed from a direction perpendicular to one surface (2) of the semiconductor substrate (1). ) Is shorter than the shortest distance (L3) between the first portion (N3b ′) of the fifth semiconductor region (N3) and the fourth semiconductor region (N2). Is a bi-directional thyristor that has been determined to be greatly determined. The bidirectional thyristor according to claim 1, 2 or 3, wherein a portion (50) for suppressing an ineffective portion of the gate trigger current is disposed in the second semiconductor region (P1). 5. The bidirectional thyristor according to claim 1, wherein the gate electrode is provided with a notch for reducing an ineffective portion of a gate trigger current. 6. A semiconductor substrate (1), a first main electrode (T1) and a gate electrode (G) provided on one main surface (2) of the semiconductor substrate (1), and the other of the semiconductor substrate (1) A second main electrode (T2) provided on the main surface (3) of
The semiconductor substrate (1) is arranged adjacent to a first semiconductor region (N1) of a first conductivity type and one main surface side of the first semiconductor region (N1), and the semiconductor substrate (1) Of the second conductivity type opposite to the first conductivity type having a portion exposed on the one main surface (2) of the second semiconductor region (P1), and the first semiconductor region (N1) ) Adjacent to the other main surface side and having a portion exposed to the other main surface (3) of the semiconductor substrate (1), a third semiconductor region (P2) of the second conductivity type And a fourth semiconductor of the first conductivity type having a portion that is disposed adjacent to the second semiconductor region (P1) and exposed to the one main surface (12) of the semiconductor substrate (1). A region (N2) and the other main surface of the semiconductor substrate (1) disposed adjacent to the third semiconductor region (P2) 3) a first conductivity type fifth semiconductor region (N3) having a portion exposed to 3), and the one of the semiconductor substrates (1) disposed adjacent to the second semiconductor region (P1) A sixth semiconductor region (N4) of the first conductivity type having a portion exposed to the main surface (2) of
The first main electrode (T1) is connected to both the second semiconductor region (P1) and the fourth semiconductor region (N2);
The second main electrode (T2) is connected to both the third semiconductor region (P2) and the fifth semiconductor region (N3);
In the bidirectional thyristor in which the gate electrode (G) is connected to both the second semiconductor region (P1) and the sixth semiconductor region (N4),
The sixth semiconductor region (N4) has a first portion (N4a ′) having a first impurity concentration and a second impurity concentration higher than the first impurity concentration. A second portion (N4b ′),
The second portion (N4b ′) of the sixth semiconductor region (N4) and the fourth semiconductor region (the fourth semiconductor region (N4)) when viewed from a direction perpendicular to one surface (2) of the semiconductor substrate (1). N2) is the shortest distance (L1) between the first portion (N4a ′) of the sixth semiconductor region (N4) and the fourth semiconductor region (N2). A bidirectional thyristor characterized in that it is determined to be larger. A semiconductor substrate (1), a first main electrode (T1) and a gate electrode (G) provided on one main surface (2) of the semiconductor substrate (1), and the other of the semiconductor substrate (1) A second main electrode (T2) provided on the main surface (3) of
The semiconductor substrate (1) is arranged adjacent to a first semiconductor region (N1) of a first conductivity type and one main surface side of the first semiconductor region (N1), and the semiconductor substrate (1) Of the second conductivity type opposite to the first conductivity type having a portion exposed on the one main surface (2) of the second semiconductor region (P1), and the first semiconductor region (N1) ) Adjacent to the other main surface side and having a portion exposed to the other main surface (3) of the semiconductor substrate (1), a third semiconductor region (P2) of the second conductivity type And a fourth semiconductor of the first conductivity type having a portion that is disposed adjacent to the second semiconductor region (P1) and exposed to the one main surface (12) of the semiconductor substrate (1). A region (N2) and the other main surface of the semiconductor substrate (1) disposed adjacent to the third semiconductor region (P2) 3) a first conductivity type fifth semiconductor region (N3) having a portion exposed to 3), and the one of the semiconductor substrates (1) disposed adjacent to the second semiconductor region (P1) A sixth semiconductor region (N4) of the first conductivity type having a portion exposed to the main surface (2) of
The first main electrode (T1) is connected to both the second semiconductor region (P1) and the fourth semiconductor region (N2);
The second main electrode (T2) is connected to both the third semiconductor region (P2) and the fifth semiconductor region (N3);
In the bidirectional thyristor in which the gate electrode (G) is connected to both the second semiconductor region (P1) and the sixth semiconductor region (N4),
The fifth semiconductor region (N3) has a first portion (N3b ′) having a first impurity concentration and a second impurity concentration higher than the first impurity concentration. A second part (N3c ′)
The second portion (N3c ′) and the fourth semiconductor region (N3c ′) of the fifth semiconductor region (N3) when viewed from a direction perpendicular to one surface (2) of the semiconductor substrate (1). N2) is the shortest distance (L3) between the first portion (N3b ′) of the fifth semiconductor region (N3) and the fourth semiconductor region (N2). A bidirectional thyristor characterized in that it is determined to be larger.

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