TWI657556B - Semiconductor diode assembly and process of fabricating a plurality of semiconductor devices including diodes - Google Patents

Abstract

Transient voltage suppressor (TVS) devices with planar p-n junctions have superior performance in breakdown and current handling. The junction diode assembly formed in the closed trench occupies less wafer area than the junction isolation diode assembly of the prior art. The use of the junction forming the trench fabrication of the diode assembly formed after the formation reduces the manufacturing cost, and the masking step increases program flexibility and enables asymmetric TSV and unidirectional TSV functions.

Description

Semiconductor diode assembly and program for manufacturing a plurality of semiconductor devices including diodes

Overvoltage transients in the form of electrostatic discharge, electromagnetic interference, illumination, or other harmful forms can undesirably strike an integrated circuit (IC) package. Therefore, transient suppression measurements are often required to ensure proper functionality over the life expectancy of the packaged circuit.

In electronic systems where space is severely limited, such as mobile phones, laptops, handheld GPS systems, or digital cameras, transient voltage suppressor (TVS) devices made of semiconductors are used to protect such The only viable option for sensitive IC chips in the system. It is often impractical to incorporate TVS functionality into the wafer to be protected, as the manufacturing process designed for most integrated circuits is not suitable for good TVS performance. For this reason, independent semiconductor TVS devices are still the choice in the industry.

In a TVS device, the p-n junction and the associated depletion region in combination with the resistive element are designed to absorb the damaging energy of the transient attack. Because transients often behave as fast, high voltage pulses, the TVS device is configured to force the p-n junction to break down and thus divert energy through such junctions rather than through the protected circuit.

It is known that TVS devices are based on diffusion lateral p-n junction diodes in germanium wafers consisting of epitaxial germanium on a heavily doped n-type substrate. The bipolar system is fabricated by implanting or diffusing a p-type dopant through a window opening that grows or deposits an oxide layer over one of the crucibles to form a p-n junction under the crucible surface. Thus, one of the p-n junctions is formed to have two portions - a planar portion opposite a fixed distance from the surface of the crucible, and a non-planar cylindrical portion surrounding one of the planar portions extending to the periphery of the crucible surface. These p-n junctions are responsible for bypassing the circuits protected by the protected circuits themselves without permanent damage. In damaging energy.

Applicants observed and recognized that the breakdown voltage of a diffused pn junction often does not reach the theoretical value and varies with the depth of the diffusion region, wherein the shallow junction exhibits a more significant reduction in one of the breakdown voltages, and the reduction is reduced. Due to the radius of curvature of the non-planar, cylindrical portion of the junction, it causes junction breakdown near the surface of the crucible rather than in the planar region of the dipole below the surface. Since the junction breakdown under electrical stress induces a high current density at the limited area bend of the p-n junction, heat will prematurely damage the TVS device.

Using this recognition, Applicants have worked hard to invent (as will be described in detail in the literature) procedures for preparing devices suitable for use in TVS devices having superior performance. A TVS device embodying the present invention includes a circuit path having at least two terminals accessible from a top surface of the device, and at least one (but no more than two) pn junctions along the electrical path, the cross-over faces thereof The area is actually planar and therefore has no fragile points associated with non-planar junctions.

The TVS device embodying the present invention can be a two-way device or a unidirectional device, and the like provides protection against voltage transients and other electrical surges and spikes, wherein the transients are positive or negative. Because the junctions are free of the plane of the cylindrical portion, such devices are capable of absorbing greater transient pulses than known devices at times of the present invention.

Other aspects of the invention include placing a p-n junction in a trench closed column of semiconductor material such that the devices can be implemented in a tiny semiconductor die or wafer. The trench may assume the shape of a ring of a circle, an ellipse, a rectangle, a square, or a polygon, or it may be non-geometric - as long as it forms a closed loop without a gap.

Other aspects of the invention include introducing a dopant into the semiconductor material in a plurality of trenches without the use of a portion of the light-preparing material to cover the die, thereby embodying the device of the present invention relative to the circuit path The two terminals rupture symmetrically. One of the advantages of this is that the devices can be made with less complexity and lower cost.

Another aspect of the present invention is that an asymmetric strike can be achieved by inserting a mask layer. A two-way device that wears voltage. With a further additional mask layer, a one-way device that provides TSV protection only in one direction relative to one of the two terminals can also be implemented.

In summary, the present invention enables a semiconductor device technician to fabricate and use (among other embodiments) a greater amount of energy that can be absorbed in the form of a transient voltage surge than is achievable in the known art. The restored TVS device, because it can achieve a breakdown voltage that is closer to the theoretical value and across the junction of the entire pn junction region. Many of the devices embodying the present invention have terminals that can be individually accessed from their top surface, and thus facilitate device packaging at low cost and high packaging density.

Exemplary embodiments of the present invention are described in the following sections by means of the drawings.

100‧‧‧ wafer/device

110‧‧‧Ditch

111‧‧‧Ditch

120‧‧‧Contacts

121‧‧‧Contacts

130‧‧‧Metal parts/矽 layer (Fig. 3)/heavier doped layer (Fig. 3)

131‧‧‧矽/heavier doped layers

140‧‧‧Window opening/window

150‧‧‧Protective coating

200‧‧‧ wafer/device

210‧‧‧Semiconductor column/channel

220‧‧‧Semiconductor column/channel

230‧‧‧layer/substrate/n+ substrate

231‧‧‧Electrical insulation materials

240‧‧‧layer/n-type epitaxial layer/exfoliation layer

250‧‧‧layer/substrate

260‧‧‧p-n junction

270‧‧‧p-n junction

280‧‧‧ wafer

300‧‧‧p-n face/device

400‧‧‧ device

401‧‧‧p-n junction

500‧‧‧Device/Diode junction

550‧‧‧p-n junction

551‧‧‧p-n junction/diode junction

600‧‧‧ device

660‧‧‧p-n junction

661‧‧‧Semiconductor materials

671‧‧‧ Terminal

672‧‧‧ Terminal

1 depicts a top plan view of one exemplary device embodying aspects of the present invention.

2 depicts a cross-sectional view of one exemplary device embodying aspects of the present invention.

3 depicts a cross-sectional view of another exemplary apparatus embodying aspects of the present invention.

4 depicts a cross-sectional view of another exemplary device embodying aspects of the present invention.

Figure 5 depicts a cross-sectional view of another exemplary apparatus embodying aspects of the present invention.

Figure 6 depicts a cross-sectional view of another exemplary apparatus embodying aspects of the present invention.

Example 1: A symmetric bidirectional transient suppressor

1 depicts a portion of a top surface of an exemplary semiconductor device wafer 100 that embodies one of the aspects of the present invention. The wafer as depicted has two trenches 110 and 111 positioned in the middle portion of the wafer. Although a circular trench and a square trench are depicted, they may be replaced by other shapes such as elliptical, rectangular, polygonal, and non-geometric trenches. Each of the trenches 110 and 111 is depicted as a columnar region that completely encloses a semiconductor material that constitutes the device wafer 100. In this example, the semiconductor material is germanium, but other semiconductor materials such as tantalum carbide, gallium nitride, gallium arsenide, and the like are also contemplated.

The inner diameter of the circular groove of this exemplary device is 150 μm, and the groove width is 1.5 μm. The trench is etched into the germanium wafer from the top surface of the germanium wafer, wherein the wafer is still part of a germanium wafer. Although in an exemplary wafer, the trench is etched perpendicularly relative to the surface of the wafer, angle etching is also contemplated such that the trench extends into the wafer at an angle (other than 90 degrees) relative to the surface of the wafer.

Contact members 120 and 121 are also depicted in FIG. 1, and the metal members 130 are contacted by the contacts 120 and 121. In this exemplary wafer, the contacts are composed of a group of contact holes having a diameter of 3 μm. Metal component 130 is depicted as being close to a square with a protective coating 150 over most of the metal area containing the contact area. The window opening 140 is etched through the protective coating 150 such that the metal component exposed through the window can connect the wafer 100 to other circuit components placed on, for example, a printed circuit board (PCB).

The wafer 100 as depicted has an edge cut from a tantalum wafer using a tool such as a circular saw at the end of wafer processing. When the wafer 100 is packaged in a wafer size package (CSP), it is apparent that at the four edges of the package, the characteristic circular saw marks are visible. Other tools such as lasers and waterjets that cut wafers from wafers are also considered.

The wafer as depicted in FIG. 1 can also be packaged using, for example, a plastic molding compound after bonding the die to a leadframe. However, the device in the form of a CSP device can be easily incorporated into a PCB by placing solder on the metal member 130 through the window 140 and soldering directly onto the surface of a PCB or embedded in a PCB.

FIG. 2 depicts a cross-sectional view of an exemplary semiconductor wafer 200. The exemplary wafer 200 includes three germanium layers designated by the component symbols 230, 240, and 250. The layer 230 is an n+ germanium substrate; the layer 240 is grown on one of the epitaxial layers on top of the substrate; and the layer 250 is a doped layer in the epitaxial germanium. For cost and performance considerations, it is often advantageous to build such a device on a heavily doped substrate wafer having one of the lightly doped germanium epitaxial layers grown on the surface of the substrate. In this exemplary wafer, layer 230 has the highest dopant concentration and layer 240 has the lowest dopant concentration. Depending on the diameter of the substrate wafer, the combination of substrate and growth epitaxial layer can be from 300 μm (in the case of a 2 to 3 inch wafer) to approximately 800 μm (on a 12 inch wafer) One of the thicknesses within the range of the case). Also consider larger or thicker wafers. At the end of the wafer processing, depending on the form of the final package, the wafer can be ground to a final thickness of only 100 μm to 200 μm before the wafer is severed. When viewing the non-contact surface of the wafer 200 in a CSP package, the grinding can be significant. As depicted in Figure 2, the wafer has an n-type substrate, but depending on the application of the device, a p-type substrate can also be used, as will be explained in a later example.

The layer 250 depicted in Figure 2 is heavily doped with a p-type dopant to overcome one of the original n-type doping concentrations in the epitaxial layer. The p-type layer can be produced by implanting a p-type ion (such as boron or aluminum) into the n-type epitaxial layer 240 followed by an annealing step, and thus forming in the closed semiconductor pillars 210 and 220, respectively. Two pn junctions 260 and 270. The p-n junctions may also be formed by a dopant deposition step (rather than by ion implantation) followed by a drive-in step. Layer 250 is referred to herein as a source layer and has an exemplary thickness of about 1 μm.

Figure 2 also depicts a cross section of the two trenches 210 and 220. The trenches may be etched after the epitaxial layer 240 is grown on the substrate 250 and after the layer 250 is formed as part of the epitaxial layer. For this exemplary device wafer, the tops of the two trenches penetrate well into the substrate. In other exemplary devices, the depth of penetration can be shorter, and thus the trench terminates in the epitaxial layer 240. In this exemplary wafer, the epitaxial layer 240 is lightly doped with a thickness of one of 4 to 5 μm. N-type 矽. In other designs, the epitaxial layer can be p-type germanium and have a different thickness and dopant concentration. Since layers 240 and 250 are formed prior to etching the trenches, this is one way of ensuring (as depicted in Figure 2) the junction plane (without the curved and cylindrical structures known in the art).

The substance may be electrically conductive, such as doped polysilicon, or metal (such as tungsten), or electrically insulated, such as cerium oxide, by filling a region between the walls of the trench. In the case where the filler material is electrically conductive, the wall of the trench may be first lined with an electrically insulating material 231 such as cerium oxide or nitride.

Applicants have determined that the p-n junction of the invention made in accordance with this method is advantageous as compared to known diffusion p-n junctions comprising both planar and non-planar portions. As observed by the inventors, the junction of the invention does not have a non-planar portion that is broken down before the planar portion. Thus, when the planar junction breaks down at a desired higher voltage level, the entire junction region tends to break down simultaneously and wherein the entire junction region disperses the breakdown current, as far as a small portion (such as in the known art) The current density per unit area remains low compared to all currents. Thus, the wafer as depicted in Figure 2 is superior to the devices known in the art in many aspects.

Another advantageous aspect of the present invention is that the two pn junctions depicted in FIG. 2 are connected in a back-to-back configuration by the n+ substrate, such that the combination of the two pn junctions can be electrically connected from the top surface of the wafer 280. Da. This is advantageous when, for example, a wafer is assembled in a CSP package, since it is easy to incorporate it into the PCB by using a connection that is all in one surface.

The wafer depicted in FIG. 2 is electrically symmetrical with respect to contacts 120 and 121. This configuration applies to applications where the expected electrical transients of opposite polarities are approximately equal amplitude and duration.

FIG. 3 depicts another exemplary back-to-back p-n junction 300 having symmetric electrical characteristics. The device as depicted in Figure 3 differs from the device depicted in Figure 2 in that one of the germanium layers 130, 131 adjacent to the p+ layer is n-type and is more heavily doped than the epitaxial germanium. The doping of this layer can be the result of additional ion implantation of one of the n-type species (such as, for example, phosphorus or arsenic) before or after the formation of the p+ layer.

The more heavily doped layers 130 and 131 are predictably supplied with a lower junction breakdown voltage than without the layers, and this exemplary device is suitable for applications where the transient amplitude can be lower than in the previous examples.

Device 300 retains the symmetrical nature of device 200 as depicted in FIG. The two p-n junctions of device 300 are fabricated using the same n+ implant and p+ implant steps, thus requiring no masking.

Example 2: An asymmetric two-way transient suppressor

FIG. 4 depicts another illustrative device 400. The main difference between the device 400 and the device 300 depicted in Figure 3 is that the layer 130 in Figure 3 does not exist near the pn junction diode 401 on the left side of Figure 4, but on the right side of Figure 4 The pn junction exists. This is done using a masking operation covering one of the diode regions during the ion implantation step leading to the junction diode 411. Therefore, the junction breakdown of the diode 411 is broken down by the junction breakdown of the diode 411 of a predictable voltage. This device facilitates applications in which one polarity is higher than the desired voltage transient with opposite polarity.

Example 3: Another symmetric bidirectional transient suppressor

FIG. 5 depicts yet another exemplary device 500. The device 500 as depicted is a bidirectional, symmetric transient suppressor. The main difference between device 500 and device 200 is that in device 500, substrate 230 and epitaxial layer 240 are of the opposite doping type, while in device 200, they are of the same polarity.

Thus, p-n junctions 550 and 551 in device 500 are formed between the substrate and the epitaxial layer. In this exemplary device as well as in prior devices, because the junctions 500 and 551 are planar, they are also superior to the non-planar junctions of the prior art. In addition, since the doping concentration of the substrate and the epitaxial layer can be more tightly controlled than the doping concentration of the implant or diffusion layer, the control of the breakdown voltage of the interface can be tighter.

Example 4: A one-way transient suppressor

FIG. 6 depicts yet another exemplary device 600. The device 600 is built on an n+ substrate 230 and grown on an n-type epitaxial layer 240 above the substrate. However, unlike in devices 100, 300, 400, and 500, p-n junction 660 is formed only in the first trench closed pillar of the semiconductor material and is not formed in the second trench closed pillar of semiconductor material 661. On the contrary, the n-type dopant is introduced into the surface region of the epitaxial layer, so that the column closed by the trench on the right side of FIG. 6 has no pn junction and the same doping from the top of the epitaxial layer to the substrate Miscellaneous type.

With this configuration, device 600 can be accessed from the top surface of the wafer, but with two terminals The circuit between 671 and 672 contains only one p-n junction 660. It therefore acts to brake a single polarity transient with respect to terminals 671 and 672 only.

In summary, the above examples are illustrative only and not limiting. Other embodiments of the invention may be implemented by those skilled in the art of designing and fabricating semiconductor devices after reading this document, which includes the drawings. For example, dopant dispersion can be tailored in the columnar semiconductor material by ion implantation and implantation of various elements to modify the p-n junction breakdown voltage and the behavior of the depletion region associated with the junctions. The trenches in a wafer may or may not have rings of the same shape.

In addition, depending on how the packaged wafer is packaged, along with the sawed edge, the surface of the wafer that is opposite to the contact side and that is ground prior to the wafer sawing step can be self-sealed, or the like can be conductive film or dielectric The material cover, or the like, may be otherwise processed to protect the wafer from rough environments in which it is designed to act underneath.

This is also considered to be within the scope of the invention, and the scope of the invention is limited only by the scope of the patent application.

Claims (32)

A semiconductor wafer having a front surface and a back surface, comprising: a substrate extending to one of a semiconductor material of the back surface of the wafer; and an epitaxial semiconductor material layer extending from the substrate to the front surface of the wafer a pair of columns of semiconductor material, each extending from the front surface of the wafer and facing a trench structure of the substrate; each of the pair of columns having a plurality of radial sections that extend together with the respective columns And a pair of electrical terminals, each of the front surfaces of the wafer contacting one of the pair of columns of semiconductor material, forming at least one and no more than two pn junctions between the terminals One of the circuits. The semiconductor wafer of claim 1 wherein the trenches enclosing the columns of the pair of semiconductor materials extend into the substrate. The semiconductor wafer of claim 1 wherein the trenches enclosing the columns of the pair of semiconductor materials terminate before they reach the substrate. The semiconductor wafer of claim 1, wherein the substrate and the epitaxial layer do not form a p-n junction at their interfaces. The semiconductor wafer of claim 1, wherein the substrate and the epitaxial layer form a p-n junction at an interface thereof. A semiconductor wafer according to claim 1, wherein there is no more than one planar p-n junction in each of the pair of columns. The semiconductor wafer of claim 1 further comprising a filler material in the trenches enclosing the pair of columns of semiconductor material. The semiconductor wafer of claim 7, wherein the filler material is a dielectric material that isolates one of the columns of semiconductor material enclosed by the respective trench. A semiconductor package comprising: a semiconductor wafer having an orthogonal outer surface including a top surface and a bottom surface; the top surface of the wafer extending toward the bottom surface of the wafer to enclose a first column of semiconductor material a first trench structure having a ring shape; extending from a top surface of the wafer toward the bottom surface of the wafer to enclose a second trench structure of a ring shape of the second semiconductor material pillar; the top surface of the semiconductor wafer Contacting a first metal component of the first semiconductor material pillar; and contacting the second metal component of the second semiconductor material pillar on the top surface of the semiconductor wafer, and passing through the first semiconductor material pillar and the second semiconductor A column of material and including one or at most two pn junction circuits between the first metal component and the second metal component. The semiconductor package of claim 9, wherein the five outer side surfaces are semiconductor surfaces. The semiconductor package of claim 9, further comprising: a substrate portion comprising a first type of conductive dopant; and an epitaxial semiconductor material having a third conductivity type of the substrate and a third dopant concentration a first parallel portion of one of the second concentrations of the second parallel portion of the second type of conductive dopant of the epitaxial semiconductor material. The semiconductor package of claim 11, wherein the first parallel portion of the epitaxial semiconductor material and the second parallel portion of the epitaxial semiconductor material form a p-n junction at an interface thereof. The semiconductor package of claim 11, wherein the third conductivity type is p-type, and the third dopant concentration is higher than the second dopant concentration. The semiconductor package of claim 12, wherein the second conductivity type is n-type, and The second concentration is higher near the second parallel portion of the epitaxial semiconductor material as compared to the substrate. The semiconductor package of claim 13, wherein the first type is an n-type. The semiconductor package of claim 11, wherein the first type is p-type and the second type and the third type are n-type. The semiconductor package of claim 11, wherein the first type, the second type, and the third type are n-type. A semiconductor device comprising: a column of semiconductor material enclosed by a ring-shaped trench structure having a top section extending to a top surface, a bottom section extending toward a bottom surface, and at the top An intermediate section extending between the section and the bottom section; the top section mainly containing a first conductivity type and having a first dopant concentration; the intermediate section mainly containing a second conductivity type and having a second dopant concentration lower than the first dopant concentration; the bottom segment mainly containing a third conductivity type and having a third dopant higher than the first and second dopant concentrations The concentration of the agent; and the interface between the segments. The semiconductor device of claim 18, wherein the first conductivity type, the second conductivity type, and the third conductivity type are n-type. The semiconductor device of claim 18, further comprising: a second semiconductor material pillar closed by a ring-shaped trench structure, the second pillar having a second top section extending toward a top surface toward a bottom The surface extends one of the second bottom section and a second intermediate section extending between the top section and the bottom section. The second top section is a p-type and has a fourth dopant concentration; The second intermediate section mainly contains the second conductivity type and has the second dopant concentration; and the second bottom section mainly contains the third conductivity type and has the third dopant concentration. The semiconductor device of claim 20, wherein each of the first top segment and the second top segment are connected by a respective metal component. The semiconductor device of claim 18, wherein the column contains no more than one p-n junction extending along a radial section of the column. The semiconductor device of claim 20, wherein the second pillar comprises no more than one p-n junction extending along a radial section of the second pillar. A process for fabricating a plurality of semiconductor devices including diodes in a semiconductor wafer, the process comprising the steps of forming semiconductor layers of different dopant concentrations, wherein boundary layers between adjacent semiconductor layers of different dopant concentrations Plane and parallel to each other. A semiconductor package comprising an orthogonal outer surface comprising a top surface and a bottom surface; a semiconductor wafer having a front surface and a bottom surface; extending from the top wafer surface toward the bottom wafer surface to enclose a first semiconductor a first trench structure of a ring shape of the material column; extending from the top surface toward the surface of the bottom wafer to enclose a second trench structure of a ring shape of the second semiconductor material pillar; contacting the first semiconductor surface at the top wafer surface a first metal component of the material column; and a second metal component contacting the second semiconductor material column on the top wafer surface, and including one or at most two between the first metal component and the second metal component One of the p-n junction electrical paths. The semiconductor package of claim 25, wherein: the first column of semiconductor material has a top section extending to a top surface, a bottom section extending to a bottom surface, and bridging the top section and the bottom section An intermediate section; the top section is mainly doped with a dopant of a first conductivity type and has a first dopant concentration; the intermediate section is mainly doped with a dopant of a second conductivity type And having a second dopant concentration lower than the first dopant concentration; and the bottom portion is mainly doped with a dopant of a third conductivity type and having a higher than the first and the first One of the two dopant concentrations, the third dopant concentration. The semiconductor package of claim 26, wherein the first conductivity type and the third conductivity type are opposite polarities. The semiconductor package of claim 26, wherein the second column of semiconductor material and the first column of semiconductor material have the same dopant concentration within a tolerance of fabrication. The semiconductor package of claim 26, wherein the first conductivity type, the second conductivity type, and the third conductivity type are the same polarity. The semiconductor package of claim 26, wherein: the second column of semiconductor material has a top section extending to a top surface, a bottom section extending to a bottom surface, and bridging the top section and the bottom section An intermediate section; the top section is mainly doped with a fourth conductivity type and has a fourth dopant concentration; the intermediate section is mainly doped with a fifth conductivity type and has a fifth doping The concentration of the agent; and the bottom section is mainly doped with a sixth conductivity type and has a sixth doping The concentration of the dopant. The semiconductor package of claim 30, wherein the fourth conductivity type is opposite in polarity to the polarities of the first, second, third, fifth, and sixth conductivity types. The semiconductor package of claim 30, wherein the second conductivity type and the fifth conductivity type are of the same type, but the second dopant concentration is higher than the fifth dopant concentration.