TWI477018B - Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof - Google Patents

Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof Download PDF

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TWI477018B
TWI477018B TW101128368A TW101128368A TWI477018B TW I477018 B TWI477018 B TW I477018B TW 101128368 A TW101128368 A TW 101128368A TW 101128368 A TW101128368 A TW 101128368A TW I477018 B TWI477018 B TW I477018B
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anode
region
cathode
transient voltage
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TW201407913A (en
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Tsung Yi Huang
jin lian Su
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Richtek Technology Corp
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暫態電壓抑制器電路與用於其中之二極體元件及其製造方法Transient voltage suppressor circuit and diode element used therein and manufacturing method thereof

本發明係有關一種暫態電壓抑制器(transient voltage suppressor,TVS)電路與用於其中之二極體元件及其製造方法,特別是指一種可承受較高順向電流之TVS電路與用於其中之二極體元件及其製造方法。The present invention relates to a transient voltage suppressor (TVS) circuit and a diode element therefor and a method of manufacturing the same, and more particularly to a TVS circuit capable of withstanding a higher forward current and used therein A diode element and a method of manufacturing the same.

第1A圖顯示典型的暫態電壓抑制器(transient voltage suppressor,TVS)電路1,用以與至少一受保護電路2耦接,進而限制來自輸入輸出墊3的暫態電壓之振幅,以保護受保護電路2免於被具有高電壓的暫態訊號(如靜電)損害。一般而言,TVS電路1包含抑制元件S1,用以箝位上述暫態訊號的電壓振幅,並吸收其電流。由於此抑制元件S1需要在非常短的時間內消耗高電流,因此具有大面積的PN接面,也因此使其具有非常高的寄生電容;如此一來,當受保護電路2正常操作時,受到此高寄生電容的影響,使其操作速度變慢,而限制了元件的應用範圍。FIG. 1A shows a typical transient voltage suppressor (TVS) circuit 1 for coupling with at least one protected circuit 2 to limit the amplitude of the transient voltage from the input/output pad 3 to protect the The protection circuit 2 is protected from being damaged by transient signals (such as static electricity) having a high voltage. In general, the TVS circuit 1 includes a suppression element S1 for clamping the voltage amplitude of the transient signal and absorbing its current. Since the suppressing element S1 needs to consume a high current in a very short time, it has a large-area PN junction and thus has a very high parasitic capacitance; thus, when the protected circuit 2 is normally operated, it is subjected to The effect of this high parasitic capacitance slows down the operation and limits the application range of the component.

一種改善前述受保護電路2操作速度變慢的方法,如第1A圖所示,是於受保護電路2與抑制元件S1之間,插入至少一寄生電容較小的二極體元件D1。二極體元件D1與抑制元件S1中的PN接面反向對接,以使電流順向流經二極體元件D1,並由抑制元件S1吸收高電流;此種方法利用低電容串聯高電容的方式,以降低電容值,提高受保護電路2的操作速度。這種作法雖然可改善抑制元件S1電容值太高的問題,但二極體元件D1仍須順向承受來自輸入輸出墊3的暫態訊號高 電流,因此,若要保持其較低的電容值,TVS電路1可承受的暫態訊號電流值就會下降,如此也會限制TVS電路1的應用範圍。A method for improving the operation speed of the protected circuit 2 is slow. As shown in FIG. 1A, at least one diode element D1 having a small parasitic capacitance is inserted between the protected circuit 2 and the suppressing element S1. The diode element D1 and the PN junction in the suppression element S1 are reversely connected to flow current through the diode element D1, and the suppression element S1 absorbs a high current; this method utilizes a low capacitance series high capacitance In order to reduce the capacitance value, the operating speed of the protected circuit 2 is increased. Although this method can improve the problem that the capacitance of the suppression element S1 is too high, the diode element D1 must still be subjected to the transient signal from the input/output pad 3 in the forward direction. The current, therefore, if the lower capacitance value is to be maintained, the transient signal current value that the TVS circuit 1 can withstand decreases, which also limits the application range of the TVS circuit 1.

第3A圖顯示先前技術用於TVS電路中之二極體元件100的剖視示意圖;而第3B圖顯示先前技術TVS電路的靜電耐壓與寄生電容相對於二極體接面面積的特性圖。如第3A圖所示,先前技術二極體元件100包含基板11、場氧化區12、N型井區13、P型漂移擴散區14、P型陽極15與N型陰極16。第3B圖顯示先前技術TVS電路之靜電耐壓與寄生電容相對於二極體PN接面面積的特性圖,其靜電耐壓以及寄生電容與應用本發明的TVS電路相比,將於後詳述。Figure 3A shows a cross-sectional view of a prior art diode element 100 for use in a TVS circuit; and Figure 3B shows a characteristic of electrostatic withstand voltage and parasitic capacitance of a prior art TVS circuit with respect to a junction area of a diode. As shown in FIG. 3A, the prior art diode element 100 includes a substrate 11, a field oxide region 12, an N-type well region 13, a P-type drift diffusion region 14, a P-type anode 15 and an N-type cathode 16. FIG. 3B is a graph showing the relationship between the electrostatic withstand voltage and the parasitic capacitance of the prior art TVS circuit with respect to the area of the PN junction of the diode, and the electrostatic withstand voltage and parasitic capacitance thereof will be detailed later than the TVS circuit to which the present invention is applied. .

有鑑於此,本發明即針對上述先前技術之不足,提出一種TVS電路與用於其中之二極體元件及其製造方法,以提高TVS電路可承受的靜電壓,並增加電路的保護與應用範圍。In view of the above, the present invention is directed to the deficiencies of the prior art described above, and proposes a TVS circuit and a diode element used therein and a manufacturing method thereof to improve the static voltage that the TVS circuit can withstand, and increase the protection and application range of the circuit. .

本發明目的在提供一種暫態電壓抑制器電路與用於其中之二極體元件及其製造方法。SUMMARY OF THE INVENTION An object of the present invention is to provide a transient voltage suppressor circuit and a diode element therefor and a method of fabricating the same.

為達上述之目的,就其中一個觀點言,本發明提供了一種暫態電壓抑制器電路,用以耦接至一受保護電路,進而限制一輸入該受保護電路的暫態電壓之振幅,該暫態電壓抑制器電路包含:一抑制元件,具有一PN接面,用以限制該暫態電壓之振幅;以及至少一二極體元件,耦接於該受保護電路與該抑制元件之間,且與該PN接面反向對接;其中,該二極體元件包括:一第一導電型基板,具有一上表面;一第一導電型或第二導電型井區,形成於該上表面下之該基板中; 一分隔區,形成於該基板中,由上視圖視之,該分隔區位於該井區中;一第一導電型陽極,形成於該分隔區一側之該上表面下方;一第二導電型陰極,形成於該分隔區另一側之該上表面下方,且該陽極與該陰極由該分隔區隔開;以及複數漂移擴散區,形成並連接於該陽極或陰極下方,其具有與該陽極或陰極相同的導電型。In order to achieve the above object, in one aspect, the present invention provides a transient voltage suppressor circuit for coupling to a protected circuit, thereby limiting the amplitude of a transient voltage input to the protected circuit. The transient voltage suppressor circuit includes: a suppression component having a PN junction for limiting the amplitude of the transient voltage; and at least one diode component coupled between the protected circuit and the suppression component, And the PN junction is oppositely connected to the PN junction; wherein the diode component comprises: a first conductivity type substrate having an upper surface; and a first conductivity type or a second conductivity type well region formed under the upper surface In the substrate; a partitioning region formed in the substrate, the partitioning region being located in the well region as viewed from a top view; a first conductive type anode formed under the upper surface on one side of the partitioning region; and a second conductivity type a cathode formed below the upper surface on the other side of the partition, and the anode and the cathode are separated by the partition; and a plurality of drift diffusion regions formed and connected under the anode or cathode, having the anode Or the same conductivity type of the cathode.

就另一觀點,本發明也提供了一種用於暫態電壓抑制器電路中之二極體元件,用以與該暫態電壓抑制器電路中所包含之一具有PN接面之抑制元件反向對接,該用於暫態電壓抑制器電路中之二極體元件包含:一第一導電型基板中,具有一上表面;一第一導電型或第二導電型井區,形成於該上表面下之該基板中;一分隔區,形成於該基板中,由上視圖視之,該分隔區位於該井區中;一第一導電型陽極,形成於該分隔區一側之該上表面下方;一第二導電型陰極,形成於該分隔區另一側之該上表面下方,且該陽極與該陰極由該分隔區隔開;以及複數漂移擴散區,形成並連接於該陽極或陰極下方,其具有與該陽極或陰極相同的導電型。In another aspect, the present invention also provides a diode element for use in a transient voltage suppressor circuit for reversing a suppression element having a PN junction included in the transient voltage suppressor circuit Docking, the diode component used in the transient voltage suppressor circuit includes: a first conductive type substrate having an upper surface; and a first conductive type or second conductive type well region formed on the upper surface In the substrate, a partition is formed in the substrate, and the partition is located in the well region from a top view; a first conductive anode is formed under the upper surface on one side of the partition a second conductive cathode formed under the upper surface on the other side of the partition, and the anode and the cathode are separated by the partition; and a plurality of drift diffusion regions formed and connected under the anode or cathode It has the same conductivity type as the anode or cathode.

就再另一個觀點言,本發明也提供了一種用於暫態電壓抑制器電路中之二極體元件製造方法,該二極體元件用以與該暫態電壓抑制器電路中所包含之一具有PN接面之抑制元件反向對接,該製造方法包含:提供一第一導電型基板,該基板具有一上表面;形成一第一導電型或第二導電型井區於該上表面下之該基板中;形成一分隔區於該基板中,由上視圖視之,該分隔區位於該井區中;形成一第一導電型陽極於該分隔區一側之該上表面下方;形成一第二導電型陰極於該分隔區另一側之該上表面下方,且該陽極與該陰極由該分隔區隔開; 以及形成複數漂移擴散區連接於該陽極或陰極下方,其具有與該陽極或陰極相同的導電型。In still another aspect, the present invention also provides a method of fabricating a diode component for use in a transient voltage suppressor circuit for use with one of the transient voltage suppressor circuits The suppressing element having the PN junction is reversely butted. The manufacturing method includes: providing a first conductive type substrate having an upper surface; forming a first conductive type or a second conductive type well below the upper surface Forming a partition in the substrate, as viewed from a top view, the partition is located in the well region; forming a first conductive anode on the side of the upper surface of the partition; forming a first a second conductive cathode below the upper surface of the other side of the partition, and the anode and the cathode are separated by the partition; And forming a complex drift diffusion region connected below the anode or cathode, having the same conductivity type as the anode or cathode.

上述暫態電壓抑制器電路中,該抑制元件可包括一變阻器元件、一齊納二極體、二串聯對接的齊納二極體、或一無閘極金屬氧化物半導體(metal oxide semiconductor,MOS)元件。In the above transient voltage suppressor circuit, the suppressing element may comprise a varistor component, a Zener diode, two Zener diodes connected in series, or a metal oxide semiconductor (MOS). element.

其中一種較佳的實施例中,該分隔區包括一場氧化區或一純質半導體區In a preferred embodiment, the separation region includes a field oxidation region or a pure semiconductor region.

其中一種較佳的實施例中,該二極體元件為複數,且安排於該抑制元件兩側。In a preferred embodiment, the diode elements are plural and arranged on both sides of the suppression element.

底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

本發明中的圖式均屬示意,主要意在表示製程步驟以及各層之間之上下次序關係,至於形狀、厚度與寬度則並未依照比例繪製。The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

請參閱第4A與4B圖,顯示本發明的第一個實施例,第4A圖顯示用於暫態電壓抑制器(transient voltage suppressor,TVS)電路中之二極體元件200的剖視示意圖。如第4A圖所示,二極體元件200包含基板21,其具有上表面21a。接著形成例如但不限於N型井區23於上表面21a下之基板21中。然後形成分隔區22於基板21中,由上視圖(未示出)視之,分隔區22位於井區23中;其中,分隔區22例如為淺溝槽絕緣(shallow trench isolation,STI)結構或如圖所示之區域氧化(local oxidation of silicon,LOCOS)結構。接著,分別形成P 型陽極25於分隔區22一側之上表面21a下方,與N型陰極26於分隔區22另一側之上表面21a下方,且陽極25與陰極26由分隔區22隔開。接著形成複數漂移擴散區24於陽極25下方並與陽極25連接,且漂移擴散區24具有與陽極25相同的P型導電型。Referring to Figures 4A and 4B, there is shown a first embodiment of the present invention, and Figure 4A shows a cross-sectional view of a diode element 200 for use in a transient voltage suppressor (TVS) circuit. As shown in FIG. 4A, the diode element 200 includes a substrate 21 having an upper surface 21a. Next, for example, but not limited to, an N-type well region 23 is formed in the substrate 21 under the upper surface 21a. A separation region 22 is then formed in the substrate 21, as viewed from a top view (not shown), the separation region 22 is located in the well region 23; wherein the separation region 22 is, for example, a shallow trench isolation (STI) structure or The local oxidation of silicon (LOCOS) structure is shown. Then, form P separately The anode 25 is below the upper surface 21a of the partition 22 side, and the N-type cathode 26 is below the upper surface 21a of the other side of the partition 22, and the anode 25 and the cathode 26 are separated by the partition 22. A complex drift diffusion region 24 is then formed under the anode 25 and connected to the anode 25, and the drift diffusion region 24 has the same P-type conductivity as the anode 25.

接下來請參閱第4B圖,顯示應用第一個實施例之二極體元件200的TVS電路的靜電耐壓與寄生電容相對於二極體接面面積的特性圖,與先前技術第3B比較,可以看出在二極體接面面積相等的情形下,其電容也大致相等,但應用本發明的TVS電路,其靜電耐壓維持在可測得的極限Max.,表示應用本發明的TVS電路,其靜電耐壓在極限Max.以上,而先前技術的TVS電路,其靜電耐壓則低於極限Max.。比較先前技術第3A圖與本實施例第4A圖,可以看出本實施例相對於第3A所示之先前技術,在本實施例中,複數的P型漂移擴散區24與N型井區23接觸面積增加,靜電的耐壓增加。此種安排方式的優點包括:在元件規格上,由於多了複數個雜質濃度低於陽極25的漂移擴散區24,可提高TVS電路中,二極體元件所能承受的暫態順向電流,增加TVS電路的應用範圍;在製程上,漂移擴散區24,可以利用在同一基板21中,其他高壓元件(未示出)中漂移擴散區相同的製程步驟,因此幾乎不會增加製造成本。Next, referring to FIG. 4B, a characteristic diagram of the electrostatic withstand voltage and the parasitic capacitance of the TVS circuit to which the diode element 200 of the first embodiment is applied with respect to the junction area of the diode is shown, which is compared with the prior art 3B. It can be seen that in the case where the junction area of the diodes is equal, the capacitances are also substantially equal, but with the TVS circuit of the present invention, the electrostatic withstand voltage is maintained at the measurable limit Max., indicating the TVS circuit to which the present invention is applied. The electrostatic withstand voltage is above the limit Max., while the prior art TVS circuit has a static withstand voltage lower than the limit Max. Comparing the prior art FIG. 3A with the fourth embodiment of the present embodiment, it can be seen that the present embodiment is different from the prior art shown in FIG. 3A. In the present embodiment, a plurality of P-type drift diffusion regions 24 and N-type well regions 23 are present. The contact area increases and the withstand voltage of static electricity increases. The advantages of this arrangement include: in the component specification, since a plurality of impurity concentrations are lower than the drift diffusion region 24 of the anode 25, the transient forward current that the diode component can withstand in the TVS circuit can be improved. The application range of the TVS circuit is increased; in the process, the drift diffusion region 24 can utilize the same process steps in the same substrate 21 as the drift diffusion regions in other high voltage components (not shown), so that the manufacturing cost is hardly increased.

第5A與5B圖顯示本發明的第二個實施例,為應用本發明之TVS電路中之二極體元件300的剖視示意圖。如圖所示,相較於第一個實施例,在本實施例中,二極體元件300包含基板31、分隔區32、P型井區33、複數P型漂移擴散區34、N型陰極35、與P型陽極36。本實施例旨在說明, 在本發明之二極體中,井區可以同為N型(如第一個實施例)或P型(如第二個實施例),只需要注意其導電型相同,且漂移擴散區可以位於P型陽極下方,亦可以位於N型陰極下方。且漂移擴散區的雜質濃度,例如但不限於低於與其連接的陽極或陰極的雜質濃度。5A and 5B are cross-sectional views showing a second embodiment of the present invention, which is a diode element 300 in a TVS circuit to which the present invention is applied. As shown in the figure, in the present embodiment, the diode element 300 includes a substrate 31, a separation region 32, a P-type well region 33, a plurality of P-type drift diffusion regions 34, and an N-type cathode. 35, with a P-type anode 36. This embodiment is intended to illustrate that In the diode of the present invention, the well region may be the same as the N-type (as in the first embodiment) or the P-type (as in the second embodiment), and only the conductivity type is the same, and the drift diffusion region may be located. Below the P-type anode, it can also be located below the N-type cathode. And the impurity concentration of the drift diffusion region is, for example but not limited to, an impurity concentration lower than an anode or a cathode connected thereto.

第5B圖顯示應用第二個實施例之二極體元件300的TVS電路的靜電耐壓與寄生電容相對於二極體接面面積的特性圖,與先前技術第3B比較,可以看出在二極體接面面積相等的情形下,其電容也大致相等,但應用本發明的TVS電路,其靜電耐壓維持在可測得的極限Max.,表示應用本發明的TVS電路,其靜電耐壓在極限Max.以上Fig. 5B is a graph showing the relationship between the electrostatic withstand voltage and the parasitic capacitance of the TVS circuit to which the diode element 300 of the second embodiment is applied with respect to the junction area of the diode, as compared with the prior art 3B, it can be seen that In the case where the contact area of the polar body is equal, the capacitance is also substantially equal, but the static withstand voltage of the TVS circuit of the present invention is maintained at the measurable limit Max., indicating the electrostatic withstand voltage of the TVS circuit to which the present invention is applied. Above the limit Max.

第6圖顯示本發明第的第三個實施例,為應用本發明之TVS電路中之二極體元件400的剖視示意圖。如圖所示,相較於第一個實施例,在本實施例中,二極體元件400包含基板41、純質半導體區42、N型井區43、複數P型漂移擴散區44、P型陽極45、與N型陰極46。本實施例旨在說明,在本發明之二極體中,不僅可利用場氧化區作為分隔區,隔開陽極與陰極,亦可以利用純質半導體區作為分隔區,隔開陽極與陰極。所謂純質半導體區係指基本上接近純質(intrinsic)半導體的區間,也就是未摻雜或低摻雜雜質之半導體區域。Figure 6 is a cross-sectional view showing a third embodiment of the present invention, which is a diode element 400 in a TVS circuit to which the present invention is applied. As shown, in the present embodiment, the diode element 400 includes a substrate 41, a pure semiconductor region 42, an N-type well region 43, a plurality of P-type drift diffusion regions 44, P, as shown in the first embodiment. The anode 45 and the N-type cathode 46. This embodiment is intended to illustrate that in the diode of the present invention, not only the field oxide region can be used as the separation region, but also the anode and the cathode can be separated, and the pure semiconductor region can be used as the separation region to separate the anode from the cathode. By pure semiconductor region is meant a region that is substantially close to an intrinsic semiconductor, that is, a semiconductor region that is undoped or lowly doped with impurities.

請參閱第1B-1D圖以及第2圖,顯示應用本發明之TVS電路中,抑制元件的數種實施例。如第1B-1D圖以及第2圖所示,抑制元件例如但不限於為如第1B圖所示之變阻器元件V1、如第1C圖所示之齊納二極體D2、如第1D圖所示之二串聯對接的齊納二極體D2、或如第2圖所示之無閘極金屬 氧化物半導體(metal oxide semiconductor,MOS)元件Q1。Referring to Figures 1B-1D and 2, several embodiments of suppressing elements in a TVS circuit to which the present invention is applied are shown. As shown in FIGS. 1B-1D and 2, the suppression element is, for example but not limited to, a varistor element V1 as shown in FIG. 1B, and a Zener diode D2 as shown in FIG. 1C, as shown in FIG. 1D. Shown in series two pairs of Zener diode D2, or the gateless metal as shown in Figure 2 Metal oxide semiconductor (MOS) device Q1.

請繼續參閱第2圖,顯示應用本發明之TVS電路中,一種較佳的安排方式,為:二極體元件Dp與Dn為複數,且安排於抑制元件,在此處為MOS元件Q1兩側,其中,二極體元件Dp例如但不限於包含N型之井區,且二極體元件Dn例如但不限於包含P型之井區。Please continue to refer to FIG. 2, which shows a preferred arrangement in the TVS circuit to which the present invention is applied. The diode elements Dp and Dn are plural and arranged in the suppression element, here on both sides of the MOS element Q1. Wherein the diode element Dp is for example but not limited to a well region comprising an N-type, and the diode element Dn is for example but not limited to a well region comprising a P-type.

請參閱第7圖,顯示第一個實施例二極體元件200的上視示意圖。如圖所示,應用本發明之TVS電路中,二極體元件200的複數漂移擴散區24由上視圖第7圖視之,可以安排如圖所示,為如陣列的排列方式,並且可以由其他高壓元件(未示出)中漂移擴散區相同的製程步驟形成,如此一來,可以幾乎不增加製造的成本,增強TVS電路承受暫態訊號的能力。Referring to Figure 7, a top view of the first embodiment of the diode element 200 is shown. As shown in the figure, in the TVS circuit to which the present invention is applied, the complex drift diffusion region 24 of the diode element 200 is viewed from the top view of FIG. 7, and can be arranged as shown in the figure, and can be arranged as an array, and can be The same process steps of drifting the diffusion regions in other high voltage components (not shown) are formed, so that the manufacturing cost can be hardly increased and the ability of the TVS circuit to withstand transient signals can be enhanced.

以上已針對較佳實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。在本發明之相同精神下,熟悉本技術者可以思及各種等效變化。例如,在不影響元件主要的特性下,可加入其他製程步驟或結構,如深井區等;又如,上述關於二極體元件的實施例中,製造二極體元件的方法步驟可以改變,井區與漂移擴散區可以形成於分隔區之前,亦可形成於分隔區之後。本發明的範圍應涵蓋上述及其他所有等效變化。The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well zones, may be added without affecting the primary characteristics of the component; as in the above-described embodiment of the diode component, the method steps for fabricating the diode component may be changed. The region and the drift diffusion region may be formed before the separation region or may be formed after the separation region. The above and other equivalent variations are intended to be covered by the scope of the invention.

1‧‧‧TVS電路1‧‧‧TVS circuit

2‧‧‧受保護電路2‧‧‧protected circuits

3‧‧‧輸入輸出墊3‧‧‧Input and output pads

11,21,31,41‧‧‧基板11,21,31,41‧‧‧substrate

12,22,32‧‧‧分隔區12,22,32‧‧‧Separated area

13,23,33,43‧‧‧井區13,23,33,43‧‧‧ Well Area

24,34,44‧‧‧漂移擴散區24,34,44‧‧‧Drag diffusion zone

15,25,36,45‧‧‧陽極15,25,36,45‧‧‧Anode

16,26,35,46‧‧‧陰極16,26,35,46‧‧‧ cathode

42‧‧‧純質半導體區42‧‧‧Pure semiconductor area

100,200,300,400‧‧‧二極體元件100,200,300,400‧‧‧dipole components

D1,Dn,Dp‧‧‧二極體元件D1, Dn, Dp‧‧‧ diode components

D2‧‧‧齊納二極體D2‧‧‧Zina diode

Q1‧‧‧MOS元件Q1‧‧‧MOS components

第1A圖顯示典型的暫態電壓抑制器(transient voltage suppressor,TVS)電路1。Figure 1A shows a typical transient voltage suppressor (TVS) circuit 1.

第1B-1D圖顯示應用本發明之TVS電路中,抑制元件的數種 實施例。1B-1D shows several kinds of suppression elements in the TVS circuit to which the present invention is applied Example.

第2圖顯示應用本發明之TVS電路中,二極體的一種較佳的安排方式。Figure 2 shows a preferred arrangement of the diodes in the TVS circuit to which the present invention is applied.

第3A-3B圖顯示先前技術用於TVS電路中之二極體元件100的剖視示意圖與先前技術TVS電路的靜電耐壓與寄生電容相對於二極體接面面積的特性圖。3A-3B are cross-sectional views showing a prior art schematic diagram of a diode element 100 for use in a TVS circuit and a characteristic of electrostatic withstand voltage and parasitic capacitance of a prior art TVS circuit with respect to a junction area of a diode.

第4A與4B圖顯示本發明的第一個實施例。Figures 4A and 4B show a first embodiment of the present invention.

第5A與5B圖顯示本發明的第二個實施例。Figures 5A and 5B show a second embodiment of the invention.

第6圖顯示本發明第的第三個實施例。Figure 6 shows a third embodiment of the present invention.

第7圖顯示第一個實施例二極體元件200的上視示意圖。Figure 7 shows a top view of the first embodiment diode element 200.

21‧‧‧基板21‧‧‧Substrate

21a‧‧‧上表面21a‧‧‧Upper surface

22‧‧‧分隔區22‧‧‧Separation zone

23‧‧‧井區23‧‧‧ Well Area

24‧‧‧漂移擴散區24‧‧‧Drag diffusion zone

25‧‧‧陽極25‧‧‧Anode

26‧‧‧陰極26‧‧‧ cathode

200‧‧‧二極體元件200‧‧‧ diode components

Claims (10)

一種暫態電壓抑制器電路,用以耦接至一受保護電路,進而限制一輸入該受保護電路的暫態電壓之振幅,該暫態電壓抑制器電路包含:一抑制元件,具有一第一PN接面,用以限制該暫態電壓之振幅;以及至少一二極體元件,耦接於該受保護電路與該抑制元件之間,且該二極體元件具有一第二PN接面,與該第一PN接面反向對接;其中,該二極體元件包括:一P型基板,具有一上表面;一P型或N型井區,形成於該上表面下之該基板中;一分隔區,形成於該基板中,由上視圖視之,該分隔區位於該井區中;一P型陽極,形成於該分隔區一側之該上表面下方;一N型陰極,形成於該分隔區另一側之該上表面下方,且該陽極與該陰極由該分隔區隔開,且該陽極或該陰極與該井區形成該第二PN接面;以及複數漂移擴散區,形成並連接於該陽極或陰極下方該井區中,其具有與對應連接之該陽極或陰極相同的導電型,且該漂移擴散區的雜質濃度,低於對應連接之該陽極或陰極的雜質濃度。 A transient voltage suppressor circuit is coupled to a protected circuit for limiting an amplitude of a transient voltage input to the protected circuit, the transient voltage suppressor circuit comprising: a suppression component having a first a PN junction for limiting an amplitude of the transient voltage; and at least one diode component coupled between the protected circuit and the suppression component, and the diode component has a second PN junction Interfacing with the first PN junction; wherein the diode element comprises: a P-type substrate having an upper surface; a P-type or N-type well region formed in the substrate under the upper surface; a partitioning region formed in the substrate, the partitioning region being located in the well region as viewed from a top view; a P-type anode formed under the upper surface on one side of the partitioning region; an N-type cathode formed in a lower surface of the upper side of the partition, and the anode is separated from the cathode by the partition, and the anode or the cathode forms a second PN junction with the well region; and a plurality of drift diffusion regions are formed And connected to the well region below the anode or cathode, There is the same conductivity type as the correspondingly connected anode or cathode, and the impurity concentration of the drift diffusion region is lower than the impurity concentration of the anode or cathode correspondingly connected. 如申請專利範圍第1項所述之暫態電壓抑制器電路,其中該分隔區包括一場氧化區或一純質半導體區。 The transient voltage suppressor circuit of claim 1, wherein the separation region comprises a field oxide region or a pure semiconductor region. 如申請專利範圍第1項所述之暫態電壓抑制器電路,其中該抑制元件包括一變阻器元件、一齊納二極體、二串聯對接 的齊納二極體、或一無閘極金屬氧化物半導體元件。 The transient voltage suppressor circuit of claim 1, wherein the suppression component comprises a varistor component, a Zener diode, and two series docking Zener diode, or a gateless metal oxide semiconductor device. 如申請專利範圍第1項所述之暫態電壓抑制器電路,其中該二極體元件為複數,且安排於該抑制元件兩側。 The transient voltage suppressor circuit of claim 1, wherein the diode element is plural and arranged on both sides of the suppression element. 一種用於暫態電壓抑制器電路中之二極體元件,與該暫態電壓抑制器電路中所包含之一具有一第一PN接面之抑制元件連接,該用於暫態電壓抑制器電路中之二極體元件包含:一P型基板,具有一上表面;一P型或N型井區,形成於該上表面下之該基板中;一分隔區,形成於該基板中,由上視圖視之,該分隔區位於該井區中;一P型陽極,形成於該分隔區一側之該上表面下方;一N型陰極,形成於該分隔區另一側之該上表面下方,且該陽極與該陰極由該分隔區隔開,且該陽極或該陰極與該井區形成一第二PN接面,該第二PN接面與該第一PN接面反向對接;以及複數漂移擴散區,形成並連接於該陽極或陰極下方該井區中,其具有與對應連接之該陽極或陰極相同的導電型,且該漂移擴散區的雜質濃度,低於對應連接之該陽極或陰極的雜質濃度。 A diode element for use in a transient voltage suppressor circuit coupled to a suppression element having a first PN junction included in the transient voltage suppressor circuit for use in a transient voltage suppressor circuit The diode component comprises: a P-type substrate having an upper surface; a P-type or N-type well region formed in the substrate under the upper surface; a separation region formed in the substrate Viewing, the partition is located in the well region; a P-type anode is formed below the upper surface on one side of the partition; an N-type cathode is formed below the upper surface on the other side of the partition, And the anode and the cathode are separated by the separation zone, and the anode or the cathode forms a second PN junction with the well region, the second PN junction is opposite to the first PN junction; and the plurality a drift diffusion region formed and connected in the well region below the anode or cathode, having the same conductivity type as the corresponding anode or cathode, and the impurity concentration of the drift diffusion region is lower than the anode or the corresponding connection The impurity concentration of the cathode. 如申請專利範圍第5項所述之用於暫態電壓抑制器電路中之二極體元件,其中該分隔區包括一場氧化區或一純質半導體區。 A diode element for use in a transient voltage suppressor circuit as described in claim 5, wherein the separation region comprises a field oxide region or a pure semiconductor region. 如申請專利範圍第5項所述之用於暫態電壓抑制器電路中之二極體元件,其中該抑制元件包括一變阻器元件、一齊納二極體、二串聯對接的齊納二極體、或一無閘極金屬氧化物半導體元件。 The diode component for use in a transient voltage suppressor circuit according to claim 5, wherein the suppression component comprises a varistor component, a Zener diode, and two Zener diodes connected in series, Or a gateless metal oxide semiconductor component. 一種用於暫態電壓抑制器電路中之二極體元件製造方法,該二極體元件與該暫態電壓抑制器電路中所包含之一具有一第一PN接面之抑制元件連接,該製造方法包含:提供一P型基板,該基板具有一上表面;形成一P型或N型井區於該上表面下之該基板中;形成一分隔區於該基板中,由上視圖視之,該分隔區位於該井區中;形成一P型陽極於該分隔區一側之該上表面下方;形成一N型陰極於該分隔區另一側之該上表面下方,且該陽極與該陰極由該分隔區隔開,且該陽極或該陰極與該井區形成一第二PN接面,該第二PN接面與該第一PN接面反向對接;以及形成複數漂移擴散區連接於該陽極或陰極下方該井區中,其具有與對應連接之該陽極或陰極相同的導電型,且該漂移擴散區的雜質濃度,低於對應連接之該陽極或陰極的雜質濃度。 A method for fabricating a diode element for use in a transient voltage suppressor circuit, the diode element being coupled to a suppression element having a first PN junction included in the transient voltage suppressor circuit, the fabrication The method includes: providing a P-type substrate having an upper surface; forming a P-type or N-type well region in the substrate under the upper surface; forming a separation region in the substrate, viewed from a top view, The separation zone is located in the well zone; forming a P-type anode below the upper surface of the separation zone; forming an N-type cathode below the upper surface of the other side of the separation zone, and the anode and the cathode Separated by the partition, and the anode or the cathode forms a second PN junction with the well region, the second PN junction is opposite to the first PN junction; and a complex drift diffusion region is formed In the well region below the anode or cathode, it has the same conductivity type as the corresponding anode or cathode, and the impurity concentration of the drift diffusion region is lower than the impurity concentration of the anode or cathode correspondingly connected. 如申請專利範圍第8項所述之用於暫態電壓抑制器電路中之二極體元件製造方法,其中該分隔區包括一場氧化區或一純質半導體區。 A method of fabricating a diode element for use in a transient voltage suppressor circuit as described in claim 8 wherein the separation region comprises a field oxide region or a pure semiconductor region. 如申請專利範圍第8項所述之用於暫態電壓抑制器電路中之二極體元件製造方法,其中該二極體元件為複數,且安排於該抑制元件兩側。 The method for fabricating a diode element for use in a transient voltage suppressor circuit according to claim 8, wherein the diode element is plural and arranged on both sides of the suppression element.
TW101128368A 2012-08-07 2012-08-07 Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof TWI477018B (en)

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