CN107301998B - Transient voltage suppressor and method of manufacturing the same - Google Patents
Transient voltage suppressor and method of manufacturing the same Download PDFInfo
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- CN107301998B CN107301998B CN201710602270.3A CN201710602270A CN107301998B CN 107301998 B CN107301998 B CN 107301998B CN 201710602270 A CN201710602270 A CN 201710602270A CN 107301998 B CN107301998 B CN 107301998B
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- 230000001052 transient effect Effects 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 22
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000008569 process Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 230000002457 bidirectional effect Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000003685 thermal hair damage Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
The application discloses a transient voltage suppressor and a manufacturing method thereof, wherein the transient voltage suppressor comprises a semiconductor substrate with a first doping type; a buried layer of a second doping type; an epitaxial layer of a second doping type on the semiconductor substrate; a first doped region of a first doping type in the epitaxial layer; and a second doped region of a second doping type extending longitudinally through the epitaxial layer from the first doped region into the buried layer, wherein the cross-sectional area of the first doped region is not smaller than the cross-sectional area of the second doped region, and the interface of the first doped region and the second doped region is positioned on the lower surface of the first doped region. Because the internal breakdown replaces the surface breakdown and the heavily doped semiconductor substrate and the lightly doped inversion epitaxial layer are adopted, the transient voltage suppressor provided by the embodiment of the application has better reliability and expansibility.
Description
Technical Field
The present application relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a transient voltage suppressor and a method of manufacturing the same.
Background
The tvs TVS (Transient Voltage Suppressor) are high performance circuit protection devices that have evolved on a regulated tube basis. The shape of the TVS device is not different from that of a common voltage stabilizing tube, however, due to the special structure and process design, the transient response speed and the surge absorption capacity of the TVS device are far higher than those of the common voltage stabilizing tube. For example, the response time of a TVS device is only 10 -12 Second, and can absorb up to thousands of watts of surge power. Under reverse application conditions, the operating impedance of the TVS device will quickly drop to an extremely low on value when subjected to a high energy large pulse, allowing large currents to pass while clamping the voltage at a predetermined level. Because ofThe TVS device can effectively protect precision components in the electronic circuit from being damaged by various surge pulses.
Compared with a unidirectional TVS device, the bidirectional TVS device has the characteristic that the conventional electrical I-V curves in the positive direction and the negative direction are basically symmetrical, so that in practical application, the two directions of a circuit can be protected at the same time, and the application range is wider.
The bidirectional TVS device provided by the prior art is generally formed by a longitudinal NPN or PNP structure, can realize larger power and better voltage symmetry, and has low cost and simple process. However, because the avalanche breakdown of the PN junction is located on the surface of the active region, the thermal damage of the device is easy to cause, the power is difficult to ensure, the low capacitance is also difficult to be realized, and each doped region with high concentration is difficult to combine with the existing low capacitance integration scheme, so that the expansibility is not realized.
Disclosure of Invention
Accordingly, the present application is directed to a bi-directional transient voltage suppressor and a method for manufacturing the same, which can avoid the damage of the device caused by the surface breakdown and has better expansibility.
In order to solve the above technical problem, according to a first aspect of the present application, there is provided a transient voltage suppressor comprising: a semiconductor substrate of a first doping type; a buried layer of a second doping type; an epitaxial layer of a second doping type on the semiconductor substrate; a first doped region of a first doping type in the epitaxial layer; and a second doped region of a second doping type extending longitudinally through the epitaxial layer from the first doped region into the buried layer, wherein the cross-sectional area of the first doped region is not smaller than the cross-sectional area of the second doped region, and the interface of the first doped region and the second doped region is positioned on the lower surface of the first doped region.
Preferably, the doping concentration of the epitaxial layer is lower than the doping concentration of the second doping region.
Preferably, the circuit comprises a first zener diode and a second zener diode which are connected in series in an inverted mode, wherein a first pole of the first zener diode is electrically connected with a first pole of the second zener diode, a second pole of the first zener diode is used as a grounding end of the transient voltage suppressor, a second pole of the second zener diode is used as a signal end of the transient voltage suppressor, and the polarities of the first pole and the second pole are opposite.
Preferably, the buried layer and the semiconductor substrate serve as a first pole and a second pole of the first zener diode, respectively, and the first doped region and the second doped region serve as a second pole and a first pole of the second zener diode, respectively.
Preferably, the doping concentration of the semiconductor substrate is greater than or equal to E18cm -3 The doping concentration of the buried layer is more than or equal to E19cm -3 The doping concentration of the second doping region is more than or equal to E18cm -3 On the order of magnitude.
Preferably, the first doping type is one of N-type or P-type, and the second doping type is the other of N-type or P-type.
According to a second aspect of the present application, there is provided a method of manufacturing a transient voltage suppressor comprising: forming a buried layer of a second doping type in the semiconductor substrate of the first doping type; forming an epitaxial layer of a second doping type on the semiconductor substrate; forming a second doping region of a second doping type in the epitaxial layer, the second doping region extending longitudinally through the epitaxial layer from the surface of the epitaxial layer into the buried layer; and forming a first doped region of a first doping type in the epitaxial layer, wherein the first doped region extends from the surface of the epitaxial layer into the second doped region, the cross-sectional area of the first doped region is not smaller than the cross-sectional area of the second doped region, and an interface of the first doped region and the second doped region is positioned on the lower surface of the first doped region.
Preferably, the doping concentration of the epitaxial layer is lower than the doping concentration of the second doping region.
Preferably, the circuit comprises a first zener diode and a second zener diode which are connected in series in opposite phases, wherein a first pole of the first zener diode is connected with a first pole of the second zener diode, a second pole of the first zener diode is used as a grounding terminal of the transient voltage suppressor, a second pole of the second zener diode is used as a signal terminal of the transient voltage suppressor, and the polarities of the first pole and the second pole are opposite.
Preferably, the buried layer and the semiconductor substrate serve as a first pole and a second pole of the first zener diode, respectively, and the first doped region and the second doped region serve as a second pole and a first pole of the second zener diode, respectively.
Preferably, the doping concentration of the semiconductor substrate is greater than or equal to E18cm -3 The doping concentration of the buried layer is more than or equal to E19cm -3 The doping concentration of the second doping region is more than or equal to E18cm -3 On the order of magnitude.
Preferably, the first doping type is one of N-type or P-type, and the second doping type is the other of N-type or P-type.
After the technical scheme of the application is adopted, the following beneficial effects can be obtained:
according to the device disclosed by the application, a bidirectional TVS device can be prepared by simple steps, the internal breakdown replaces the surface breakdown, the thermal damage caused by the surface breakdown is avoided, the reliability of the TVS device is improved, and the TVS device is easy to combine with the existing low-capacitance process or other processes such as a bipolar integrated circuit and the like due to the adoption of the heavily doped semiconductor substrate and the lightly doped inversion epitaxial layer, so that the TVS device has better expansibility.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the application with reference to the accompanying drawings, in which:
fig. 1 shows a schematic circuit diagram of a transient voltage suppressor according to a first embodiment of the application.
Fig. 2 shows a block diagram of a transient voltage suppressor according to a first embodiment of the application.
Fig. 3a to 3d show cross-sectional views of various stages of a method of manufacturing a transient voltage suppressor according to a first embodiment of the application.
Detailed Description
The present application is described below based on examples, but the present application is not limited to only these examples. In the following detailed description of embodiments of the application, certain specific details are set forth in order to provide a thorough understanding of the application. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the application.
Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings. The flowcharts, block diagrams in the figures illustrate the possible architecture, functionality, and operation of systems, methods, devices according to embodiments of the present application, and the order of the blocks in the figures are merely for better illustrating the processes and steps of the embodiments, and should not be taken as limiting the application itself.
The application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly on top of another layer, another region, the expression "a directly on top of B" or "a directly on top of B and adjoining it" will be used herein. In the present application, "a is directly in B" means that a is in B and a is directly adjacent to B, instead of a being in the first doped region formed in B.
In the present application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed.
Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.
Fig. 1 shows a schematic circuit diagram of a transient voltage suppressor according to a first embodiment of the application.
As shown in fig. 1, the TVS device is a bidirectional TVS device, and includes a first zener diode ZD1 and a second zener diode ZD2 connected in anti-phase series with each other, in this embodiment, an anode of the second zener diode ZD2 is used as a signal terminal I/O of the TVS device, a cathode of the second zener diode ZD2 is connected with a cathode of the first zener diode ZD1, and an anode of the first zener diode ZD1 is used as a ground terminal GND of the TVS device.
Fig. 2 shows a block diagram of a transient voltage suppressor according to a first embodiment of the application.
As shown in fig. 2, TVS device 100 includes a semiconductor substrate 101, a buried layer 102 in semiconductor substrate 101, an epitaxial layer 103 on semiconductor substrate 101, a first doped region 105 and a second doped region 104 in epitaxial layer 103.
The semiconductor substrate 101 is, for example, a heavily doped P-type semiconductor substrate. To form a P-type or N-type semiconductor layer or region, a corresponding type of dopant may be incorporated into the semiconductor layer or region. For example, the P-type dopant includes boron and the N-type dopant includes phosphorus or arsenic or antimony. In this embodiment, the doping concentration of the semiconductor substrate 101 is not lower than E18cm -3 On the order of magnitude.
Buried layer 102 is, for example, an N-type buried layer with a doping concentration not lower than E19cm -3 On the order of magnitude.
Epitaxial layer 103 is, for example, a lightly doped N-type epitaxial layer.
The first doped region 105 is doped, for exampleThe impurity concentration is greater than or equal to E18cm -3 An N-type doped region of the order of magnitude, the first doped region 105 extending longitudinally into the epitaxial layer 103 from the surface of the epitaxial layer 103.
The second doped region 104 is, for example, an N-type doped region having a doping concentration greater than that of the epitaxial layer 103, and is located in the epitaxial layer 103, longitudinally passing through the epitaxial layer 103 from the first doped region 105, and extending into the buried layer 102.
The first doped region 105 completely covers the second doped region 104, i.e., the cross-sectional area of the first doped region 105 is larger than that of the second doped region 104, and the interface between the two is located on the lower surface of the first doped region 105.
Referring to fig. 1, in the TVS device 100 shown in fig. 2, a buried layer 102 and a semiconductor substrate 101 serve as a cathode and an anode of a first zener diode ZD1, respectively, a PN junction of the first zener diode ZD1 is formed between the buried layer 102 and the semiconductor substrate 101, a first doped region 105 and a second doped region 104 serve as an anode and a cathode of a second zener diode ZD2, respectively, a PN junction of the second zener diode ZD2 is formed between the first doped region 105 and the second doped region 104, and the first zener diode ZD1 and the second zener diode ZD2 are connected in series in opposite phases. When the PN junction of the second zener diode ZD2 is turned on, the current flows in the direction indicated by the arrow in fig. 2, and since the first doped region 105 completely covers the second doped region 104 and the doping concentration of the second doped region 104 is higher than that of the epitaxial layer 103, the avalanche breakdown of the PN junction of the second zener diode ZD2 occurs only in the area indicated by the dashed box a. Fig. 3a to 3d show cross-sectional views of various stages of a method of manufacturing a transient voltage suppressor according to a first embodiment of the application.
As shown in fig. 3a, a buried layer 102 is formed in a semiconductor substrate 101, the semiconductor substrate 101 having a doping concentration of not less than E18cm -3 An order of magnitude P-type semiconductor substrate, the buried layer 102 having a doping concentration of not less than E19cm -3 An order of magnitude buried N-type layer.
As shown in fig. 3b, an epitaxial layer 103 is formed on the semiconductor substrate 101, the epitaxial layer 103 being, for example, a lightly doped N-type epitaxial layer.
As shown in fig. 3c, a second doped region 104 is formed in the epitaxial layer 103, the second doped region 104 extends longitudinally through the epitaxial layer 103 from the surface of the epitaxial layer 103 into the buried layer 102, the second doped region 104 is, for example, an N-type doped region having a doping concentration greater than that of the epitaxial layer 103, and the doping concentration of the second doped region 104 is greater than that of the epitaxial layer 103.
As shown in FIG. 3d, a doping concentration of E18cm or more is formed in the epitaxial layer 103 -3 An order of magnitude N-type first doped region 105, the first doped region 105 extending from the surface of the epitaxial layer 103 into the second doped region 104, the first doped region 105 completely covering the second doped region 104, and the interface of the two being located on the lower surface of the first doped region 105.
It can be seen that according to the device of the present application, a bi-directional TVS device can be manufactured in a simple process, which avoids thermal damage due to surface breakdown due to the replacement of surface breakdown, improves the reliability of the TVS device, and is easy to combine with other processes such as the existing low-capacitance process or bipolar integrated circuit due to the adoption of the heavily doped semiconductor substrate and the lightly doped inversion epitaxial layer, and has good expansibility.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A transient voltage suppressor, comprising:
a semiconductor substrate of a first doping type;
a buried layer of a second doping type;
an epitaxial layer of a second doping type on the semiconductor substrate;
a first doped region of a first doping type in the epitaxial layer; and
a second doped region of a second doping type extending longitudinally through the epitaxial layer from the first doped region into the buried layer,
the cross section area of the first doped region is not smaller than that of the second doped region, and the interface of the first doped region and the second doped region is positioned on the lower surface of the first doped region;
the buried layer and the semiconductor substrate are respectively used as a first pole and a second pole of a first Zener diode, the first doping region and the second doping region are respectively used as a second pole and a first pole of a second Zener diode, and the polarities of the first pole and the second pole are opposite; the first zener diode and the second zener diode are connected in reverse series, and a first pole of the first zener diode is electrically connected with a first pole of the second zener diode.
2. The tvs of claim 1, wherein a doping concentration of said epitaxial layer is lower than a doping concentration of said second doped region.
3. The tvs of claim 1, wherein a second diode of said first zener diode is a ground terminal of said tvs and a second diode of said second zener diode is a signal terminal of said tvs.
4. The transient voltage suppressor of claim 1, wherein a doping concentration of said semiconductor substrate is equal to or greater than E18cm -3 The doping concentration of the buried layer is more than or equal to E19cm -3 The doping concentration of the second doping region is more than or equal to E18cm -3 On the order of magnitude.
5. The transient voltage suppressor of claim 1, wherein said first doping type is one of N-type or P-type and said second doping type is the other of N-type or P-type.
6. A method of manufacturing a transient voltage suppressor comprising:
forming a buried layer of a second doping type in the semiconductor substrate of the first doping type;
forming an epitaxial layer of a second doping type on the semiconductor substrate;
forming a second doping region of a second doping type in the epitaxial layer, the second doping region extending longitudinally through the epitaxial layer from the surface of the epitaxial layer into the buried layer; and
forming a first doped region of a first doping type in the epitaxial layer, the first doped region extending from a surface of the epitaxial layer into the second doped region,
the cross section area of the first doped region is not smaller than that of the second doped region, and the interface of the first doped region and the second doped region is positioned on the lower surface of the first doped region;
the buried layer and the semiconductor substrate are respectively used as a first pole and a second pole of a first Zener diode, the first doping region and the second doping region are respectively used as a second pole and a first pole of a second Zener diode, and the polarities of the first pole and the second pole are opposite; the first zener diode and the second zener diode are connected in reverse series, and a first pole of the first zener diode is electrically connected with a first pole of the second zener diode.
7. The method of claim 6, wherein the epitaxial layer has a doping concentration that is lower than a doping concentration of the second doped region.
8. The method of claim 6, wherein a second pole of the first zener diode is used as a ground terminal of the transient voltage suppressor and a second pole of the second zener diode is used as a signal terminal of the transient voltage suppressor, and the first pole and the second pole are opposite in polarity.
9. The method of manufacturing a transient voltage suppressor of claim 6, wherein said semiconductor substrate has a doping concentration of E18cm or more -3 The doping concentration of the buried layer is more than or equal to E19cm -3 The doping concentration of the second doping region is more than or equal to E18cm -3 On the order of magnitude.
10. The method of claim 6, wherein the first doping type is one of N-type or P-type and the second doping type is the other of N-type or P-type.
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| CN201710602270.3A CN107301998B (en) | 2017-07-21 | 2017-07-21 | Transient voltage suppressor and method of manufacturing the same |
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| CN201710602270.3A CN107301998B (en) | 2017-07-21 | 2017-07-21 | Transient voltage suppressor and method of manufacturing the same |
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| CN107301998B true CN107301998B (en) | 2023-11-10 |
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|---|---|---|---|---|
| US6392266B1 (en) * | 2001-01-25 | 2002-05-21 | Semiconductor Components Industries Llc | Transient suppressing device and method |
| CN101536189A (en) * | 2006-11-16 | 2009-09-16 | 万国半导体股份有限公司 | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (tvs) and emi filter |
| CN101853853A (en) * | 2009-03-31 | 2010-10-06 | 万国半导体有限公司 | The semiconductor controlled rectifier that has low electric capacity and forward drop and exhaust is as the Transient Voltage Suppressor of steering diode |
| CN102142370A (en) * | 2010-12-20 | 2011-08-03 | 杭州士兰集成电路有限公司 | Preparation method of diode chip on P+ substrate and structure of diode chip |
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