CN102142370A - Preparation method of diode chip on P+ substrate and structure of diode chip - Google Patents
Preparation method of diode chip on P+ substrate and structure of diode chip Download PDFInfo
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- CN102142370A CN102142370A CN 201010606126 CN201010606126A CN102142370A CN 102142370 A CN102142370 A CN 102142370A CN 201010606126 CN201010606126 CN 201010606126 CN 201010606126 A CN201010606126 A CN 201010606126A CN 102142370 A CN102142370 A CN 102142370A
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Abstract
The invention discloses a preparation method of a diode chip on a P+ substrate and a structure of the diode chip. The method comprises the following steps of: directly forming a P- epitaxial layer on the P+ substrate through epitaxy; forming a P+ well through filling boron; annealing a P well; forming an N- ring region through photoetching and etching; annealing the N- ring; forming an N+ main junction region through photoetching and etching; annealing the N+ main junction region; evaporating or sputtering A1 as a positive electrode and the like. In the structure, special structures of the P- epitaxial layer, the P+ well and an N- voltage dividing ring device, and an N+ arsenic filling process are adopted to ensure that the N+/P+ is broken down on a plane and to avoid lateral breakdown; the voltage of a diode formed on the P+ substrate is reduced to be lower than 5.1V, the lowest voltage can reach 2.0V, and leakage current is within 100uA, so that the uniformity of the voltage in the chip is ensured to be within 5%; and in fact the diode is a P-N junction formed by the P well and an N+ region. The structure is successfully applied to the fields of a low-voltage voltage-regulator diode and a low-voltage transient voltage suppressor diode.
Description
Technical field
The present invention relates to semiconductor chip and make the field, relate in particular to low pressure diode chip and manufacture method thereof.
Background technology
For high-voltage diode, low pressure diode all can have special requirement to the structure and the manufacturing process of device, and this mainly is to consider the bigger characteristics of low pressure diode electric leakage.Low pressure diode is by the P+/N+ structure one-tenth of both sides very high concentrations in theory, belongs to Zener breakdown (also being tunnel breakdown), and I-V curve breakdown point is softer, and reverse leakage is bigger.If form the P+/N+ knot so directly inject N+ on dense P+ substrate, although voltage may reach below the 5.1V, electric leakage can reach a milliampere level, can't form well behaved diode basically.See Fig. 1 by device architecture and the preparation technology who injects or spread the low pressure diode of introducing N+ on the P+ substrate of present common employing, briefly introduce as follows:
Inject the denseer N+ of one deck (the N+ concentration and the degree of depth are looked the puncture voltage decision) earlier on the P+ substrate, because compensating action, surface one layer thickness of P+ substrate becomes the P-layer; In the active area of P-floor, introduce the higher N+ district of concentration by injection or diffusion more then, just formed low pressure diode, therefore this diode is actual is exactly the P-N knot that P-floor and N+ district form, different puncture voltages can be drawn partially by the concentration that the first time, N+ injected and the degree of depth and be realized, need explanation:
1) to form generally all be to adopt phosphorus to inject or diffuse to form for twice N+.
2) adopt that the well behaved diode breakdown voltage of this device architecture and prepared is minimum can to reach 5.6V, electric leakage is about tens microamperes, and the voltage uniformity can reach in 5% in the sheet.But this structure can't form the following well behaved low pressure diode of 5.1V, and main cause is that the electric leakage meeting increases (milliampere level) rapidly, and the voltage uniformity can rapid variation (＞8%) in the sheet in addition.
Summary of the invention
The objective of the invention is in order to overcome above-mentioned defective of the prior art, propose the technical scheme of two problems of voltage lack of homogeneity in the bigger than normal and sheet of solution 2.0V-5.1V low pressure diode (P+ substrate) electric leakage, proposed a kind of method and structure thereof that on the P+ substrate, prepares the low pressure diode chip.
A kind of method for preparing the low pressure diode chip on the P+ substrate that the present invention proposes comprises the steps:
Step 1: on the P+ substrate,, form the P-epitaxial loayer directly by extension;
Step 2: pass through to inject boron again in the active area of P-epitaxial loayer, form the P+ trap, its concentration ratio P+ substrate is light, and the different voltages of the diode of follow-up formation are mainly realized by the concentration of P+ trap;
The annealing of step 3:P trap;
Step 4: form N-ring zone by photoetching and etching;
Step 5:N-encircles annealing;
Step 6: form N+ master interface by photoetching and etching;
The annealing of step 7:N+ master interface;
Step 8: the etching contact hole, evaporation or sputter Al do front electrode;
Step 9: thinning back side, evaporation Au does backplate, and so far the low pressure diode on the P+ substrate forms.
A kind of structure for preparing the low pressure diode device on the P+ substrate that the present invention proposes is:
(1) on the P+ substrate, directly passes through extension, form the P-epitaxial loayer;
(2) pass through to inject boron again in the active area of P-epitaxial loayer, form the P+ trap, its concentration ratio P+ substrate is light, and the different puncture voltages of the diode of follow-up formation mainly realize by the implantation dosage of P+ trap;
(3) on the common device architecture of low pressure diode, added the N-potential dividing ring, punctured all in the plane, avoided side direction to puncture, thereby guarantee voltage uniformity in the sheet to guarantee N+/P+;
(4) in active area, inject one deck N+ district at last, form low pressure diode, thus this diode actual be exactly that the P-N of P trap and the formation of N+ district ties.
Innovative technology of the present invention is that the phosphorus that adopts usually when forming N+ district injects or diffusion technology changes to the arsenic injection technology, and reason is that the arsenic diffusion coefficient is less, and one side can guarantee that junction depth is more shallow, and puncture voltage is lower; Can guarantee that on the other hand the P+/N+ knot is single side abrupt junction substantially, reduce electric leakage.
The present invention adopts distinctive P-extension, P+ trap, N-potential dividing ring device architecture and N+ to annotate arsenic technology, the diode voltage that forms on the P+ substrate can be dropped to below the 5.1V, minimumly can reach 2.0V (different puncture voltages mainly the dosage by the P+ trap draw partially adjust), electric leakage is in 100uA, the voltage uniformity is successfully applied to low pressure voltage stabilizing didoe and low-voltage transient voltage suppression diode field in the sheet in 5%.
Description of drawings
Fig. 1 is the device architecture schematic cross-section of preparation low pressure diode chip on the common P+ substrate;
Fig. 2 is the device architecture schematic cross-section of preparation low pressure diode chip on the P+ substrate among the present invention;
The P+ substrate cross-section schematic diagram of Fig. 3 for being adopted among the present invention;
The schematic cross-section of Fig. 4 after for growth P-epitaxial loayer on the P+ substrate among the present invention;
Fig. 5 is for injecting the schematic cross-section of P+ trap in the active area of P-epitaxial loayer among the present invention;
Fig. 6 is the schematic cross-section behind the introducing N-potential dividing ring among the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention being further described, is example with Fig. 2 particularly, and embodiment is as follows:
A kind of method for preparing the low pressure diode chip on the P+ substrate that the present invention proposes comprises the steps:
Step 1:P+ resistance substrate rate is about 0.005≤ρ≤0.008 Ω .cm, chemical vapor-phase growing thickness 3.0-10.0um under 1050 ℃ of conditions, and resistivity is the P-epitaxial loayer of 1.0-5.0 Ω .cm.
Step 2: be formed with the source region by photoetching and etching on the P-epitaxial loayer, annotate boron then and form the P+ trap in active area, the dosage of P+ trap is decided (for the low pressure diode below the 5.1V, dosage is greatly about 1E15-8E15) on puncture voltage.
Step 3:P trap annealing temperature is at 1100 ℃-1200 ℃, time 1h-2h.
Step 4: form N-ring zone by photoetching and etching, N-ring dosage is lighter, greatly about 1E14-8E14.
Step 5:N-encircles annealing temperature about 1100 ℃, time 1h-2h.
Step 6: form N+ master interface by photoetching and etching, N+ master interface is adopted and is annotated arsenic technology, and dosage is greatly about 5E15-2E16.
About 900 ℃ of step 7:N+ master interface annealing temperatures, time 0.5h-1h.
Step 8: the etching contact hole, evaporation or sputter Al do front electrode;
Step 9: thinning back side is to 180 μ m, and evaporation Au does backplate, and so far the low pressure diode on the P+ substrate basically forms.
A kind of structure for preparing the low pressure diode device on the P+ substrate that the present invention proposes is:
(1) on the P+ substrate, directly passes through extension, form the P-epitaxial loayer.
(2) pass through to inject boron again in the active area of P-epitaxial loayer, form the P+ trap, its concentration ratio P+ substrate is light, and the different voltages of the diode of follow-up formation are mainly realized by the concentration of P+ trap.
(3) on the common device architecture of low pressure diode, added the N-potential dividing ring, punctured all in the plane, avoided side direction to puncture, thereby guarantee voltage uniformity in the sheet to guarantee N+/P+.
(4) in active area, inject one deck N+ district at last again, form low pressure diode, thus this diode actual be exactly that the P-N of P trap and the formation of N+ district ties.
Be to be understood that and be; the foregoing description is just to explanation of the present invention; rather than limitation of the present invention; any replacement or modification that does not exceed the unsubstantiality in the connotation scope of the present invention (for example is changed to the N+ substrate with the P+ substrate; adopt the N-extension; N+ trap, the diode device structure that P-potential dividing ring and P+ inject) innovation and creation all fall into protection range of the present invention.
Claims (10)
1. a method for preparing the low pressure diode chip on the P+ substrate is characterized in that, described method comprises the steps:
Step 1: on the P+ substrate,, form the P-epitaxial loayer directly by extension;
Step 2: pass through to inject boron again in the active area of P-epitaxial loayer, form the P+ trap, its concentration ratio P+ substrate is light, and the different puncture voltages of follow-up formed diode mainly realize by the implantation dosage of P+ trap;
The annealing of step 3:P trap;
Step 4: form N-ring zone by photoetching and etching;
Step 5:N-encircles annealing;
Step 6: form N+ master interface by photoetching and etching;
The annealing of step 7:N+ master interface;
Step 8: the etching contact hole, evaporation or sputter Al do front electrode;
Step 9: thinning back side, evaporation Au does backplate, and so far the low pressure diode on the P+ substrate forms.
2. method according to claim 1, it is characterized in that, described step 1 further comprises: P+ resistance substrate rate is about 0.005≤ρ≤0.008 Ω .cm, and the chemical vapor deposition growth thickness is 3.0-10.0um under 1050 ℃ of conditions, and resistivity is the P-epitaxial loayer of 1.0-5.0 Ω .cm.
3. method according to claim 2 is characterized in that, described step 2 further comprises: the implantation dosage of described P+ trap is decided on puncture voltage, and for the low pressure diode below the 5.1V, dosage is in the 1E15-8E15 scope.
4. method according to claim 3 is characterized in that, described step 3 further comprises: P trap annealing temperature is at 1100 ℃-1200 ℃, time 1h-2h.
5. method according to claim 4 is characterized in that, described step 4 further comprises: N-ring dosage is lighter, in the 1E14-8E14 scope.
6. method according to claim 5 is characterized in that, described step 5 further comprises: N-encircles annealing temperature about 1100 ℃, time 1h-2h.
7. method according to claim 6 is characterized in that, described step 6 further comprises: N+ master interface is adopted and is annotated arsenic technology, and dosage is in the 5E15-2E16 scope.
8. method according to claim 7 is characterized in that, described step 7 further comprises: about 900 ℃ of N+ master interface annealing temperatures, time 0.5h-2h.
9. method according to claim 8 is characterized in that, described step 9 further comprises: thinning back side is to 180 μ m.
10. the structure of a preparation low pressure diode device on the P+ substrate is characterized in that described structure is:
(1) on the P+ substrate, directly passes through extension, form the P-epitaxial loayer;
(2) pass through to inject boron again in the active area of P-epitaxial loayer, form the P+ trap, its concentration ratio P+ substrate is light, and the different puncture voltages of the diode of follow-up formation mainly realize by the implantation dosage of P+ trap;
(3) on the common device architecture of low pressure diode, added the N-potential dividing ring, punctured all in the plane, avoided side direction to puncture, thereby guarantee voltage uniformity in the sheet to guarantee N+/P+;
(4) in active area, inject one deck N+ district at last again, form low pressure diode, thus this diode actual be exactly that the P-N of P trap and the formation of N+ district ties.
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| CN 201010606126 CN102142370B (en) | 2010-12-20 | 2010-12-20 | Preparation method of diode chip on P+ substrate and structure of diode chip |
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| CN 201010606126 CN102142370B (en) | 2010-12-20 | 2010-12-20 | Preparation method of diode chip on P+ substrate and structure of diode chip |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102983077A (en) * | 2012-12-06 | 2013-03-20 | 乐山嘉洋科技发展有限公司 | Diode chip manufacturing method |
| CN103107086A (en) * | 2013-01-29 | 2013-05-15 | 淄博晨启电子有限公司 | Manufacturing technique of low-voltage chip and low-voltage chip thereof |
| CN103474427A (en) * | 2013-09-16 | 2013-12-25 | 杭州士兰集成电路有限公司 | Integrated type one-way ultra-low capacitance TVS device and manufacturing method thereof |
| CN103972273A (en) * | 2014-04-18 | 2014-08-06 | 苏州固锝电子股份有限公司 | One-way transient voltage suppression chip of low reverse leakage current |
| CN104091823A (en) * | 2014-07-24 | 2014-10-08 | 江苏捷捷微电子股份有限公司 | Transient-suppression diode chip and manufacturing method thereof |
| CN106653865A (en) * | 2017-02-27 | 2017-05-10 | 杭州赛晶电子有限公司 | P+ N+ type low pressure silicon diffusion sheet with intrinsic region removed, silicon diode and preparation method thereof |
| CN107301998A (en) * | 2017-07-21 | 2017-10-27 | 北京燕东微电子有限公司 | Transient Voltage Suppressor and its manufacture method |
| CN109192785A (en) * | 2018-07-23 | 2019-01-11 | 富芯微电子有限公司 | A kind of the low pressure TVS device and its manufacturing method of Low dark curient |
| CN110010703A (en) * | 2019-04-23 | 2019-07-12 | 江阴新顺微电子有限公司 | A kind of transient voltage suppression diode chip and manufacturing process of punch-through |
| CN111276393A (en) * | 2020-03-11 | 2020-06-12 | 天水天光半导体有限责任公司 | Manufacturing method of wafer-level packaging transient voltage suppression diode |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102983077B (en) * | 2012-12-06 | 2015-10-14 | 乐山嘉洋科技发展有限公司 | A kind of preparation method of diode chip for backlight unit |
| CN102983077A (en) * | 2012-12-06 | 2013-03-20 | 乐山嘉洋科技发展有限公司 | Diode chip manufacturing method |
| CN103107086A (en) * | 2013-01-29 | 2013-05-15 | 淄博晨启电子有限公司 | Manufacturing technique of low-voltage chip and low-voltage chip thereof |
| CN103107086B (en) * | 2013-01-29 | 2015-03-11 | 淄博晨启电子有限公司 | Manufacturing technique of low-voltage chip and low-voltage chip thereof |
| CN103474427A (en) * | 2013-09-16 | 2013-12-25 | 杭州士兰集成电路有限公司 | Integrated type one-way ultra-low capacitance TVS device and manufacturing method thereof |
| CN103474427B (en) * | 2013-09-16 | 2016-01-06 | 杭州士兰集成电路有限公司 | Integrated form one-way ultra-low capacitance TVS device and manufacture method thereof |
| CN103972273A (en) * | 2014-04-18 | 2014-08-06 | 苏州固锝电子股份有限公司 | One-way transient voltage suppression chip of low reverse leakage current |
| CN104091823A (en) * | 2014-07-24 | 2014-10-08 | 江苏捷捷微电子股份有限公司 | Transient-suppression diode chip and manufacturing method thereof |
| CN106653865A (en) * | 2017-02-27 | 2017-05-10 | 杭州赛晶电子有限公司 | P+ N+ type low pressure silicon diffusion sheet with intrinsic region removed, silicon diode and preparation method thereof |
| CN107301998A (en) * | 2017-07-21 | 2017-10-27 | 北京燕东微电子有限公司 | Transient Voltage Suppressor and its manufacture method |
| CN107301998B (en) * | 2017-07-21 | 2023-11-10 | 北京燕东微电子有限公司 | Transient voltage suppressor and method of manufacturing the same |
| CN109192785A (en) * | 2018-07-23 | 2019-01-11 | 富芯微电子有限公司 | A kind of the low pressure TVS device and its manufacturing method of Low dark curient |
| CN110010703A (en) * | 2019-04-23 | 2019-07-12 | 江阴新顺微电子有限公司 | A kind of transient voltage suppression diode chip and manufacturing process of punch-through |
| CN111276393A (en) * | 2020-03-11 | 2020-06-12 | 天水天光半导体有限责任公司 | Manufacturing method of wafer-level packaging transient voltage suppression diode |
| CN111276393B (en) * | 2020-03-11 | 2022-10-04 | 天水天光半导体有限责任公司 | Manufacturing method of wafer-level packaging transient voltage suppression diode |
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