CN103107086A - Manufacturing technique of low-voltage chip and low-voltage chip thereof - Google Patents
Manufacturing technique of low-voltage chip and low-voltage chip thereof Download PDFInfo
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- CN103107086A CN103107086A CN2013100332214A CN201310033221A CN103107086A CN 103107086 A CN103107086 A CN 103107086A CN 2013100332214 A CN2013100332214 A CN 2013100332214A CN 201310033221 A CN201310033221 A CN 201310033221A CN 103107086 A CN103107086 A CN 103107086A
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Abstract
The invention belongs to the technical field of chip manufacturing and preparation, and particularly relates to a manufacturing technique of a low-voltage chip and the low-voltage chip thereof. The manufacturing technique comprises the following steps: (1), a P-shaped primary silicon slice is selected; (2) boron impurities are pre-processed before spreading; (3) the boron impurities are spread; (4) crystal separation and cleaning are conducted; (5) phosphorus impurities are spread; (6) crystal separation and cleaning are conducted; (7) table board processing is conducted; (8) cleaning is conducted before passivation; (9) sodion is cleaned; (10) glass is passivated; and (11) a finished product is manufactured. The manufacturing technique is simple and easy to operate. The low-voltage chip manufactured by the manufacturing technique is low in leakage value and capable of meeting the requirement of low leakage.
Description
Technical field
The invention belongs to the technical field of chip production preparation, be specifically related to a kind of production technology and low pressure chip thereof of low pressure chip.
Background technology
The electric leakage of low pressure chip at present is large, is difficult to satisfy present client to the more and more stricter requirement of this parameter, and for example the transient state of 6.8V voltage supression diode goes to survey and can't accomplish in 20UA with its operating voltage with the leakage current of chip.In order to satisfy the requirement of low electric leakage, the method for some employing shallow junction diffusions causes easy in the process of metal and silicon alloy and the conducting of P/N knot but do like this, causes product failure.Existing low pressure chip production employing low temperature oxidation technology can not satisfy the thickness of oxide layer, can't play the purpose of passivation, more can't meet the tendency freely in packaging technology.The low pressure diffusion can not accomplish that junction depth can reach again the requirement of surge and VC more than 23UM.Cleaning and the protection at mesa technique P/N knot place are most important, are subject to the restriction of environment and process conditions, and the cleannes of existing technique are difficult to reach specification requirement.
Summary of the invention
The object of the invention is to provide for the defective of above-mentioned existence a kind of production technology and low pressure chip thereof of low pressure chip, this technique is simple to operation, and the low pressure chip electrical leakage prepared by this technique is low, satisfies the requirement of low electric leakage.
Technical scheme of the present invention is: a kind of production technology of low pressure chip comprises the following steps:
(1) choose the former silicon chip of P type: selecting resistivity is 0.002～0.0037 ohm/cm, and thickness is the former silicon chip of P type of 290～340 microns;
(2) preliminary treatment before boron impurity diffusion: at first that step (1) is the selected former silicon chip of P type was carrying out chemical corrosion 30 seconds under 1～3 ℃ of temperature conditions in the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in the I liquid that is formed by hydrogen peroxide, ammoniacal liquor and water proportioning after the former silicon chip of P type being rinsed well in pure water, the former silicon chip of P type was cleaned under 80～95 ℃ 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Cleaning complete rear water in I liquid rinses well, again the former silicon chip of P type is placed in the II liquid heat temperature raising that is formed by hydrogen peroxide, hydrochloric acid and water proportioning, the former silicon chip of P type was cleaned 10 minutes, wherein hydrogen peroxide by volume under 80～95 ℃: hydrochloric acid: water is 1:1:6; Bath at last cleans up and dries;
(3) boron impurity diffusion: the former silicon chip of pretreated P type is positioned in stove, and heat temperature raising carries out the diffusion of boron impurity under 1200～1300 ℃ of conditions, then is cooled to 500～600 ℃ and comes out of the stove, and forms the P+ diffusion layer on the upper and lower surface of the former silicon chip of P type;
(4) brilliant minute/clean: the former silicon chip of P type that step (3) is completed the boron impurity diffusion was positioned in hydrofluoric acid and soaks separately, then was positioned in pure water bath and cleaned 1 hour, and described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: advance stove under 200～400 ℃ of conditions, be heated to 900 ℃ and carry out the diffusion of first paragraph phosphorus impurities; Be heated to again and carry out the diffusion of second segment phosphorus impurities under 1200～1300 ℃ of conditions, complete whole phosphorus impurities diffusion, form the phosphorus impurities diffusion layer, be cooled at last 500～600 ℃ and come out of the stove, form U-shaped P/N knot between P+ diffusion layer and phosphorus impurities diffusion layer;
(6) brilliant minute/clean: the former silicon chip of P type that step (5) is completed the phosphorus impurities diffusion was positioned in hydrofluoric acid and soaks separately, then bath was cleaned 1 hour in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblast; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) clean before passivation: at first the wafer of completing steps (7) is used the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning to clean after one minute, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then bath was cleaned after 10 minutes, then put into the solution that is formed by hydrofluoric acid and water proportioning and remove oxide layer, wherein hydrofluoric acid by volume: water is 1:1; At last 80～95 ℃ of lower heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule be heated to 1200 ℃ and inject chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped P/N knot place sodium ion, scavenging period is 30～60 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product is made: clean before nickel plating; Nickel plating/alloy; Scribing; Test; Packing.
In described step (3), the temperature of boron impurity diffusion is 1200～1240 ℃.
In described step (5), the temperature of second segment phosphorus impurities diffusion is 1220～1260 ℃.
In described step (5), the diffusion junction depth of U-shaped P/N knot is greater than 23 microns.
The low pressure chip of described production technology preparation comprises the former silicon chip of P type, and upper surface and the lower surface of the former silicon chip of this P type all are covered with the P+ diffusion layer; The P+ diffusion layer is connected with the phosphorus impurities diffusion layer phase by U-shaped P/N junction structure; The phosphorus impurities diffusion layer is positioned at the groove of U-shaped P/N junction structure, and the upper surface of phosphorus impurities diffusion layer is covered with alloy-layer; On two of U-shaped P/N junction structure upright end ends, the oxychloride of mixing layer is arranged all, be covered with glass passivation layer mixing on the oxychloride layer.
Beneficial effect of the present invention is: (1) is diffused with boron impurity on the former silicon chip of P type, makes the former silicon chip of P type increase the P+ diffusion layer, adds the expansion phosphorus impurities on the P+ diffusion layer, obtains the phosphorus impurities diffusion layer, makes P+ diffusion layer and phosphorus impurities diffusion layer form U-shaped P/N knot.Diffused with boron impurity on the former silicon chip of P type, the gradient of restraining the phosphorus impurities diffusion by the boron impurity of high concentration, reach gradual to the abrupt junction purpose of transition, diffusion gradient is steep like this, improved diffusion gradient, made diffusion close to the CONCENTRATION DISTRIBUTION of P/N knot, and also dwindle depletion layer, reach the purpose that reduces electric leakage, can fully reduce electrical leakage.
(2) the interim diffusion way of two-part is adopted in the diffusion of phosphorus impurities, with the decomposition of diffusion impurity, accumulation, the process control that distributes again in as far as possible little line style diffusion, select the districution temperature of phosphorus impurities the best as diffusion temperature, in conjunction with the needed time of distribution again of phosphorus impurities, to spread more than junction depth is controlled at 23UM, guarantee enough electric field width, guaranteed that also enough spaces complete the purpose that the alloy of metal and silicon reaches bonding, be beneficial to carrying out smoothly of alloy, and avoid product to cross the shallow inefficacy that produces because of the diffusion junction depth.
(3) when carrying out the cleaning of sodium ion, wafer is put into quartz ampoule be heated to 1200 ℃ and inject chlorine and oxygen, adopt the long-time oxidation technology of high temperature, the sodium ion at the U-shaped P/N knot of absorption place pollutes, high temperature chlorine constraint sodium ion, control sodium ion in the mobility at U-shaped P/N knot place, the sodium ion at U-shaped P/N knot place is adsorbed in the silicon dioxide layer that is at high temperature produced by silicon and oxide layer, the prevention sodium ion moves the electric leakage that causes.Can further reduce electrical leakage.
(4) use the passivation mode of glass protection that the exposed parts that U-shaped P/N ties is protected, improve stability and the reliability of product, eliminated the hidden danger that product may exist.Adopt the mode of glass passivation protection to protect U-shaped P/N knot, use the reliability of product and stability to have one significantly to promote.
Technical target of the product is as follows: (1) product voltage bias value is in+/-3% left and right; (2) product is surveyed electrical leakage below 30UA under operating voltage; (3) product can bear the impact of 110% surge of setting; (4) product can be completed the target of the reliability test zero failure shown in form 1.
Form 1
| Sequence number | Experimental project | Experiment condition | Experiment quantity | Inefficacy quantity |
| 1 | Can |
5 seconds | 22 | 0 |
| 2 | Lead strain | 10 seconds | 70 | 0 |
| 3 | The lead-in |
3 times | 35 | 0 |
| 4 | Working life | 1000 hours | 22 | 0 |
| 5 | High temperature reverse bias | 1000 hours | 40 | 0 |
| 6 | The discontinuous operation life-span | 1000 cycles | 22 | 0 |
| 7 | Reverse flow is gushed electric current | 10/1000 | All | 0 |
| 8 | The high temperature storage life-span | 1000 hours | 22 | 0 |
| 9 | Humidity | 100 hours | 22 | 0 |
| 10 | Autoclaving | 4 hours | 22 | 0 |
| 11 | Thermal shock | 10 cycles | 22 | 0 |
| 12 | Temperature cycles | 10 cycles | 22 | 0 |
| 13 | Anti-sweating heat | 10 seconds | 125 | 0 |
Description of drawings
Fig. 1 is the structural representation of specific embodiment of the invention midplane low pressure chip.
Wherein, 1 is the former silicon chip of P type, and 2 is the P+ diffusion layer, and 3 is the phosphorus impurities diffusion layer, and 4 is alloy-layer, and 5 is U-shaped P/N junction structure, and 6 for mixing the oxychloride layer, and 7 is glass passivation layer.
Embodiment
Describe the present invention below by specific embodiment.
Embodiment 1
A kind of production technology of low pressure chip comprises the following steps:
(1) choose the former silicon chip of P type: selecting resistivity is 0.002 ohm/cm, and thickness is the former silicon chip of P type of 290 microns;
(2) preliminary treatment before boron impurity diffusion: at first that step (1) is the selected former silicon chip of P type was carrying out chemical corrosion 30 seconds under 1～3 ℃ of temperature conditions in the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in the I liquid that is formed by hydrogen peroxide, ammoniacal liquor and water proportioning after the former silicon chip of P type being rinsed well in pure water, the former silicon chip of P type was cleaned under 80 ℃ 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Cleaning complete rear water in I liquid rinses well, again the former silicon chip of P type is placed in the II liquid heat temperature raising that is formed by hydrogen peroxide, hydrochloric acid and water proportioning, the former silicon chip of P type was cleaned 10 minutes, wherein hydrogen peroxide by volume under 80 ℃: hydrochloric acid: water is 1:1:6; Bath at last cleans up and dries;
(3) boron impurity diffusion: the former silicon chip of pretreated P type is positioned in stove, and heat temperature raising carries out the diffusion of boron impurity under 1200 ℃ of conditions, then is cooled to 500 ℃ and comes out of the stove, and forms the P+ diffusion layer on the upper and lower surface of the former silicon chip of P type;
(4) brilliant minute/clean: the former silicon chip of P type that step (3) is completed the boron impurity diffusion was positioned in hydrofluoric acid and soaks separately, then was positioned in pure water bath and cleaned 1 hour, and described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: advance stove under 200 ℃ of conditions, be heated to 900 ℃ and carry out the diffusion of first paragraph phosphorus impurities; Be heated to again and carry out the diffusion of second segment phosphorus impurities under 1200 ℃ of conditions, complete whole phosphorus impurities diffusion, form the phosphorus impurities diffusion layer, be cooled at last 500 ℃ and come out of the stove, form U-shaped P/N knot between P+ diffusion layer and phosphorus impurities diffusion layer;
(6) brilliant minute/clean: the former silicon chip of P type that step (5) is completed the phosphorus impurities diffusion was positioned in hydrofluoric acid and soaks separately, then bath was cleaned 1 hour in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblast; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) clean before passivation: at first the wafer of completing steps (7) is used the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning to clean after one minute, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then bath was cleaned after 10 minutes, then put into the solution that is formed by hydrofluoric acid and water proportioning and remove oxide layer, wherein hydrofluoric acid by volume: water is 1:1; At last 80 ℃ of lower heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule be heated to 1200 ℃ and inject chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped P/N knot place sodium ion, scavenging period is 30 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product is made: clean before nickel plating; Nickel plating/alloy; Scribing; Test; Packing.
In described step (5), the diffusion junction depth of U-shaped P/N knot is greater than 23 microns.
The low pressure chip of described production technology preparation comprises the former silicon chip 1 of P type, and upper surface and the lower surface of the former silicon chip 1 of this P type all are covered with P+ diffusion layer 2; P+ diffusion layer 2 is connected with phosphorus impurities diffusion layer 3 by U-shaped P/N junction structure 5; Phosphorus impurities diffusion layer 3 is positioned at the groove of U-shaped P/N junction structure 5, and the upper surface of phosphorus impurities diffusion layer 3 is covered with alloy-layer 4; On two of U-shaped P/N junction structure 5 upright end ends, the oxychloride of mixing layer 6 is arranged all, be covered with glass passivation layer 7 on oxychloride layer 6 mixing.
Embodiment 2
A kind of production technology of low pressure chip comprises the following steps:
(1) choose the former silicon chip of P type: selecting resistivity is 0.0037 ohm/cm, and thickness is the former silicon chip of P type of 340 microns;
(2) preliminary treatment before boron impurity diffusion: at first that step (1) is the selected former silicon chip of P type was carrying out chemical corrosion 30 seconds under 1～3 ℃ of temperature conditions in the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in the I liquid that is formed by hydrogen peroxide, ammoniacal liquor and water proportioning after the former silicon chip of P type being rinsed well in pure water, the former silicon chip of P type was cleaned under 95 ℃ 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Cleaning complete rear water in I liquid rinses well, again the former silicon chip of P type is placed in the II liquid heat temperature raising that is formed by hydrogen peroxide, hydrochloric acid and water proportioning, the former silicon chip of P type was cleaned 10 minutes, wherein hydrogen peroxide by volume under 95 ℃: hydrochloric acid: water is 1:1:6; Bath at last cleans up and dries;
(3) boron impurity diffusion: the former silicon chip of pretreated P type is positioned in stove, and heat temperature raising carries out the diffusion of boron impurity under 1300 ℃ of conditions, then is cooled to 600 ℃ and comes out of the stove, and forms the P+ diffusion layer on the upper and lower surface of the former silicon chip of P type;
(4) brilliant minute/clean: the former silicon chip of P type that step (3) is completed the boron impurity diffusion was positioned in hydrofluoric acid and soaks separately, then was positioned in pure water bath and cleaned 1 hour, and described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: advance stove under 400 ℃ of conditions, be heated to 900 ℃ and carry out the diffusion of first paragraph phosphorus impurities; Be heated to again and carry out the diffusion of second segment phosphorus impurities under 1300 ℃ of conditions, complete whole phosphorus impurities diffusion, form the phosphorus impurities diffusion layer, be cooled at last 600 ℃ and come out of the stove, form U-shaped P/N knot between P+ diffusion layer and phosphorus impurities diffusion layer;
(6) brilliant minute/clean: the former silicon chip of P type that step (5) is completed the phosphorus impurities diffusion was positioned in hydrofluoric acid and soaks separately, then bath was cleaned 1 hour in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblast; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) clean before passivation: at first the wafer of completing steps (7) is used the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning to clean after one minute, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then bath was cleaned after 10 minutes, then put into the solution that is formed by hydrofluoric acid and water proportioning and remove oxide layer, wherein hydrofluoric acid by volume: water is 1:1; At last 95 ℃ of lower heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule be heated to 1200 ℃ and inject chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped P/N knot place sodium ion, scavenging period is 60 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product is made: clean before nickel plating; Nickel plating/alloy; Scribing; Test; Packing.
In described step (5), the diffusion junction depth of U-shaped P/N knot is greater than 23 microns.
The low pressure chip of described production technology preparation comprises the former silicon chip 1 of P type, and upper surface and the lower surface of the former silicon chip 1 of this P type all are covered with P+ diffusion layer 2; P+ diffusion layer 2 is connected with phosphorus impurities diffusion layer 3 by U-shaped P/N junction structure 5; Phosphorus impurities diffusion layer 3 is positioned at the groove of U-shaped P/N junction structure 5, and the upper surface of phosphorus impurities diffusion layer 3 is covered with alloy-layer 4; On two of U-shaped P/N junction structure 5 upright end ends, the oxychloride of mixing layer 6 is arranged all, be covered with glass passivation layer 7 on oxychloride layer 6 mixing.
A kind of production technology of low pressure chip comprises the following steps:
(1) choose the former silicon chip of P type: selecting resistivity is 0.0035 ohm/cm, and thickness is the former silicon chip of P type of 310 microns;
(2) preliminary treatment before boron impurity diffusion: at first that step (1) is the selected former silicon chip of P type was carrying out chemical corrosion 30 seconds under 1～3 ℃ of temperature conditions in the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in the I liquid that is formed by hydrogen peroxide, ammoniacal liquor and water proportioning after the former silicon chip of P type being rinsed well in pure water, the former silicon chip of P type was cleaned under 90 ℃ 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Cleaning complete rear water in I liquid rinses well, again the former silicon chip of P type is placed in the II liquid heat temperature raising that is formed by hydrogen peroxide, hydrochloric acid and water proportioning, the former silicon chip of P type was cleaned 10 minutes, wherein hydrogen peroxide by volume under 90 ℃: hydrochloric acid: water is 1:1:6; Bath at last cleans up and dries;
(3) boron impurity diffusion: the former silicon chip of pretreated P type is positioned in stove, and heat temperature raising carries out the diffusion of boron impurity under 1240 ℃ of conditions, then is cooled to 550 ℃ and comes out of the stove, and forms the P+ diffusion layer on the upper and lower surface of the former silicon chip of P type;
(4) brilliant minute/clean: the former silicon chip of P type that step (3) is completed the boron impurity diffusion was positioned in hydrofluoric acid and soaks separately, then was positioned in pure water bath and cleaned 1 hour, and described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: advance stove under 300 ℃ of conditions, be heated to 900 ℃ and carry out the diffusion of first paragraph phosphorus impurities; Be heated to again and carry out the diffusion of second segment phosphorus impurities under 1220 ℃ of conditions, complete whole phosphorus impurities diffusion, form the phosphorus impurities diffusion layer, be cooled at last 550 ℃ and come out of the stove, form U-shaped P/N knot between P+ diffusion layer and phosphorus impurities diffusion layer;
(6) brilliant minute/clean: the former silicon chip of P type that step (5) is completed the phosphorus impurities diffusion was positioned in hydrofluoric acid and soaks separately, then bath was cleaned 1 hour in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblast; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) clean before passivation: at first the wafer of completing steps (7) is used the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning to clean after one minute, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then bath was cleaned after 10 minutes, then put into the solution that is formed by hydrofluoric acid and water proportioning and remove oxide layer, wherein hydrofluoric acid by volume: water is 1:1; At last 90 ℃ of lower heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule be heated to 1200 ℃ and inject chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped P/N knot place sodium ion, scavenging period is 50 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product is made: clean before nickel plating; Nickel plating/alloy; Scribing; Test; Packing.
In described step (5), the diffusion junction depth of U-shaped P/N knot is greater than 23 microns.
The low pressure chip of described production technology preparation comprises the former silicon chip 1 of P type, and upper surface and the lower surface of the former silicon chip 1 of this P type all are covered with P+ diffusion layer 2; P+ diffusion layer 2 is connected with phosphorus impurities diffusion layer 3 by U-shaped P/N junction structure 5; Phosphorus impurities diffusion layer 3 is positioned at the groove of U-shaped P/N junction structure 5, and the upper surface of phosphorus impurities diffusion layer 3 is covered with alloy-layer 4; On two of U-shaped P/N junction structure 5 upright end ends, the oxychloride of mixing layer 6 is arranged all, be covered with glass passivation layer 7 on oxychloride layer 6 mixing.
Embodiment 4
A kind of production technology of low pressure chip comprises the following steps:
(1) choose the former silicon chip of P type: selecting resistivity is 0.0025 ohm/cm, and thickness is the former silicon chip of P type of 320 microns;
(2) preliminary treatment before boron impurity diffusion: at first that step (1) is the selected former silicon chip of P type was carrying out chemical corrosion 30 seconds under 1～3 ℃ of temperature conditions in the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in the I liquid that is formed by hydrogen peroxide, ammoniacal liquor and water proportioning after the former silicon chip of P type being rinsed well in pure water, the former silicon chip of P type was cleaned under 85 ℃ 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Cleaning complete rear water in I liquid rinses well, again the former silicon chip of P type is placed in the II liquid heat temperature raising that is formed by hydrogen peroxide, hydrochloric acid and water proportioning, the former silicon chip of P type was cleaned 10 minutes, wherein hydrogen peroxide by volume under 85 ℃: hydrochloric acid: water is 1:1:6; Bath at last cleans up and dries;
(3) boron impurity diffusion: the former silicon chip of pretreated P type is positioned in stove, and heat temperature raising carries out the diffusion of boron impurity under 1230 ℃ of conditions, then is cooled to 570 ℃ and comes out of the stove, and forms the P+ diffusion layer on the upper and lower surface of the former silicon chip of P type;
(4) brilliant minute/clean: the former silicon chip of P type that step (3) is completed the boron impurity diffusion was positioned in hydrofluoric acid and soaks separately, then was positioned in pure water bath and cleaned 1 hour, and described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: advance stove under 350 ℃ of conditions, be heated to 900 ℃ and carry out the diffusion of first paragraph phosphorus impurities; Be heated to again and carry out the diffusion of second segment phosphorus impurities under 1260 ℃ of conditions, complete whole phosphorus impurities diffusion, form the phosphorus impurities diffusion layer, be cooled at last 570 ℃ and come out of the stove, form U-shaped P/N knot between P+ diffusion layer and phosphorus impurities diffusion layer;
(6) brilliant minute/clean: the former silicon chip of P type that step (5) is completed the phosphorus impurities diffusion was positioned in hydrofluoric acid and soaks separately, then bath was cleaned 1 hour in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblast; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) clean before passivation: at first the wafer of completing steps (7) is used the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning to clean after one minute, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then bath was cleaned after 10 minutes, then put into the solution that is formed by hydrofluoric acid and water proportioning and remove oxide layer, wherein hydrofluoric acid by volume: water is 1:1; At last 85 ℃ of lower heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule be heated to 1200 ℃ and inject chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped P/N knot place sodium ion, scavenging period is 55 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product is made: clean before nickel plating; Nickel plating/alloy; Scribing; Test; Packing.
In described step (5), the diffusion junction depth of U-shaped P/N knot is greater than 23 microns.
The low pressure chip of described production technology preparation comprises the former silicon chip 1 of P type, and upper surface and the lower surface of the former silicon chip 1 of this P type all are covered with P+ diffusion layer 2; P+ diffusion layer 2 is connected with phosphorus impurities diffusion layer 3 by U-shaped P/N junction structure 5; Phosphorus impurities diffusion layer 3 is positioned at the groove of U-shaped P/N junction structure 5, and the upper surface of phosphorus impurities diffusion layer 3 is covered with alloy-layer 4; On two of U-shaped P/N junction structure 5 upright end ends, the oxychloride of mixing layer 6 is arranged all, be covered with glass passivation layer 7 on oxychloride layer 6 mixing.
Claims (5)
1. the production technology of a low pressure chip comprises the following steps:
(1) choose the former silicon chip of P type: selecting resistivity is 0.002～0.0037 ohm/cm, and thickness is the P of 290～340 microns
The former silicon chip of type;
(2) preliminary treatment before boron impurity diffusion: at first that step (1) is the selected former silicon chip of P type was carrying out chemical corrosion 30 seconds under 1～3 ℃ of temperature conditions in the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in the I liquid that is formed by hydrogen peroxide, ammoniacal liquor and water proportioning after the former silicon chip of P type being rinsed well in pure water, the former silicon chip of P type was cleaned under 80～95 ℃ 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Cleaning complete rear water in I liquid rinses well, again the former silicon chip of P type is placed in the II liquid heat temperature raising that is formed by hydrogen peroxide, hydrochloric acid and water proportioning, the former silicon chip of P type was cleaned 10 minutes, wherein hydrogen peroxide by volume under 80～95 ℃: hydrochloric acid: water is 1:1:6; Bath at last cleans up and dries;
(3) boron impurity diffusion: the former silicon chip of pretreated P type is positioned in stove, and heat temperature raising carries out the diffusion of boron impurity under 1200～1300 ℃ of conditions, then is cooled to 500～600 ℃ and comes out of the stove, and forms the P+ diffusion layer on the upper and lower surface of the former silicon chip of P type;
(4) brilliant minute/clean: the former silicon chip of P type that step (3) is completed the boron impurity diffusion was positioned in hydrofluoric acid and soaks separately, then was positioned in pure water bath and cleaned 1 hour, and described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: advance stove under 200～400 ℃ of conditions, be heated to 900 ℃ and carry out the diffusion of first paragraph phosphorus impurities; Be heated to again and carry out the diffusion of second segment phosphorus impurities under 1200～1300 ℃ of conditions, complete whole phosphorus impurities diffusion, form the phosphorus impurities diffusion layer, be cooled at last 500～600 ℃ and come out of the stove, form U-shaped P/N knot between P+ diffusion layer and phosphorus impurities diffusion layer;
(6) brilliant minute/clean: the former silicon chip of P type that step (5) is completed the phosphorus impurities diffusion was positioned in hydrofluoric acid and soaks separately, then bath was cleaned 1 hour in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblast; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) clean before passivation: at first the wafer of completing steps (7) is used the mixed acid that is formed by nitric acid, hydrofluoric acid and glacial acetic acid proportioning to clean after one minute, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then bath was cleaned after 10 minutes, then put into the solution that is formed by hydrofluoric acid and water proportioning and remove oxide layer, wherein hydrofluoric acid by volume: water is 1:1; At last 80～95 ℃ of lower heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule be heated to 1200 ℃ and inject chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped P/N knot place sodium ion, scavenging period is 30～60 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product is made: clean before nickel plating; Nickel plating/alloy; Scribing; Test; Packing.
2. the production technology of low pressure chip according to claim 1, is characterized in that, in described step (3), the temperature of boron impurity diffusion is 1200～1240 ℃.
3. the production technology of low pressure chip according to claim 1, is characterized in that, in described step (5), the temperature of second segment phosphorus impurities diffusion is 1220～1260 ℃.
4. the production technology of low pressure chip according to claim 1, is characterized in that, in described step (5), the diffusion junction depth of U-shaped P/N knot is greater than 23 microns.
5. the low pressure chip of the described production technology preparation of claim 1, is characterized in that, comprise the former silicon chip of P type, upper surface and the lower surface of the former silicon chip of this P type all are covered with the P+ diffusion layer; The P+ diffusion layer is connected with the phosphorus impurities diffusion layer phase by U-shaped P/N junction structure; The phosphorus impurities diffusion layer is positioned at the groove of U-shaped P/N junction structure, and the upper surface of phosphorus impurities diffusion layer is covered with alloy-layer; On two of U-shaped P/N junction structure upright end ends, the oxychloride of mixing layer is arranged all, be covered with glass passivation layer mixing on the oxychloride layer.
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