CN104465773B - The terminal structure and its manufacture method of metal oxide semiconductor field effect tube - Google Patents
The terminal structure and its manufacture method of metal oxide semiconductor field effect tube Download PDFInfo
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- CN104465773B CN104465773B CN201410629243.1A CN201410629243A CN104465773B CN 104465773 B CN104465773 B CN 104465773B CN 201410629243 A CN201410629243 A CN 201410629243A CN 104465773 B CN104465773 B CN 104465773B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 230000005669 field effect Effects 0.000 title claims abstract description 18
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 18
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000002513 implantation Methods 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- 239000000243 solution Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims 6
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The present invention relates to a kind of terminal structure of metal oxide semiconductor field effect tube, cut-off ring including N-type, also include being formed at the first p-type low doped region and the second p-type low doped region ended between ring and active area, implantation dosage 1.5*10 by ion implanting11~2*1013/cm2, Implantation Energy is 20 kiloelectron-volts~80 kiloelectron-volts, and the first p-type low doped region described in two p-type low doped regions is relative closer to the active area, and the length of the first p-type low doped region is less than the length of the second p-type low doped region.The invention further relates to a kind of manufacture method of the terminal structure of metal oxide semiconductor field effect tube.The present invention reduces surface field, raising MOSFET breakdown voltage using two low-doped P areas, it instead of the terminal structure of traditional multiple potential dividing rings, substantially reduce terminal size, improve chip effectively utilize area, make the parameter of chip more excellent under equal area.
Description
Technical field
The present invention relates to semiconductor technology, more particularly to a kind of terminal knot of metal oxide semiconductor field effect tube
Structure, further relate to a kind of manufacture method of the terminal structure of metal oxide semiconductor field effect tube.
Background technology
Metal oxide semiconductor field effect tube (MOSFET) market competition increasingly encourages, and each producer is all by every means
Cost is reduced, the scheme of use mainly effectively utilizes area including improving current density, improving chip, reduces terminal size.
MOSFET terminal still uses partial pressure ring structure mostly at present, be chip occupying area the shortcomings that this structure compared with
Greatly.
The content of the invention
Based on this, it is necessary to provide a kind of terminal structure of the less metal oxide semiconductor field effect tube of size.
A kind of terminal structure of metal oxide semiconductor field effect tube, includes the cut-off ring of N-type, in addition to passes through ion
Injection is formed at the first p-type low doped region and the second p-type low doped region between the cut-off ring and active area, injectant
Measure as 1.5*1011~2*1013/cm2, Implantation Energy is 20 kiloelectron-volts~80 kiloelectron-volts, institute in two p-type low doped regions
State that the first p-type low doped region is relative closer to the active area, the length of the first p-type low doped region is less than described the
The length of two p-type low doped regions.
In one of the embodiments, the length of the first p-type low doped region is 10~50 microns, the 2nd P
The length of type low doped region is 30~200 microns.
In one of the embodiments, the spacing of the first p-type low doped region and the second p-type low doped region is 4
~20 microns.
In one of the embodiments, in addition to located at the first p-type low doped region close to the active area side
P type trap zone, the P type trap zone is connected with the first p-type low doped region.
It there is a need to the manufacture method that a kind of terminal structure of metal oxide semiconductor field effect tube is provided.
A kind of manufacture method of the terminal structure of metal oxide semiconductor field effect tube, comprises the following steps：N-type is provided
Substrate；Oxide layer is formed in the N-type substrate；Two p type island regions are formed by photoetching and the etching oxide layer and inject window；
Window implanting p-type foreign ion into the N-type substrate is injected by two p type island regions, the first p-type for being formed close to active area is low
Doped region and the second p-type low doped region for being relatively distant from active area, implantation dosage 1.5*1011~2*1013/cm2, injection
Energy is 20 kiloelectron-volts~80 kiloelectron-volts；It is low-doped that the length of the first p-type low doped region is less than second p-type
The length in region；Processing is diffused to the foreign ion of the first p-type low doped region and the second p-type low doped region；
Polysilicon field plate is formed, the polysilicon field plate covers the oxide layer above the first p-type low doped region；Described second
Side photoetching of the p-type low doped region away from the first p-type low doped region simultaneously injects N-type ion formation cut-off ring.
In one of the embodiments, to the impurity of the first p-type low doped region and the second p-type low doped region from
Son was diffused after the step of processing, and the length of the first p-type low doped region is 10~50 microns, second p-type
The length of low doped region is 30~200 microns, the spacing of the first p-type low doped region and the second p-type low doped region
For 4~20 microns.
In one of the embodiments, after the step of formation polysilicon field plate, it is low to be additionally included in first p-type
Doped region is formed after diffusion and is connected with the first p-type low doped region close to the side implanting p-type ion of the active area
P type trap zone the step of.
In one of the embodiments, it is described in the step of N-type substrate forms oxide layer, the oxide layer of formation
Thickness is 800~1500 microns.
In one of the embodiments, it is described that two p type island regions injection windows are formed by photoetching and the etching oxide layer
The step of in, be using BOE solution carry out wet etching.
In one of the embodiments, in described the step of carrying out wet etching using BOE solution, latter two P of corrosion
The sacrificial oxide layer that thickness is less than 20 angstroms is remained with type area injection window.
Above-mentioned MOSFET terminal structure and its manufacture method, using two low-doped P- areas come reduce surface field,
MOSFET breakdown voltage is improved, instead of the terminal structure of traditional multiple potential dividing rings, terminal size is substantially reduced, improves
Chip effectively utilizes area, makes the parameter of chip more excellent under equal area.
Brief description of the drawings
By being more particularly described for the preferred embodiments of the present invention shown in accompanying drawing, above and other mesh of the invention
, feature and advantage will become more fully apparent.The identical reference instruction identical part in whole accompanying drawings, and do not carve
Meaning draws accompanying drawing by actual size equal proportion scaling, it is preferred that emphasis is shows the purport of the present invention.
Fig. 1 is the schematic diagram of the MOSFET chips provided with terminal；
Fig. 2 is the schematic cross-section of MOSFET terminal structures in an embodiment；
Fig. 3 is the flow chart of the manufacture method of MOSFET terminal structure in an embodiment.
Embodiment
For the ease of understanding the present invention, the present invention is described more fully below with reference to relevant drawings.In accompanying drawing
Give the preferred embodiment of the present invention.But the present invention can realize in many different forms, however it is not limited to this paper institutes
The embodiment of description.On the contrary, the purpose for providing these embodiments is made to the disclosure more thorough and comprehensive.
It should be noted that when element is referred to as " being fixed on " another element, it can be directly on another element
Or there may also be element placed in the middle.When an element is considered as " connection " another element, it can be directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " on ",
" under ", "left", "right" and similar statement for illustrative purposes only.
Unless otherwise defined, all of technologies and scientific terms used here by the article is with belonging to technical field of the invention
The implication that technical staff is generally understood that is identical.Term used in the description of the invention herein is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term as used herein " and/or " include one or more phases
The arbitrary and all combination of the Listed Items of pass.
The present invention provides a kind of MOSFET terminal structure.Fig. 1 is the schematic diagram of the MOSFET chips provided with terminal, wherein
Part of the edge without filling lines is terminal, and it is active area that, which there is the part of filling lines centre,.Referring to Fig. 2, terminal structure includes N
The cut-off ring 40 of type, the first p-type low doped region 22 and the second p-type low doped region 24.Wherein cut-off ring 40 is located in terminal
Close to the side of chip boundary, the first p-type low doped region 22 and the second p-type low doped region 24 are located at terminal in chip
The side of the heart, the i.e. side close to active area.First p-type low doped region 22 and the second p-type low doped region 24 pass through ion
Thermal diffusion is formed after injection, implantation dosage 1.5*1011~2*1013/cm2, Implantation Energy is 20 kiloelectron-volts~80,000 electronics
Volt.The length of first p-type low doped region 22 is less than the length of the second p-type low doped region 24, and the length refers to left and right in Fig. 2
Length on direction.
Above-mentioned MOSFET terminal structure, reduce surface field using two low-doped P- areas, improve MOSFET's
Breakdown voltage, the terminal structure of traditional multiple potential dividing rings is instead of, substantially reduce terminal size, improve the effective of chip
Using area, make the parameter of chip more excellent under equal area.By taking 600 volts of pressure-resistant products as an example, using partial pressure ring structure
Terminal size in 300 microns, and the MOSFET of present invention terminal structure size is only 100 microns~250 microns.
In one of the embodiments, the length of the first p-type low doped region 22 is 10~50 microns, the second p-type low-mix
The length in miscellaneous region 24 is 30~200 microns.The spacing of first p-type low doped region 22 and the second p-type low doped region 24 is 4
~20 microns.
Structure shown in Fig. 2 also includes P type trap zone 30, dielectric layer 50 (the present embodiment includes oxide layer and boron-phosphorosilicate glass)
And polysilicon field plate 60.P type trap zone 30 is located at the first p-type low doped region 22 close to the side of active area, with the first p-type low-mix
Miscellaneous region 22 connects.The one end of polysilicon field plate 60 is overlapped in the first p-type low doped region 22 of covering and the second p-type low doped region
24 dielectric layer 50, the other end are extended in P type trap zone 30.
The present invention also provides a kind of manufacture method of MOSFET terminal structure, referring to Fig. 3, MOSFET terminal structure
Manufacture method comprises the following steps：
S110, there is provided N-type substrate.
S120, oxide layer is formed in N-type substrate.
In the present embodiment, it is that thermally grown a layer thickness is 800~1500 microns of oxide layer.
S130, two p type island regions are formed by photoetching and etching and inject window.
Photoetching is simultaneously performed etching, and the oxide layer formed in step S120 is etched into two p type island region injection windows.In this reality
It is to use wet etching to apply in example, can specifically use BOE solution as etching liquid, i.e. HF and NH4The buffering erosion that F is mixed to form
Carve liquid.In the present embodiment, the oxide layer at two p type island region injection windows will not be completely removed, but retained a thin layer and made
For sacrificial oxide layer, the thickness of sacrificial oxide layer should be less thanIn the present embodiment, corrosion temperature is set to 21 degrees Celsius, when
Between be 22 minutes.
S140, two p-type low doped regions are formed by ion implanting.
Window implanting p-type ion is injected by two p type island regions.Implantation dosage is 1.5*1011~2*1013/cm2, inject energy
Measure as 20 kiloelectron-volts~80 kiloelectron-volts, so as to form low-doped P- areas.Wherein the first p-type low doped region is more leaned on relatively
Nearly active area, the second p-type low doped region are relatively distant from active area, and the length of the first p-type low doped region should be less than the second p-type
The length of low doped region, preferable potential lines could be obtained.
S150, processing is diffused to the foreign ion of two p-type low doped regions.
Wafer (Wafer) is heated, the foreign ion of two p-type low doped regions is produced diffusion.
S160, form polysilicon field plate.
Oxide layer above the polysilicon field plate covering p-type low doped region of formation.
S170, photoetching simultaneously inject N-type ion formation cut-off ring.
In side of the second p-type low doped region away from the first p-type low doped region (i.e. close to the side of chip boundary)
Photoetching simultaneously injects the cut-off ring that N-type ion forms N+.
In one of the embodiments, the first p-type low doped region is additionally included in close to active area after step S160
Side implanting p-type ion, after diffusion formed be connected with the first p-type low doped region P type trap zone the step of.Injection can pass through
Polysilicon field plate carries out autoregistration injection, without carrying out photoetching.
In one of the embodiments, the length of the first p-type low doped region after step S150 diffusions is micro- for 10~50
Rice, the length of the second p-type low doped region is 30~200 microns.First p-type low doped region and the second p-type low doped region
Spacing be 4~20 microns.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Therefore the limitation to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that for one of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (7)
1. a kind of manufacture method of the terminal structure of metal oxide semiconductor field effect tube, comprises the following steps：
N-type substrate is provided；
Oxide layer is formed in the N-type substrate；
The p type island region of only two is formed by photoetching and the etching oxide layer and injects window；
Inject window implanting p-type foreign ions into the N-type substrate by two p type island regions, formed with and the p-type of only two
Low doped region, including the first p-type low doped region of close active area and the second p-type doped regions for being relatively distant from active area
Domain, implantation dosage 1.5*1011~2*1013/cm2, Implantation Energy is 20 kiloelectron-volts~80 kiloelectron-volts；First p-type
The length of low doped region is less than the length of the second p-type low doped region；
Processing is diffused to the foreign ion of the first p-type low doped region and the second p-type low doped region；
Polysilicon field plate is formed, the polysilicon field plate covers the oxide layer above the first p-type low doped region；
In side photoetching of the second p-type low doped region away from the first p-type low doped region and inject N-type ion shape
Into cut-off ring；
The step of processing is diffused to the foreign ion of the first p-type low doped region and the second p-type low doped region it
Afterwards, the length of the first p-type low doped region is 10~50 microns, the length of the second p-type low doped region for 30~
200 microns, the spacing of the first p-type low doped region and the second p-type low doped region is 4~20 microns.
2. the manufacture method of the terminal structure of metal oxide semiconductor field effect tube according to claim 1, its feature
It is, after described the step of forming polysilicon field plate, is additionally included in the first p-type low doped region close to the active area
Side implanting p-type ion, after diffusion formed be connected with the first p-type low doped region P type trap zone the step of.
3. the manufacture method of the terminal structure of metal oxide semiconductor field effect tube according to claim 1, its feature
It is, described in the step of N-type substrate forms oxide layer, the thickness of the oxide layer of formation is 800~1500 microns.
4. the manufacture method of the terminal structure of metal oxide semiconductor field effect tube according to claim 1, its feature
It is, it is described to be formed by photoetching and the etching oxide layer in the step of window is injected in two p type island regions, it is to use BOE solution
Carry out wet etching.
5. the manufacture method of the terminal structure of metal oxide semiconductor field effect tube according to claim 4, its feature
It is, in described the step of carrying out wet etching using BOE solution, thickness is remained with latter two p type island region injection window of corrosion
Sacrificial oxide layer of the degree less than 20 angstroms.
6. a kind of terminal structure of metal oxide semiconductor field effect tube, include the cut-off ring of N-type, it is characterised in that also wrap
Include by ion implanting be formed at it is described cut-off ring and active area between the first p-type low doped region and the second p-type it is low-doped
Region, implantation dosage 1.5*1011~2*1013/cm2, Implantation Energy is 20 kiloelectron-volts~80 kiloelectron-volts, and two p-types are low
First p-type low doped region described in doped region is relative closer to the active area, the length of the first p-type low doped region
Degree is less than the length of the second p-type low doped region, and the length of the first p-type low doped region is 10~50 microns, institute
The length for stating the second p-type low doped region is 30~200 microns, the first p-type low doped region and the second p-type doped regions
The spacing in domain is 4~20 microns.
7. the terminal structure of metal oxide semiconductor field effect tube according to claim 6, it is characterised in that also include
P type trap zone located at the first p-type low doped region close to the active area side, the P type trap zone and first p-type
Low doped region connects.
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| CN201410629243.1A CN104465773B (en) | 2014-11-10 | 2014-11-10 | The terminal structure and its manufacture method of metal oxide semiconductor field effect tube |
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| CN201410629243.1A CN104465773B (en) | 2014-11-10 | 2014-11-10 | The terminal structure and its manufacture method of metal oxide semiconductor field effect tube |
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| CN104465773B true CN104465773B (en) | 2018-01-19 |
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| TWI635611B (en) * | 2017-09-25 | 2018-09-11 | 新唐科技股份有限公司 | High voltage semiconductor device |
| CN109524474B (en) * | 2018-11-08 | 2021-06-25 | 西安电子科技大学 | 4H-SiC metal semiconductor field effect transistor with gate edge drain side part light doping |
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| CN101719509B (en) * | 2009-11-10 | 2011-12-28 | 深圳深爱半导体有限公司 | Vertical double-diffusion metal-oxide-semiconductor field effect transistor |
| CN102760648B (en) * | 2010-08-27 | 2015-01-07 | 杭州士兰集成电路有限公司 | Manufacturing method of voltage division ring of plane high-voltage transistor |
| CN202839619U (en) * | 2012-09-28 | 2013-03-27 | 中国科学院微电子研究所 | High-voltage semiconductor device and terminal thereof |
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