TWI635611B - High voltage semiconductor device - Google Patents

Abstract

A high-voltage semiconductor element includes a substrate, a first well region having a second conductivity type, a second well region having a first conductivity type, a first doped region, a second doped region, a gate structure, and a plurality of isolation structures. . The first well area is located on the base. The second well area is located on the base next to the first well area. The first doped region is located in the first well region. The second doped region is located in the second well region. The gate structure is located on the substrate between the first doped region and the second doped region. The isolation structure is located in the first well area. The isolation structures are staggered into an array. Each isolation structure includes a dielectric pillar and a top doped region under the dielectric pillar. The bottom surface of the first well area is lower than the bottom surface of the isolation structure.

Description

High-voltage semiconductor components

The present invention relates to a semiconductor device, and more particularly, to a high-voltage semiconductor device.

Generally speaking, high-voltage semiconductor components are mainly used in power switching circuits. It has become a trend to intelligentize the power switching circuit to make power management techniques more efficient. In this trend, analog or digital control electronics and power transistors can be integrated on the same chip.

With the advancement of science and technology, electronic components are becoming thinner and thinner. As electronic components continue to shrink in size, it is becoming increasingly difficult to maintain high breakdown voltages for high-voltage semiconductor components. Therefore, how to increase the breakdown voltage of high-voltage semiconductor components under a certain component size or miniaturized component size will become an important issue.

The invention provides a high-voltage semiconductor element, which can effectively increase the breakdown voltage of the high-voltage semiconductor element.

The invention provides a high-voltage semiconductor element, which includes a substrate having a first conductivity type, a first well region having a second conductivity type, a second well region having a first conductivity type, and a first doped region having a second conductivity type. , A second doped region having a second conductivity type, a gate structure, and a plurality of isolation structures. The first well area is located on the base. The second well area is located on the base next to the first well area. The first doped region is located in the first well region. The second doped region is located in the second well region. The gate structure is located on the substrate between the first doped region and the second doped region. The isolation structure is located in the first well area. The isolation structures are staggered into an array. Each isolation structure includes a dielectric pillar and a top doped region having a first conductivity type under the dielectric pillar. The bottom surface of the first well area is lower than the bottom surface of the isolation structure.

In an embodiment of the present invention, the isolation structures are arranged in a plurality of rows of the isolation structures, and the spacing between the rows of the isolation structures is the same.

In an embodiment of the present invention, the top doped regions of the isolation structure are separated from each other.

In an embodiment of the present invention, the top doped regions of the isolation structure are connected to each other to form a doped pattern, which extends from a direction adjacent to the gate structure toward the first doped region.

In an embodiment of the present invention, the doping patterns have a uniform doping depth.

In an embodiment of the present invention, the widths of the isolation structures of the isolation structure rows are different.

In an embodiment of the present invention, a width of the isolation structure of the isolation structure row decreases gradually from a direction adjacent to the gate structure toward the first doped region.

In an embodiment of the present invention, a distance between a bottom surface of the first well region and a bottom surface of the isolation structure is 0.2 μm to 3 μm.

In an embodiment of the present invention, the high-voltage semiconductor element further includes a plurality of buried layers having the first conductivity type, which are respectively located between the isolation structure and the substrate.

In an embodiment of the invention, the high-voltage semiconductor device further includes a barrier layer disposed on the isolation structure.

Based on the above, the present invention increases the distance of the current path between the first doped region and the second doped region by forming a plurality of isolation structures in the first well region, thereby increasing the breakdown voltage of the high-voltage semiconductor element. In addition, the isolation structure of the present invention includes a dielectric pillar and a top doped region under the dielectric pillar. The top doped region has a function of reducing a surface area (reduced surface field, RESURF) to further increase the breakdown voltage of the high-voltage semiconductor element. In addition, the present invention arranges the barrier layer on the isolation structure to reduce the surface current, thereby increasing the breakdown voltage of the high-voltage semiconductor element.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

The invention is explained more fully with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, which will not be repeated in the following paragraphs.

In the following embodiments, when the first conductivity type is N-type and the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type. The P-type doping is, for example, boron; the N-type doping is, for example, phosphorus or arsenic. In this embodiment, the first conductivity type is a P-type and the second conductivity type is an N-type for illustration, but the present invention is not limited thereto.

FIG. 1 is a schematic top view of a high-voltage semiconductor device according to a first embodiment of the present invention. 2A is a schematic cross-sectional view of a high-voltage semiconductor device according to a second embodiment of the present invention. Here, FIG. 2A can be regarded as a schematic cross-sectional view of a high-voltage semiconductor device in FIG. 1.

1 and 2A, this embodiment provides a high-voltage semiconductor device including a substrate 100 having a first conductivity type, a first well region 102 having a second conductivity type, and a second well region 104 having a first conductivity type. , A first lightly doped region 105 having a second conductivity type, a first doped region 106, a second lightly doped region 107 with a second conductivity type, a second doped region 108, a gate structure 110, and a plurality of Isolation structure 120.

The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The substrate 100 may have a P-type doping or an N-type doping. The P-type doping may be a group IIIA ion, such as a boron ion. The N-type doping may be a group VA ion such as arsenic ion or phosphorus ion. In this embodiment, the substrate 100 is a P-type silicon substrate. In another embodiment, the substrate 100 may also include a semiconductor substrate and an epitaxial layer (not shown) thereon. The semiconductor substrate may be a P-type substrate, and the epitaxial layer may be an N-type epitaxial layer. Layer (N-epi).

As shown in FIG. 2A, a first well region 102 (eg, an N-type well region) is located on the substrate 100 such that the first lightly doped region 105, the first doped region 106, and the isolation structure 120 are located in the first well region 102. In detail, the first lightly doped region 105 is located in the first well region 102. The first doped region 106 is located in the first lightly doped region 105, that is, the first lightly doped region 105 surrounds the first doped region 106. In an embodiment, the dopant implanted in the first well region 102 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 8´10 ¹⁴ / cm ³ to 1´10 ¹⁸ / cm ³ . The dopant implanted in the first lightly doped region 105 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 5´10 ¹⁶ / cm ³ to 5´10 ¹⁸ / cm ³ . The dopant implanted in the first doped region 106 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 1´10 ¹⁹ / cm ³ to 5´10 ²⁰ / cm ³ .

As shown in view 1 above, the isolation structure 120 is located in the first well region 102. The isolation structures 120 are staggered into an array. Specifically, the isolation structure 120 is arranged into a plurality of isolation structure columns C1-Cn, where n is an integer greater than 1. The isolation structure rows C1-Cn are alternately arranged along the first direction X, and extend along the second direction Y. The first direction X refers to an extending direction from the first doped region 106 toward the second doped region 108; and the second direction Y is perpendicular to the first direction X. In one embodiment, the isolation structures 120 may be separated island structures that are staggered with each other. For example, the isolation structures 120 in the isolation structure rows C1 and C3 of the odd rows and the isolation structures 120 in the isolation structure rows C2 and C4 of the even rows are staggered with each other, which can increase the first doped region 106 and the second doped region. The distance between the miscellaneous regions 108 between the laterally extending current paths 118. That is to say, the current path 118 of this embodiment travels around the isolation structure 120 in a circuitous manner. Compared to the linear distance between the first doped region 106 and the second doped region 108, the current path 118 of this embodiment With a longer path distance, it can increase the breakdown voltage of high-voltage semiconductor components. In addition, the pitch P between the isolation structure rows C1-Cn is uniform. In one embodiment, the pitch P may be between 0.1 μm and 4 μm.

As can be seen from the cross-sectional view of FIG. 2A, each of the isolation structures 120 includes a dielectric pillar 122 and a top doped region 124 having a first conductivity type under the dielectric pillar 122. In an embodiment, the dielectric pillar 122 may be a shallow trench isolation structure (STI), and a material thereof includes silicon oxide. The dopant implanted in the top doped region 124 may be, for example, boron, and the doping concentration may be, for example, 1´10 ¹⁵ / cm ³ to 1´10 ¹⁸ / cm ³ . The top doped regions 124 of the isolation structure 120 are separated from each other by a distance P. As shown in FIG. 2A, the bottom surface of the first well region 102 is lower than the bottom surface of the isolation structure 120 (or the top doped region 124). In one embodiment, the distance D1 between the bottom surface of the first well region 102 and the bottom surface of the isolation structure 120 (or the top doped region 124) may be greater than 0.2 micrometers (μm). In an alternative embodiment, the distance D1 between the bottom surface of the first well region 102 and the bottom surface of the isolation structure 120 (or the top doped region 124) may be between 0.2 μm and 3 μm. The top doped region 124 has the effect of reducing the surface electric field (RESURF), thereby increasing the breakdown voltage of the high-voltage semiconductor device of this embodiment. In some embodiments, the number of the isolation structures 120 can be adjusted according to requirements and component sizes.

The second well region 104 (such as a P-type well region) is located on the substrate 100 beside the first well region 102 such that the second lightly doped region 107 and the second doped region 108 are located therein. In detail, as shown in FIG. 2A, the second lightly doped region 107 is located in the second well region 104. The second doped region 108 is located in the second lightly doped region 107, that is, the second lightly doped region 107 surrounds the second doped region 108. In an embodiment, the dopant implanted in the second well region 104 may be, for example, boron, and the doping concentration may be, for example, 8´10 ¹⁴ / cm ³ to 1´10 ¹⁸ / cm ³ . The dopant implanted in the second lightly doped region 107 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 5´10 ¹⁶ / cm ³ to 5´10 ¹⁸ / cm ³ . The dopant implanted in the second doped region 108 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 1´10 ¹⁹ / cm ³ to 5´10 ²⁰ / cm ³ .

The gate structure 110 is located on the substrate 100 between the first doped region 106 and the second doped region 108. In detail, the gate structure 110 includes a gate dielectric layer 112 and a gate electrode 114 on the gate dielectric layer 112. In one embodiment, the material of the gate dielectric layer 112 includes silicon oxide. The material of the gate electrode 114 includes a conductive material, and may be, for example, a metal, polycrystalline silicon, a silicided metal, or a combination thereof. The gate structure 110 further includes a spacer 116 to cover sidewalls of the gate dielectric layer 112 and the gate electrode 114. The material of the spacer 116 may include silicon oxide, silicon nitride, or a combination thereof. The gate structure 110 extends along the second direction Y. In one embodiment, the gate structure 110 is located on the substrate 100 between the first well region 102 and the second well region 104, so that the isolation structure 120 is located between the gate structure 110 and the first doped region 106.

As shown in FIG. 1, the high-voltage semiconductor device of this embodiment further includes a plurality of drain contact windows 126, a plurality of source contact windows 128, and a plurality of gate contact windows 130. The drain contact windows 126 are respectively disposed on the first doped region 106 and are electrically connected to the first doped region 106. In other words, in the present embodiment, a portion of the first doped region 106 in contact with the drain contact window 126 can be regarded as a drain region. The source contact windows 128 are respectively disposed on the second doped region 108 and are electrically connected to the second doped region 108. In other words, in this embodiment, a part of the second doped region 108 in contact with the source contact window 128 can be regarded as a source region. The gate contact windows 130 are respectively disposed on the gate structure 110 and are electrically connected to the gate structure 110. In an embodiment, the material of the drain contact window 126, the source contact window 128, and the gate contact window 130 includes a conductive material, and may be, for example, metal, polycrystalline silicon, silicided metal, or a combination thereof. In some embodiments, the number and position of the drain contact window 126, the source contact window 128, and the gate contact window 130 can be adjusted as required.

2B is a schematic cross-sectional view of a high-voltage semiconductor device according to a third embodiment of the present invention. Here, FIG. 2B can be regarded as a schematic cross-sectional view of another high-voltage semiconductor device of FIG. 1.

Please refer to FIG. 2B. The high-voltage semiconductor device in FIG. 2B is similar to the high-voltage semiconductor device in FIG. 2A. The difference between the two is that the isolation structure 220 of the high-voltage semiconductor device in FIG. 2B includes a dielectric pillar 222 and a top doped region (not shown) with a first conductivity type under the dielectric pillar 222. The top doped regions under each dielectric pillar 222 are connected to each other to form a strip-shaped doped pattern 224. The doped pattern 224 extends from the adjacent gate structure 110 toward the first doped region 106. In one embodiment, the doping pattern 224 has a uniform doping depth. That is, the doping depth of the doped pattern 224 near the gate structure 110 is substantially the same as the doping depth near the first doped region 106. In some embodiments, the method for forming the isolation structure 220 includes forming a mask pattern (not shown) on the first well region 102 (or the substrate 100). Using the mask pattern as an etching mask, a plurality of trenches (not shown) are formed in the first well region 102 (or the substrate 100). In one embodiment, the spacing between the trenches is substantially the same. Then, using the mask pattern as an ion implantation mask, an ion implantation process is performed, and a dopant is implanted in the first well region 102 below the bottom surface of the trench to be in the first well region 102. A plurality of top doped regions are formed (not shown). After tempering. During tempering, two adjacent top doped regions will spread uniformly and be connected to each other to form a stripe-shaped doped pattern 224. A dielectric material is then filled into the trenches to form a dielectric pillar 222 on the doped pattern 224.

In one embodiment, the distance D2 between the bottom surface of the first well region 102 and the bottom surface of the isolation structure 220 (or the doped pattern 224) may be greater than 0.2 micrometers (μm). In an alternative embodiment, the distance D2 between the bottom surface of the first well region 102 and the bottom surface of the isolation structure 220 (or the doped pattern 224) may be between 0.2 μm and 3 μm.

3 is a schematic top view of a high-voltage semiconductor device according to a fourth embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a high-voltage semiconductor device according to a fifth embodiment of the present invention. Here, FIG. 4 can be regarded as a schematic cross-sectional view of a high-voltage semiconductor device in FIG. 3.

Please refer to FIG. 3. The high-voltage semiconductor device in FIG. 3 is similar to the high-voltage semiconductor device in FIG. 1. The above two are different in that the pitches P1-P4 between the isolation structure rows C1'-Cn 'of the high-voltage semiconductor element of Fig. 3 are different. In detail, the interval P1-P4 between the isolation structure rows C1'-Cn 'gradually increases from the neighboring gate structure 110 toward the first doped region 106. That is, the interval P1 is smaller than the interval P2; the interval P2 is smaller than the interval P3; the interval P3 is smaller than the interval P4. Therefore, as shown in FIG. 4, a part of the top doped regions 324 a and 324 b in the isolation structure 320 overlap and are connected to each other; and another part of the top doped regions 324 c and 324 d in the isolation structure 320 are separated from each other. In an embodiment, the distance D3 between the bottom surface of the first well region 102 and the bottom surface of the isolation structure 320 (or the top doped region 324) may be greater than 0.2 micrometers (μm). In an alternative embodiment, the distance D3 between the bottom surface of the first well region 102 and the bottom surface of the isolation structure 320 (or the top doped region 324) may be between 0.2 μm and 3 μm.

FIG. 5 is a schematic cross-sectional view of a high-voltage semiconductor device according to a sixth embodiment of the present invention.

Please refer to FIG. 5. The high-voltage semiconductor device in FIG. 5 is similar to the high-voltage semiconductor device in FIG. 2A. The difference between the two is that the high-voltage semiconductor device of FIG. 5 further includes a plurality of buried layers 510 (eg, PBL) having a first conductivity type, which are respectively located between the isolation structure 520 and the substrate 100. As shown in FIG. 5, the buried layer 510 may be a block-like region separated from each other, which is between the first well region 102 and the substrate 100. That is, the bottom surface of the buried layer 510 may be lower than the bottom surface of the first well region 102. However, the present invention is not limited thereto. In other embodiments, the bottom surface of the buried layer 510 may be equal to or higher than the bottom surface of the first well region 102. In an alternative embodiment, the buried layer 510 may also have a strip shape, which extends from the adjacent gate structure 110 toward the first doped region 106. In an embodiment, the dopant implanted in the buried layer 510 may be, for example, boron, and the doping concentration may be, for example, 5´10 ¹⁷ / cm ³ to 5´10 ¹⁹ cm ³ .

FIG. 6 is a schematic cross-sectional view of a high-voltage semiconductor device according to a seventh embodiment of the present invention.

Please refer to FIG. 6. The high-voltage semiconductor device in FIG. 6 is similar to the high-voltage semiconductor device in FIG. 2A. The above two are different in that the bottom widths BW1-BWn of the isolation structures 620a-620e of the isolation structure rows C1-Cn of the high-voltage semiconductor element of FIG. 6 are different, where n is an integer greater than 1. Specifically, the bottom widths BW1-BWn of the isolation structures 620a-620e of the isolation structure rows C1-Cn gradually decrease from the adjacent gate structure 110 toward the first doped region 106. In detail, the isolation structure row C1 has a plurality of isolation structures 620a including a dielectric pillar 622a and a top doped region 624a under the dielectric pillar 622a. Similarly, the isolation structure rows C2-Cn also have a plurality of isolation structures 620b-620e, respectively, which include dielectric pillars 622b-622e and top doped regions 624b-624e below the dielectric pillars 622b-622e. The bottom width BW1 of the dielectric pillar 622a is larger than the bottom width BW2 of the dielectric pillar 622b; the bottom width BW2 of the dielectric pillar 622b is larger than the bottom width BW3 of the dielectric pillar 622c; the bottom width BW3 of the dielectric pillar 622c is greater than the bottom width BW4 of the dielectric pillar 622d; the dielectric pillar The bottom width BW4 of 622d is larger than the bottom width BWn of the dielectric pillar 622e. Since the bottom widths BW1-BWn of the dielectric pillars 622a-622e decrease gradually from the adjacent gate structure 110 toward the first doped region 106, the range (or width) of the top doped regions 624a-624e is also from the adjacent gate structure 110 gradually decreases toward the first doped region 106. In addition, the dielectric pillars 622a-622e are separated from each other by a gap S. Therefore, the top doped regions 624a-624e below the dielectric pillars 622a-622e are separated from each other. In this embodiment, the gap S is the same, which may be between 0.1 μm and 4 μm.

FIG. 7 is a schematic top view of a high-voltage semiconductor device according to an eighth embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of FIG. 7.

Please refer to FIGS. 7 and 8. The high-voltage semiconductor device in FIG. 7 is similar to the high-voltage semiconductor device in FIG. 1. The difference between the two is that the high-voltage semiconductor device of FIG. 7 further includes a barrier layer 740 disposed on the isolation structure 120. Specifically, as shown in FIG. 8, the blocking layer 740 is disposed on the isolation structure 120 and the first lightly doped region 105 between the first doped region 106 and the gate structure 110. The blocking layer 740 can prevent subsequent formation of low-resistance materials (such as metal silicide) on the isolation structure 120 to reduce the surface current and thereby increase the breakdown voltage of the high-voltage semiconductor device. In one embodiment, the material of the blocking layer 740 includes an oxide, such as silicon oxide. The method for forming the barrier layer 740 includes forming a barrier material (not shown) on the substrate 100 by blanket using a suitable deposition method such as chemical vapor deposition (CVD) before forming a low-resistance material (not shown). . After that, a portion of the blocking material (that is, a region where a low-resistance material needs to be formed, such as a source / drain region) is removed to form a blocking layer 740 on the isolation structure 120.

It should be noted that although the barrier layer 740 is only shown in the high-voltage semiconductor device of FIGS. 7 and 8, the invention is not limited thereto. In other embodiments, the high-voltage semiconductor element as shown in FIG. 3-6 may also have a barrier layer, which is configured on the corresponding isolation structure to reduce the surface current and thereby increase the breakdown voltage of the high-voltage semiconductor element.

In summary, the present invention increases the distance of the current path between the first doped region and the second doped region by forming a plurality of isolation structures in the first well region, thereby increasing the breakdown voltage of the high-voltage semiconductor element. . In addition, the isolation structure of the present invention includes a dielectric pillar and a top doped region under the dielectric pillar. The top doped region has the effect of reducing the surface electric field to further increase the breakdown voltage of the high-voltage semiconductor element. In addition, the present invention arranges the barrier layer on the isolation structure to reduce the surface current, thereby increasing the breakdown voltage of the high-voltage semiconductor element.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧ substrate
102‧‧‧The first well area
104‧‧‧Second Well District
105‧‧‧First lightly doped region
106‧‧‧ first doped region
107‧‧‧ second lightly doped region
108‧‧‧ second doped region
110‧‧‧Gate structure
112‧‧‧Gate dielectric layer
114‧‧‧Gate electrode
116‧‧‧Gap Wall
118‧‧‧Current Path
120, 220, 320, 520, 620a, 620b, 620c, 620d, 620e‧‧‧Isolation structure
122, 222, 322, 522, 622a, 622b, 622c, 622d, 622e‧‧‧
124, 324, 324a, 324b, 324c, 324d, 524, 624a, 624b, 624c, 624d, 624e
126‧‧‧Drain contact window
128‧‧‧Source contact window
130‧‧‧Gate contact window
224, 424‧‧‧‧doped pattern
510‧‧‧ buried layer
740‧‧‧ barrier
BW1-BWn‧‧‧Bottom width
C1-Cn, C1'-Cn'‧‧‧Isolation Structure Row
D1-D4‧‧‧ distance
P, P1-P4 ‧‧‧ pitch
S‧‧‧ Clearance
X‧‧‧ first direction
Y‧‧‧ second direction

FIG. 1 is a schematic top view of a high-voltage semiconductor device according to a first embodiment of the present invention. 2A is a schematic cross-sectional view of a high-voltage semiconductor device according to a second embodiment of the present invention. 2B is a schematic cross-sectional view of a high-voltage semiconductor device according to a third embodiment of the present invention. 3 is a schematic top view of a high-voltage semiconductor device according to a fourth embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a high-voltage semiconductor device according to a fifth embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a high-voltage semiconductor device according to a sixth embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a high-voltage semiconductor device according to a seventh embodiment of the present invention. FIG. 7 is a schematic top view of a high-voltage semiconductor device according to an eighth embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of FIG. 7.

Claims (10)

A high-voltage semiconductor element includes: a substrate having a first conductivity type; a first well region having a second conductivity type on the substrate; the first conductivity type being different from the second conductivity type; A second well region of a first conductivity type is located on the substrate beside the first well region; a first doped region having the second conductivity type is located in the first well region; A second doped region of a second conductivity type is located in the second well region; a gate structure is located on the substrate between the first doped region and the second doped region; and An isolation structure is located in the first well region, and the isolation structure forms a plurality of rows of isolation structures arranged in an array, wherein adjacent rows of the isolation structures run from the first doped region toward the first The directions of the two doped regions are staggered with each other, wherein each of the isolation structures includes a dielectric pillar and a top doped region having the first conductivity type under the dielectric pillar, wherein a bottom surface of the first well region is lower than A bottom surface of the isolation structure. The high-voltage semiconductor device according to item 1 of the scope of patent application, wherein the spacing between the rows of the isolation structures is uniform. The high-voltage semiconductor element according to item 2 of the patent application scope, wherein the top doped regions of the isolation structure are separated from each other. The high-voltage semiconductor device according to item 2 of the scope of patent application, wherein the top doped regions of the isolation structure are connected to each other to form a doping pattern, which is adjacent to the gate structure toward the first doping The direction of the zone extends. The high-voltage semiconductor device according to item 4 of the patent application scope, wherein the doping pattern has a uniform doping depth. The high-voltage semiconductor element according to item 2 of the scope of patent application, wherein the widths of the isolation structures of the isolation structure rows are different. The high-voltage semiconductor device according to item 2 of the scope of patent application, wherein a width of the isolation structure of the isolation structure row decreases gradually from a direction adjacent to the gate structure toward the first doped region. The high-voltage semiconductor device according to item 1 of the scope of patent application, wherein a distance between the isolation structure rows gradually increases from an extension direction adjacent to the gate structure toward the first doped region. The high-voltage semiconductor device according to item 1 of the scope of patent application, further comprising a plurality of buried layers having the first conductivity type, which are respectively located between the isolation structure and the substrate. The high-voltage semiconductor device according to item 1 of the patent application scope further includes a barrier layer disposed on the isolation structure.