CN105489581B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN105489581B CN105489581B CN201510996499.0A CN201510996499A CN105489581B CN 105489581 B CN105489581 B CN 105489581B CN 201510996499 A CN201510996499 A CN 201510996499A CN 105489581 B CN105489581 B CN 105489581B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract
A kind of semiconductor structure and preparation method thereof, the pseudo- metal interconnecting layer being electrically insulated with it is formed simultaneously in formation multiple layer metal interconnection layer, the puppet metal interconnecting layer includes at least one layer of pseudo- top layer metal pattern, the puppet top layer metal pattern and the top-level metallic pattern same layer in metal interconnecting layer；When forming conductive plunger on top-level metallic pattern, net metal support construction is formed on pseudo- top layer metal pattern, dielectric material is filled in the mesh of the net metal support construction；Weld pad is formed on conductive plunger and net metal support construction, which includes the central area for the fringe region and exposure being covered by a passivation layer, and side edges region is electrically connected with metal interconnecting layer, and weld pad central area is supported by net metal support construction.Good, the easily rupturable dielectric material of net metal support construction support effect is limited in single mesh, will not be ruptured because of the dielectric material in single mesh, the crackle is caused to amplify in full wafer dielectric material, improves chip reliability.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor structure and preparation method thereof.
Background technology
In technical field of manufacturing semiconductors, integrated circuit (IC) encapsulation is very important a ring, is chip and circuit
Electrical interconnection, mechanical support, machinery and environmental protection and passage of heat are provided between plate.Specifically, IC package is exactly to utilize
Routing technique, the weld pad (Pad) on chip draw bonding wire, and bonding wire is guided on the pin of package casing, these pins are again
It is connected by the conducting wire on printed circuit board with other devices, so as to fulfill the connection of inside chip and external circuit.
In recent years, with the rapid development of semiconductor process technique, the function of semiconductor chip is become stronger day by day, number of pins
Amount also increases therewith, and in order to meet the needs of market, wafer-level package (CSP) occurs in chip encapsulation technology, is with convex block
(Bumping) or tin ball (Ball Mount) is directly connected with circuit board, due to not needing to the processing procedures such as routing, thus is greatly decreased
Process costs.
No matter however, in bonding process or during convex block or tin ball be connected directly, in the prior art on weld pad
Pressure welding strength (Bonding Force) is born by the interlayer dielectric layer (IMD) under it, this can cause interlayer dielectric layer to rupture
(Crack), the reliability (Reliability) of chip is influenced under serious conditions.
Invention content
The present invention solves the problems, such as be how to provide a kind of semiconductor structure and preparation method thereof, avoid the interlayer under weld pad
Dielectric layer ruptures during pressure welding, so as to improve chip reliability.
To solve the above problems, an aspect of of the present present invention provides a kind of semiconductor structure, including：
Semiconductor substrate, the surface of the Semiconductor substrate are formed with semiconductor devices, are formed on the semiconductor devices
If there is dried layer metal interconnecting layer；
Weld pad, it is described several for passing through if being connect with the Portions of top layer metal pattern in the dried layer metal interconnecting layer
Layer metal interconnecting layer is electrically connected with the semiconductor devices；
Wherein, the semiconductor structure further includes：
If the pseudo- metal interconnecting layer with dried layer metal interconnecting layer electrical isolation, the puppet metal interconnecting layer includes at least puppet
Top-level metallic pattern, if the puppet top layer metal pattern is located at together with the top-level metallic pattern in the dried layer metal interconnecting layer
Layer；The weld pad includes the fringe region being covered by a passivation layer and the central area exposed by the passivation layer, the weld pad
Fringe region be electrically connected with the top-level metallic pattern in the metal interconnecting layer, the central area of the weld pad with its under puppet
Between top-level metallic pattern there is net metal support construction, dielectric material is filled in the mesh of the net metal support construction
Material.
Optionally, the pseudo- metal interconnecting layer is equal with the number of plies of the metal interconnecting layer, the puppet metal interconnecting layer
It is net metal support construction or multiple by dielectric material insulation between each layer puppet metal pattern and pseudo- metal pattern under it
Conductive plunger.
Optionally, the number of plies of the pseudo- metal interconnecting layer is less than the number of plies of the metal interconnecting layer, the puppet metal interconnection
Layer is lower for part metals interconnection layer.
Optionally, it is netted gold between pseudo- each layer puppet metal pattern of metal interconnecting layer and the pseudo- metal pattern under it
Belong to support construction or multiple conductive plungers to be insulated by dielectric material.
Optionally, each width of mesh of the net metal support construction is equal, shape is identical.
Optionally, each mesh of the net metal support construction is rectangular, cross or circle.
Another aspect of the present invention provides a kind of production method of semiconductor structure, including：
Semiconductor substrate is provided, the surface of the Semiconductor substrate is formed with semiconductor devices, in the semiconductor devices
If upper formation dried layer metal interconnecting layer, if the top layer of the dried layer metal interconnecting layer is top-level metallic pattern；If forming dried layer
During metal interconnecting layer, if being formed simultaneously the pseudo- metal interconnecting layer being electrically insulated with the dried layer metal interconnecting layer, the puppet metal is mutual
Even layer includes at least pseudo- top layer metal pattern, the puppet top layer metal pattern and the top-level metallic pattern in the metal interconnecting layer
Positioned at same layer；
In top-level metallic pattern with forming dielectric layer on pseudo- top layer metal pattern, dielectric layer shape described in photoetching, dry etching
Through-hole into the exposure top-level metallic pattern and multiple dielectric posts positioned at the pseudo- top layer metal pattern surface；Institute
It states in through-hole and inserts metal between each dielectric post, planarize the metal up to the upper surface flush with the dielectric layer；
The metal inserted in the through-hole forms conductive plunger, and the metal inserted between each dielectric post forms net metal support knot
Structure；
Weld pad is formed in the conductive plunger and net metal support construction upper surface, exposure is formed on the weld pad
The passivation layer of weld pad central area is net metal support construction under the weld pad central area.
Optionally, when forming every layer of metal pattern, every layer of pseudo- metal figure being formed simultaneously in the pseudo- metal interconnecting layer
Case, described every layer pseudo- metal pattern are electrically insulated with every layer of metal pattern, and the conductive plunger between formation double layer of metal pattern is simultaneously
Form the net metal support construction between two layers of pseudo- metal pattern or multiple conductive plungers to be insulated by dielectric material.
Optionally, in the multiple layer metal pattern under forming top-level metallic pattern, respective layer puppet metal pattern is formed simultaneously,
Described every layer pseudo- metal pattern is electrically insulated with every layer of metal pattern.
Optionally, the conductive plunger in the multiple layer metal pattern under forming top-level metallic pattern between double layer of metal pattern
When, the net metal support construction or multiple conductions to be insulated by dielectric material that are formed simultaneously between corresponding two layers pseudo- metal pattern
Plug.
Compared with prior art, technical scheme of the present invention has the following advantages：1) it is same in formation multiple layer metal interconnection layer
When formed with the metal interconnecting layer electrical isolation pseudo- metal interconnecting layer, the puppet metal interconnecting layer include at least one layer puppet top-level metallic
Pattern, the puppet top layer metal pattern are located at same layer with the top-level metallic pattern in metal interconnecting layer；On top-level metallic pattern
When forming conductive plunger, net metal support construction, the net of the net metal support construction are formed on pseudo- top layer metal pattern
Intraocular tamponade has dielectric material；Weld pad is formed on conductive plunger and net metal support construction, which includes follow-up
The fringe region for the passivation layer covering that technique is formed and the central area of passivation layer exposure, side edges region passes through conduction
Plug is connect with top-level metallic pattern, and so as to be electrically connected with metal interconnecting layer, weld pad central area is by net metal support construction
Support.On the one hand net metal support construction is structure as a whole, thus support effect is good, and two aspects are due to being formed in pseudo- top layer gold
On metal patterns, because without being electrically connected with other devices；The easily rupturable dielectric material of three aspects is limited in single mesh, will not
Because the dielectric material rupture in single mesh, causes the crackle to amplify in full wafer dielectric material, improves chip reliability.
2) in alternative, a) pseudo- metal interconnecting layer can be equal with the number of plies of metal interconnecting layer, such semiconductor structure
Referred to as non-circuit under pad (Non-Circuit Under Pad, Non-CUP), in such cases, each layer of pseudo- metal interconnecting layer
Can be net metal support construction between pseudo- metal pattern and pseudo- metal pattern under it；It is or multiple by dielectric material
The conductive plunger of insulation；B) number of plies of pseudo- metal interconnecting layer can also be less than the number of plies of metal interconnecting layer, under pseudo- metal interconnecting layer
For metal interconnecting layer, such semiconductor structure is known as circuit under pad (Circuit Under Pad, CUP), in such cases,
It can be net metal support construction between each layer puppet metal pattern of pseudo- metal interconnecting layer and the pseudo- metal pattern under it, also may be used
Think multiple conductive plungers to be insulated by dielectric material.
3) in alternative, each mesh of net metal support construction can be rectangular, cross or circle, be easy to make
Make.
Description of the drawings
Fig. 1 to Fig. 8 is the structure diagram of the semiconductor structure in each production phase of one embodiment of the invention；
Fig. 9 to Figure 10 is the structure diagram of the semiconductor structure in two production phases of another embodiment of the present invention；
Figure 11 to Figure 12 is the structure diagram of the semiconductor structure in two production phases of yet another embodiment of the invention.
Specific embodiment
As described in the background art, the interlayer dielectric layer that weld pad of the prior art is easily caused during pressure welding under it is broken
It splits, the reliability of chip can be influenced under serious conditions.Inventor by analysis, it is found that its Producing reason is：The support of weld pad
Using conductive plunger, conductive plunger is formed in interlayer dielectric layer.Interlayer dielectric layer is after rupture, due to joining together, because
And rupture and can be amplified, so as to which the interlayer dielectric layer insulation performance is deteriorated, influence reliability.
Based on above-mentioned analysis, the present invention is using net metal support construction support pad, the net metal support construction shape
On the pseudo- metal interconnecting layer of Cheng Yu other devices electrical isolation, and dielectric material is limited in each of net metal support construction
In mesh, above-mentioned integrity problem is avoided.In addition, above-mentioned net metal support construction is in weld pad central area support pad, weldering
Conducting for pad is electrically connected realization by metal interconnection structure with its fringe region.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 to Fig. 8 is the structure diagram of the semiconductor structure in each production phase of one embodiment of the invention.Below in conjunction with
Semiconductor structure of an embodiment and preparation method thereof is discussed in detail in Fig. 1 to Fig. 8.
First, with reference to shown in Fig. 1, Semiconductor substrate 10 is provided, the surface of Semiconductor substrate 10 is formed with semiconductor devices
(not shown), if forming dried layer metal interconnecting layer 11 on the semiconductor device, if the top layer of dried layer metal interconnecting layer 11 is top layer
Metal pattern 11a；If when forming dried layer metal interconnecting layer 11, if being formed simultaneously what is be electrically insulated with being somebody's turn to do dried layer metal interconnecting layer 11
Pseudo- metal interconnecting layer 12, pseudo- metal interconnecting layer 12 include pseudo- top layer metal pattern 12a, and pseudo- top layer metal pattern 12a and metal are mutual
Even the top-level metallic pattern 11a in layer 11 is located at same layer.
Specifically, the material of semiconductor device substrate 10 can be silicon, germanium, silicon-on-insulator (SOI) etc..Semiconductor devices example
Such as it is MOS transistor.With reference to shown in Fig. 1, the metal interconnecting layer 11 in the present embodiment is 7 layers, can also in other embodiments
For other number numbers of plies；Pseudo- metal interconnecting layer 12 only includes pseudo- top layer metal pattern 12a.Top in metal interconnecting layer 11 is formed
Layer metal pattern 11a is formed simultaneously pseudo- top layer metal pattern 12a.The material of top-level metallic pattern 11a, pseudo- top layer metal pattern 12a
Matter a) can be copper, be formed using groove mode is filled out；B) it may be aluminium, formed using photoetching, dry etching method.
Metal interconnecting layer 11 includes each layer metal pattern (not indicating) and the conductive plunger on metal pattern (is not marked
Show).Interlayer dielectric layer (not indicating) is filled between each metal pattern, each conductive plunger.
It is lower mutual for part metals as can be seen that pseudo- metal interconnecting layer 12 only includes pseudo- top layer metal pattern 12a in Fig. 1
Even layer 11, such semiconductor structure are known as circuit under pad (Circuit Under Pad, CUP).
Then, with reference to shown in Fig. 2, in top-level metallic pattern 11a with forming dielectric layer 13 on pseudo- top layer metal pattern 12a,
Photoetching, dry etching dielectric layer 13 form the through-hole 131 of exposed top layer metal pattern 11a and positioned at pseudo- top layer metal patterns
Multiple dielectric posts 132 on 12a surfaces.
The material of dielectric layer 13 is, for example, silica.After this step makes, in one embodiment, pseudo- top-level metallic
For the vertical view of pattern 12a as shown in figure 3,132 shape size of each dielectric post is consistent, cross section is circle.In another embodiment,
The vertical view of pseudo- top layer metal pattern 12a is as shown in figure 4, the cross section of dielectric post 132 is cross.In other embodiments, respectively
The cross section of dielectric post 132 can also be other shapes, and the shape size of for example, rectangular or even each dielectric post 132 can not
Unanimously, each dielectric post 132 is discrete.
Later, with reference to shown in Fig. 5, metal is inserted in through-hole 131 and between each dielectric post 132, planarizes the metal
Until the upper surface flush with dielectric layer 13；The metal inserted in through-hole 131 forms conductive plunger 141, between each dielectric post 132
The metal inserted forms net metal support construction 142.Inserted between dielectric post 132 shown in Fig. 3 after metal formed it is netted
The net metal support knot that metal support structure 142 as shown in fig. 6, inserted between dielectric post shown in Fig. 4 132 is formed after metal
Structure 142 is as shown in Figure 7.As can be seen that net metal support construction 142 is connected, mesh is dielectric post 132.
It, can be by controlling 132 size of dielectric post so that in net metal support construction 142 in specific implementation process
Metal part occupied area at least more than all dielectric posts 132 cross-sectional area summation.
Later, with reference to shown in Fig. 8, weld pad is formed in conductive plunger 141 and 142 upper surface of net metal support construction
15.The material of the weld pad 15 can be aluminium, specially deposit one layer of aluminium layer, formed afterwards using photoetching, dry etching.
Then, referring now still to shown in Fig. 8, the passivation layer 16 of exposure weld pad central area 151 is formed on weld pad 15, in weld pad
Heart district domain 151 times is net metal support construction 142.The electrical connection of weld pad 15 passes through the conduction under fringe region 152 therein
Plug 141 is realized.
Based on above-mentioned production method, a kind of semiconductor structure is formd, with reference to shown in Fig. 8, which includes：
Semiconductor substrate 10, the surface of Semiconductor substrate 10 are formed with semiconductor devices (not shown), the semiconductor devices
If dried layer metal interconnecting layer 11 is formed on；
If the pseudo- metal interconnecting layer 12 being electrically insulated with dried layer metal interconnecting layer 11, pseudo- metal interconnecting layer 12 includes at least false roof
Layer metal pattern 12a, if pseudo- top layer metal pattern 12a is located at together with the top-level metallic pattern 11a in dried layer metal interconnecting layer 11
Layer；
Weld pad 15, including being passivated the fringe region 152 of the covering of layer 16 and being passivated the central area of the exposure of layer 16
151, the fringe region 152 of weld pad is electrically connected with the top-level metallic pattern 11a in metal interconnecting layer 11, if for passing through dried layer gold
Belong to interconnection layer 11 to be electrically connected with semiconductor devices；Have between weld pad central area 151 and pseudo- top layer metal pattern 12a under it
Net metal support construction 142, the mesh of net metal support construction 142 is interior to be filled with dielectric material.
In above-mentioned semiconductor structure, net metal support construction 142 is advantageous in that：1) it is structure as a whole, thus supports
Effect is good；2) due to being formed on pseudo- top layer metal pattern 12a, because without being electrically connected with other devices；3) easily rupturable dielectric
Material is limited in single mesh, will not be ruptured because of the dielectric material in single mesh, lead to the crackle in full wafer dielectric
Amplify in material, improve chip reliability.
Fig. 9 to Figure 10 is the structure diagram of the semiconductor structure in two production phases of another embodiment of the present invention.With reference to
Shown in Fig. 9 and Fig. 1, shown in Figure 10 and Fig. 8, it can be seen that the pseudo- metal interconnecting layer 12 in the present embodiment is in addition to including pseudo- top layer
Metal pattern 12a further includes the layer puppet metal pattern 12b second from the bottom under it, layer puppet metal pattern 12c third from the bottom.It should fall
The number third layer puppet metal pattern 12c and layer metal pattern 11c third from the bottom in metal interconnecting layer 11 is formed in the same process；
Layer metal pattern 11b second from the bottom in layer puppet metal pattern 12b second from the bottom and metal interconnecting layer 11 shape in the same process
Into.Conductive plunger on layer metal pattern 11c third from the bottom is made has made layer puppet metal pattern 12c third from the bottom simultaneously
On net metal support construction 17, the production method of the net metal support construction 17 is referring to figs. 1 to the net in Fig. 8 embodiments
The production method of shape metal support structure 142, the interior mesh of net metal support construction 17 is dielectric post.In other embodiments,
The reticular supporting structure 17 can also replace with the conductive plunger in interlayer dielectric layer, such as the layer metal pattern third from the bottom of same layer
Conductive plunger on 11c.Similarly, the conductive plunger on layer metal pattern 11b second from the bottom is made simultaneously, has made inverse
Net metal support construction 18 on second layer puppet metal pattern 12b, the production method reference of the net metal support construction 18
The production method of net metal support construction 142 in Fig. 1 to Fig. 8 embodiments is in the mesh of net metal support construction 18
Dielectric post.In other embodiments, which can also replace with the conductive plunger in interlayer dielectric layer, such as
Conductive plunger on the layer metal pattern 11b second from the bottom of same layer.
In other embodiments, in addition to three layers, the number of plies of pseudo- metal interconnecting layer 12 can be other numbers.
Figure 11 to Figure 12 is the structure diagram of the semiconductor structure in two production phases of yet another embodiment of the invention.With reference to
Shown in Figure 11 and Fig. 1, shown in Figure 12 and Fig. 8, it can be seen that the number of plies and metal of the pseudo- metal interconnecting layer 12 in the present embodiment are mutual
Even the number of plies of layer 11 is equal, i.e., each layer puppet metal pattern makes in the same process with metal pattern.On each layer metal pattern
In conductive plunger manufacturing process, while the net metal support construction on respective layer puppet metal pattern is made.The net metal
The production method of support construction referring to figs. 1 to the net metal support construction 142 in Fig. 8 embodiments production method, it is each netted
It is dielectric post in the mesh of metal support structure.In other embodiments, which can also replace with interlayer
Conductive plunger in dielectric layer, such as the conductive plunger on same layer metal pattern.
Unlike previous embodiment, in the semiconductor structure in Figure 12, pseudo- metal interconnecting layer 12 is mutual without metal under it
Even layer, although being shown in Figure 12 has conductive plunger between first layer puppet metal pattern and Semiconductor substrate 10, however, this is led
Electric plug does not play electric action.In other words, the semiconductor structure for non-circuit under pad (Non-Circuit Under Pad,
Non-CUP)。
No matter semiconductor structure is circuit under pad, pseudo- metal interconnecting layer has how many layer or is non-circuit under pad, by
It is electrically insulated in pseudo- metal interconnecting layer and other devices, net metal support construction is formed at least on pseudo- top layer metal pattern, it is right
Weld pad center is supported, and one side support effect is good, and on the other hand easily rupturable dielectric material is limited in single mesh,
It will not be ruptured because of the dielectric material in single mesh, the crackle be caused to amplify in full wafer dielectric material, improving chip can
By property.Weld pad conducts the connection remained to by between the side edges region covered under passivation layer and metal interconnecting layer simultaneously
It realizes.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of semiconductor structure, including：
Semiconductor substrate, the surface of the Semiconductor substrate are formed with semiconductor devices, if being formed on the semiconductor devices
Dried layer metal interconnecting layer；
Weld pad, if being connect with the Portions of top layer metal pattern in the dried layer metal interconnecting layer, if for passing through the dried layer gold
Belong to interconnection layer to be electrically connected with the semiconductor devices；
It is characterized in that, the semiconductor structure further includes：
If the pseudo- metal interconnecting layer with dried layer metal interconnecting layer electrical isolation, the puppet metal interconnecting layer includes at least pseudo- top layer
Metal pattern, if the puppet top layer metal pattern is located at same layer with the top-level metallic pattern in the dried layer metal interconnecting layer；Institute
It states weld pad and includes the fringe region being covered by a passivation layer and the central area exposed by the passivation layer, the edge of the weld pad
Region is electrically connected with the top-level metallic pattern in the metal interconnecting layer, the central area of the weld pad and the pseudo- top layer gold under it
Between metal patterns there is net metal support construction, dielectric material is filled in the mesh of the net metal support construction；Its
In, the net metal support construction is structure as a whole.
2. semiconductor structure according to claim 1, which is characterized in that the puppet metal interconnecting layer is interconnected with the metal
The number of plies of layer is equal, is net metal between puppet each layer puppet metal pattern of metal interconnecting layer and the pseudo- metal pattern under it
Support construction or multiple conductive plungers to be insulated by dielectric material.
3. semiconductor structure according to claim 1, which is characterized in that the number of plies of the puppet metal interconnecting layer is less than described
The number of plies of metal interconnecting layer, it is described puppet metal interconnecting layer under be part metals interconnection layer.
4. semiconductor structure according to claim 3, which is characterized in that each layer puppet metal figure of the puppet metal interconnecting layer
It is net metal support construction or multiple conductive plungers to be insulated by dielectric material between case and pseudo- metal pattern under it.
5. semiconductor structure according to claim 1, which is characterized in that each mesh of the net metal support construction
It is equal in magnitude, shape is identical.
6. semiconductor structure according to claim 5, which is characterized in that each mesh of the net metal support construction
For rectangular, cross or circle.
7. a kind of production method of semiconductor structure, which is characterized in that including：
Semiconductor substrate is provided, the surface of the Semiconductor substrate is formed with semiconductor devices, the shape on the semiconductor devices
If into dried layer metal interconnecting layer, if the top layer of the dried layer metal interconnecting layer is top-level metallic pattern；If forming dried layer metal
During interconnection layer, if being formed simultaneously the pseudo- metal interconnecting layer being electrically insulated with the dried layer metal interconnecting layer, the puppet metal interconnecting layer
Including at least pseudo- top layer metal pattern, the puppet top layer metal pattern is located at the top-level metallic pattern in the metal interconnecting layer
Same layer；
In top-level metallic pattern with forming dielectric layer on pseudo- top layer metal pattern, dielectric layer described in photoetching, dry etching is formed cruelly
The through-hole for revealing the top-level metallic pattern and multiple dielectric posts positioned at the pseudo- top layer metal pattern surface；Described logical
Metal is inserted in hole and between each dielectric post, planarizes the metal up to the upper surface flush with the dielectric layer；It is described
The metal inserted in through-hole forms conductive plunger, and the metal inserted between each dielectric post forms net metal support construction；
Wherein, the net metal support construction is structure as a whole；
Weld pad is formed in the conductive plunger and net metal support construction upper surface, exposure weld pad is formed on the weld pad
The passivation layer of central area is net metal support construction under the weld pad central area.
8. production method according to claim 7, which is characterized in that when forming every layer of metal pattern, be formed simultaneously institute
Every layer of pseudo- metal pattern in pseudo- metal interconnecting layer is stated, described every layer pseudo- metal pattern is electrically insulated with every layer of metal pattern, is formed
Conductive plunger between double layer of metal pattern is formed simultaneously the net metal support construction or multiple between two layers of pseudo- metal pattern
The conductive plunger to be insulated by dielectric material.
9. production method according to claim 7, which is characterized in that the multiple layer metal figure in the case where forming top-level metallic pattern
During case, respective layer puppet metal pattern is formed simultaneously, described every layer pseudo- metal pattern is electrically insulated with every layer of metal pattern.
10. production method according to claim 9, which is characterized in that the multiple layer metal in the case where forming top-level metallic pattern
In pattern during conductive plunger between double layer of metal pattern, the net metal branch that is formed simultaneously between corresponding two layers pseudo- metal pattern
Support structure or multiple conductive plungers to be insulated by dielectric material.
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| CN106252313B (en) * | 2016-10-12 | 2018-12-11 | 上海华虹宏力半导体制造有限公司 | A kind of bond pad structure |
| TWI635611B (en) * | 2017-09-25 | 2018-09-11 | 新唐科技股份有限公司 | High voltage semiconductor device |
| CN117080163B (en) * | 2023-10-11 | 2024-02-23 | 芯耀辉科技有限公司 | Chip structure and forming method thereof, chip packaging structure and forming method thereof |
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| TW484196B (en) * | 2001-06-05 | 2002-04-21 | United Microelectronics Corp | Bonding pad structure |
| CN1779969A (en) * | 2004-11-17 | 2006-05-31 | 联华电子股份有限公司 | Integrated circuit structure with welding pad on top of active circuit |
| CN102800665A (en) * | 2011-05-27 | 2012-11-28 | Nxp股份有限公司 | Integrated circuit with sensor and method of manufacturing such an integrated circuit |
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| US8258775B2 (en) * | 2009-04-15 | 2012-09-04 | Via Technologies, Inc. | Method and apparatus for determining phase error between clock signals |
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| CN1314710A (en) * | 2000-03-17 | 2001-09-26 | 国际商业机器公司 | Method and structure of pole interconnection |
| TW484196B (en) * | 2001-06-05 | 2002-04-21 | United Microelectronics Corp | Bonding pad structure |
| CN1779969A (en) * | 2004-11-17 | 2006-05-31 | 联华电子股份有限公司 | Integrated circuit structure with welding pad on top of active circuit |
| CN102800665A (en) * | 2011-05-27 | 2012-11-28 | Nxp股份有限公司 | Integrated circuit with sensor and method of manufacturing such an integrated circuit |
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