CN108573885B

CN108573885B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN108573885B
Application number: CN201710131843.9A
Authority: CN
Inventors: 殷原梓
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-03-07
Filing date: 2017-03-07
Publication date: 2021-03-23
Anticipated expiration: 2037-03-07
Also published as: CN108573885A

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a device wafer, forming bumps for connecting with a packaging substrate on the device wafer, wherein the bumps comprise dense bumps and isolated bumps, and forming protection walls surrounding the isolated bumps around the isolated bumps. According to the manufacturing method of the semiconductor device, the effect of stress caused by deformation of the packaging substrate on the isolated bump is limited by forming the protection wall, so that the problems such as damage of the passivation layer and the like are not easy to occur in the quality test of the semiconductor device packaging chip. The semiconductor device has better reliability and stress resistance due to the existence of the protection wall. The electronic device comprises the semiconductor device and has the advantages.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.

Background

In package interconnections for integrated circuits, the connection of a semiconductor device (e.g., a chip) to a package substrate (e.g., a leadframe) provides circuit connections for distribution of power and signals. Common connection methods for electronic packages include Wire Bonding (WB), TAPE Automated Bonding (TAB) and Flip Chip (FC). Flip chip bump structures are a common packaging technology due to their high semiconductor device mounting density. As shown in fig. 1, in the flip chip bump structure, a bump 101, such as a copper pillar, is formed on a chip 100, and the connection between the chip 100 and a substrate 102 is achieved by connecting the bump to a pad on one surface of the substrate 102, while a solder ball 103 is formed on the other surface of the substrate 102, and the packaged chip can be mounted on a Printed Circuit Board (PCB) through the solder ball 103 to form various electronic products.

After the chip packaging is completed, the chip packaging quality test is carried out to check the bonding performance of the chip and the packaging material. Failure analysis of the rejected product revealed cracking and peeling of the chip passivation layer (e.g., polyimide layer), damage to the second passivation layer, and deformation of the aluminum layer.

Therefore, in order to solve the above technical problems, it is necessary to provide a new semiconductor device and a method for manufacturing the same.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, aiming at the defects of the prior art, and the semiconductor device, the manufacturing method and the electronic device can prevent the problem of chip damage caused by deformation stress in the chip packaging quality test.

One embodiment of the present invention provides a method of manufacturing a semiconductor device, the method including: providing a device wafer, forming bumps for connecting with a packaging substrate on the device wafer, wherein the bumps comprise dense bumps and isolated bumps, and forming protection walls surrounding the isolated bumps around the isolated bumps.

Further, the shape of the protection wall is determined based on the position distribution of the dense bumps and the isolated bumps.

Further, the shape of the protection wall is round, rectangular, square, diamond or hexagonal.

Further, still include: and forming a rewiring layer on the device wafer, wherein the rewiring layer comprises a first rewiring layer used for being connected with the bump and a second rewiring layer used for being connected with the protection wall.

Further, the second redistribution layer is a dummy redistribution layer that is not electrically connected to the metal interconnect layer in the device wafer.

Further, the surface area of the second rewiring layer is larger than the bottom area of the protection wall.

Further, still include: providing a packaging substrate, wherein welding spots corresponding to the bumps are formed on the packaging substrate; and completing the connection of the device wafer and the packaging substrate through the bumps and the welding spots.

Further, still include: and forming a contact point corresponding to the protection wall on the packaging substrate, and connecting the protection wall and the contact point while connecting the bump and the welding spot.

According to the manufacturing method of the semiconductor device, the protection wall is formed around the isolated bump for connecting with the packaging substrate, the protection wall can limit the effect of stress caused by the deformation of the packaging substrate on the isolated bump in the packaging quality test, can support and balance weight, and the protection wall is not easy to collapse, so that the stress resistance of the isolated bump and the device is enhanced, and the problems of cracking and peeling of the passivation layer, damage of the second passivation layer, deformation of the aluminum layer and the like are not easy to occur in the packaging chip quality test of the semiconductor device.

Another embodiment of the present invention provides a semiconductor device including a device wafer on which bumps for connection with a package substrate are formed, the bumps including dense bumps and isolated bumps, and protective walls surrounding the isolated bumps formed around the isolated bumps.

Further, the shape of the protection wall corresponds to the position distribution of the dense bumps and the isolated bumps.

Further, a redistribution layer is formed on the device wafer, and the redistribution layer includes a first redistribution layer connected to the bump and a second redistribution layer connected to the protection wall.

Further, still include: and the packaging substrate is provided with welding spots corresponding to the bumps, and the bumps and the welding spots are connected together to realize the connection of the device wafer and the packaging substrate.

Furthermore, contact points corresponding to the protection walls are formed on the packaging substrate, and the protection walls and the contact points are connected together to realize the connection of the device wafer and the packaging substrate.

According to the semiconductor device, the protection wall is formed, so that the effect of stress caused by deformation of the packaging substrate on the isolated bump can be limited in the packaging quality test, the stress resistance of the isolated bump and the device is enhanced, the problems of cracking and peeling of the passivation layer, damage of the second passivation layer, deformation of the aluminum layer and the like are not easy to occur in the packaging chip quality test of the semiconductor device, and the reliability of the semiconductor device is improved.

Still another embodiment of the present invention provides an electronic apparatus including the above semiconductor device and an electronic component connected to the semiconductor device.

The electronic device according to the present invention has similar advantages because it includes the above-described semiconductor device.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a diagram illustrating a bump package structure of a flip chip in the prior art;

FIG. 2 is a schematic diagram illustrating a shape change of a flip chip bump package structure during a chip package quality test;

FIG. 3 is a schematic diagram illustrating the stress of the bump and the chip in the flip chip bump package during the chip package quality test;

fig. 4A and 4B show SEM photographs of the flip chip bump package structure before and after chip damage in a chip package quality test;

FIG. 5A is a schematic diagram illustrating a bump distribution of a chip in a flip chip bump package structure;

FIG. 5B is a diagram illustrating stress distribution of bumps of a chip in a flip-chip bump package;

fig. 6A shows a graph of scanning acoustic diagnostic results for flip chip bump packages;

FIG. 6B shows a schematic diagram of the result graph shown in FIG. 6A;

FIG. 6C is an enlarged view of the area 600C in FIG. 6B;

fig. 7A is a schematic top view of a device wafer with bumps and protection walls formed according to an embodiment of the invention;

fig. 7B is a schematic cross-sectional view of a device wafer with bumps and protective walls formed according to an embodiment of the invention;

fig. 8A to 8C show device cross-sectional views corresponding to steps of a method of packaging a semiconductor device according to an embodiment of the present invention;

fig. 9 shows a flowchart of steps of a method of packaging a semiconductor device according to an embodiment of the invention;

fig. 10 shows a schematic view of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

As described above, when a chip package quality test is performed on a product packaged by using the flip chip bump structure, it is found that there are problems of cracking and peeling of a chip passivation layer (e.g., a polyimide layer), damage of a second passivation layer, and deformation of an aluminum layer, and it is considered that this is because a packaged chip undergoes many times of thermal cycles while the chip package quality test is performed, and the packaged chip shrinks due to the non-uniform thermal expansion coefficients of the chip 100 and the substrate 102. Since the packaging material, such as the material of the substrate 102 is usually plastic, and the chip 101 is a semiconductor material such as silicon, the deformation of the plastic substrate 102 is much larger than that of the chip 100 during the heating and cooling cycles, and the deformation difference between the chip 100 and the substrate 102 causes a large additional stress, which acts on the bumps first and then transfers to the chip, and finally causes the chip to be damaged. As shown in fig. 2, the stress from the shrinkage deformation of the substrate 102 causes the bumps at the edge of the chip 100 to be inclined inward, and the chip may be damaged because the bumps are forced to be inclined.

Specifically, as shown in fig. 3, under the stress (black arrow in fig. 3) from the shrinkage deformation of the substrate, the bump 102 is inclined toward the inner side of the chip, and the inclination of the bump 102 toward the inner side of the chip results in a tensile stress acting on the chip region 100A outside the bump and a compressive stress acting on the chip region 100B inside the bump, and the tensile stress and the compressive stress cause severe damage to the chip. For example, in chip region 100A outside the bump, the tensile stress causes the passivation layer to crack and peel off, while in chip region 100B inside the bump, the compressive stress causes the second passivation layer to be damaged and the aluminum layer to be deformed.

The analysis was confirmed by observation through a scanning electron microscope before and after the damage to the chip 100. Fig. 4A and 4B show scanning electron microscope representations of the damage process of the chip 100 under stress from the bumps. Wherein the chip bump area (e.g., copper pillar) 400 indicates, the passivation layer area 401 indicates, and the aluminum layer area (pad or redistribution layer) 402 indicates, as shown in fig. 4A and 4B, the stress from the bump has a tensile stress on the chip area 100A outside the bump and a compressive stress on the chip area 100B inside the bump, the tensile stress causes the passivation layer to crack and peel off, and the compressive stress causes the second passivation layer and the aluminum layer to deform.

However, not all bumps 102 of the chip 100 may damage the chip under stress, and then we continue to analyze whether the bumps 102 damage the chip and which factors are related.

Fig. 5A shows a top view illustrating bumps 101 on chip 100, and fig. 5B shows a schematic diagram illustrating the stress experienced by each bump in the presence of additional stress. The X-direction and the Y-direction, and the diagonal direction therebetween are defined herein for convenience of explanation.

As shown in fig. 5A and 5B, when the additional stress (i.e., the stress from the shrinkage deformation of the substrate) is not present, each bump 101 is not subjected to the additional stress, and when the additional stress is present, the stress from the X direction or the Y direction is relatively small for the bump 102 in the non-corner region, and the stress from both the X direction and the Y direction is relatively large for the bump 102 in the edge corner region. Under the combined stress in the X and Y directions, the bump 102 located in the edge corner region is most inclined along the diagonal line, and as described above, the tensile stress acts on the chip region 100A outside the bump, and the compressive stress acts on the chip region 100B inside the bump, and both the tensile stress and the compressive stress cause severe damage to the chip.

The above analysis, that is, the corner regions of the chip 100 are more susceptible to damage than other regions, is confirmed by a scanning acoustic wave diagnostic test (SAT) for the packaged chip to detect whether the chip is delaminated by ultrasonic waves, as shown in fig. 6A and 6B. The area surrounded by 600A is a region that passes the SAT test, and the area surrounded by 600B is a region that does not pass the SAT test, that is, a region where chip damage such as passivation layer fracture, delamination and the like exists in the quality test of the packaged chip. It was found by observation and test that the bump density (the number of bumps per unit area) was large in the region that passed the test, and was small in the region that failed the test. This is because when the bump density is small, each bump is subjected to a large stress, and accordingly the chip in this region is easily damaged, whereas when the bump density is large, each bump is subjected to a small stress, and accordingly the chip in this region is not easily damaged.

Although the bumps in the corner regions of the chip are highly stressed and tend to cause chip damage, the bumps not located in the corner regions tend to cause chip damage. As shown in fig. 6C, in the region 600D closer to the edge in the corner region of the chip, no chip damage is caused, while in the inner region 600B, most of the isolated bumps match the chip structure. The main difference between the two regions is the bump density, which is greater in the region 600D and thus does not cause chip damage, while the bump density is less in the region 600B and thus causes chip damage due to the fact that most of the bumps are isolated bumps matching the chip structure and fail the SAT test. In other words, in the corner region of the chip, whether the chip is damaged in the packaging quality test or not is related to the bump density, the larger the bump density is, the less the chip is damaged, and the smaller the bump density is, the more the chip is damaged.

Based on the above analysis, the present invention provides a new method for manufacturing a semiconductor device, which is used to avoid the problems of cracking and peeling of the passivation layer, damage of the second passivation layer, deformation of the aluminum layer, etc. during the package quality test of the semiconductor device. The method has the basic idea that the protection wall is formed around the isolated bump, the protection wall can limit the effect of stress caused by the deformation of the packaging substrate on the isolated bump in the packaging quality test, and can support and balance the weight, and the protection wall is not easy to collapse, so that the stress resistance of the isolated bump and a device is enhanced, and the problems of passivation layer cracking and peeling, second passivation layer damage, aluminum layer deformation and the like are not easy to occur in the packaging chip quality test of the semiconductor device.

A method for fabricating a semiconductor device according to an embodiment of the present invention is described in detail below with reference to fig. 7A and 7B. Fig. 7A is a schematic top view of a device wafer with bumps and protection walls formed according to an embodiment of the invention; fig. 7B is a schematic cross-sectional view of a device wafer with bumps and protection walls formed according to an embodiment of the invention.

As shown in fig. 7A, bumps are formed on the device wafer 700 for connection with a package substrate to provide circuit connection for distribution of power and signals, and in the schematic arrangement of bumps shown in fig. 7A, dense bumps 701A, which refer to bumps in a region with a greater bump density, around which neighboring regions each bump is formed with the same dense bumps, and isolated bumps 701B, which refer to bumps in a region with a lower bump density, around which each bump is relatively isolated and around which no other bumps are formed. When the device wafer 700 is subjected to an external stress, the isolated bumps 701B are subjected to a large stress, and a device damage problem such as a passivation layer crack peeling is easily caused around the isolated bumps, for this reason, protective walls 702 are formed around the isolated bumps 701B to surround the isolated bumps, as shown in fig. 7A, one protective wall 702 is formed in each of two corner regions where the isolated bumps exist, and the protective walls can surround the isolated bumps 701B in the corner regions, wherein when the external stress is applied, the stress applied to the isolated bumps 701B in a region with a low bump density is limited and released by the protective walls surrounding the isolated bumps, the stress applied to the isolated bumps is reduced, and the influence on the bumps is insufficient (i.e., the bumps are inclined inward), so that a problem such as a passivation layer damage is not easily caused in a packaged chip quality test.

Illustratively, in an embodiment of the present invention, as shown in fig. 7A, the protection wall has a rectangular shape, which encloses the isolated bumps in the corresponding region. It is of course understood that the shape of the protection wall is not limited to a rectangular shape, but is determined according to the distribution of the bumps and the isolated bumps, and may be, for example, a circular shape, a rectangular shape, a square shape, a diamond shape, a hexagonal shape, or any other suitable regular or irregular shape.

Further, the material of the protection wall is preferably the same as the material of the bump, for example, when the bump is a copper pillar bump, the material of the protection wall is also copper, so as to reduce the process steps and the cost. Of course, in other embodiments, the material of the protection wall may be different from that of the bump.

Further, in order to make the protection wall stronger, a corresponding redistribution layer is formed on the device wafer 700 without the protection wall 702, that is, the protection wall 702 is formed on the redistribution layer or connected with the redistribution layer, so that the protection wall is stronger, and the limiting effect of the protection wall on the stress and the stress resistance of the device are further improved.

As shown in fig. 7B, a first redistribution layer 703 for connection with bumps and a second redistribution layer 704 for connection with protection walls are formed on the device wafer 700, and a passivation layer 705 and a protection layer 706 covering the first redistribution layer 703 and the second redistribution layer 704, openings are formed in the passivation layer 705 and the protection layer 706 to expose areas where the bumps and the protection walls are to be formed, and then the bump protection walls are formed by filling corresponding materials and patterning steps.

Further, in order to make the protection wall stronger, it is preferable that the bottom area of the protection wall 702 (i.e., the area of the side in contact with the second re-wiring layer 704) is smaller than the surface area of the second re-wiring layer 704 (i.e., the area of the side in contact with the protection wall 702), so that the adhesion between the protection wall 702 and the second re-wiring layer 704 can be increased, and the stability and stress resistance of the protection wall 702 can be improved.

Furthermore, in the embodiment of the present invention, the second redistribution layer 704 used for connecting with the protection wall is a dummy redistribution layer, which is not electrically connected with the metal interconnection layer in the device wafer, i.e. the second redistribution layer 704 is only used for making the protection wall more robust, and is not used for implementing other electrical functions.

Further, after the protective wall is added, the semiconductor device and the package substrate are also improved in adaptability in order to facilitate the packaging of the semiconductor device and make the protective wall stable and firm. The packaging method using this new design is described below with reference to fig. 8A to 8C.

First, as shown in fig. 8A, a device wafer 800 and a package substrate 900 are provided.

The device wafer 800 includes, among other things, a semiconductor substrate such as silicon, device layers, interconnect layers (not shown), and a passivation layer 801, a first re-wiring layer 802 for connection with bumps, and a second re-wiring layer 803 for connection with protection walls. Various semiconductor elements such as PMOS or NMOS, etc. are formed in the substrate of the device wafer, an interconnect layer is used to connect the various semiconductor elements in the semiconductor substrate, and a passivation layer 801 is used to protect the semiconductor devices.

Further, bumps for connecting with the package substrate are formed on the device wafer 800, the bumps include dense bumps and isolated bumps as described above, only isolated bumps 805 are shown here for the sake of brevity, the isolated bumps 805 are formed on the first redistribution layer 802 (such as a redistribution aluminum layer), and simultaneously, as described above, protection walls 806 are formed around the isolated bumps 805 to surround the isolated bumps 805, and simultaneously, in order to stabilize and secure the protection walls, the protection walls 806 are formed on the dummy second redistribution layer 803. Illustratively, the second re-wiring layer 803 is a dummy re-wiring layer, which is electrically connected to the interconnect layers in the device wafer.

The package substrate 900 is formed with pads 901 corresponding to bumps (e.g., isolated bumps 805) and contacts 902 corresponding to the protection walls, wherein the pads 901 are used for connecting with the bumps 805 and participating in circuit connection, the contacts 902 are used only for connecting with the protection walls and not participating in circuit connection, and the shape of the contacts 902 corresponds to the shape of the protection walls.

It should be understood that bump-to-pad correspondence means that the bump-to-pad shape and distribution are consistent, and that corresponding bumps and pads may be bonded to each other when the device wafer and package substrate are joined together, i.e., the pads and bumps may coincide with each other, or one may encompass the other, without the bumps and pads being misaligned or only a portion of the area may contact each other.

Next, as shown in fig. 8B, the bump 805 and the protection wall 806 are soldered with the corresponding solder joint 901 and the contact point 902 by a suitable solder 903, such as tin, to realize the connection between the device wafer 800 and the package substrate 900, such that the connected protection wall 806 and the contact point 902 form a final protection wall for the isolated bump in the packaged device, and limit the stress caused by deformation to act on the isolated bump 805 during the packaging test, thereby avoiding the problems such as damage to the passivation layer.

Finally, as shown in fig. 8C, the device wafer 800 is encapsulated by a suitable material 904 to complete the final package.

It is understood that in order to better connect the device wafer 800 and the package substrate 900, the contact points 902 corresponding to the protection walls are formed on the package substrate 900, but in fact, in other embodiments, the contact points 902 may not be formed, and when the package substrate 900 is deformed due to a thermal cycle in a semiconductor package quality test, the protection walls may also contact the package substrate and limit an external stress applied to the isolated bumps due to the deformation of the package substrate 900, thereby preventing device damage.

Fig. 9 shows a flowchart of the semiconductor device packaging method described above. The packaging method comprises the following steps:

step S901, providing a device wafer and a package substrate, forming bumps on the device wafer, where the bumps include dense bumps and isolated bumps, forming a protection wall surrounding the isolated bumps around the isolated bumps, and forming solder joints and contact points corresponding to the bumps and the protection wall on the package substrate.

And step S902, welding the lug and the protection wall with the corresponding welding point and the corresponding contact point together.

Step S903, a suitable packaging material is used to encapsulate the semiconductor device to complete the final package.

Example two

In addition to the above-described semiconductor device fabrication method and packaging method, another aspect of the present invention provides a semiconductor device, which can be prepared by the above-described method.

As shown in fig. 8C, a semiconductor device according to an embodiment of the present invention includes a device wafer 800 and a package substrate 900, wherein bumps for connecting with the package substrate 900 are formed on the device wafer 800, the bumps include dense bumps and isolated bumps 805, a protection wall 806 surrounding the isolated bumps is formed around the isolated bumps 805, and solder joints 901 corresponding to the bumps are formed on the package substrate, and the bumps and the solder joints are connected together to realize the connection between the device wafer 800 and the package substrate 900.

Illustratively, the shape of the protection walls 806 corresponds to the distribution of the positions of the dense bumps and the isolated bumps.

Illustratively, the shape of the protection wall 806 is circular, rectangular, square, diamond, or hexagonal.

Illustratively, a redistribution layer is further formed on the device wafer 800, and the redistribution layer includes a first redistribution layer 802 for connecting with the bump and a second redistribution layer 803 for connecting with the protection wall.

Illustratively, the second redistribution layer 803 is a dummy redistribution layer that is not electrically connected to metal interconnect layers in the device wafer 800.

Illustratively, the surface area of the second redistribution layer 803 is larger than the bottom area of the protection wall 806.

Illustratively, contact points 902 corresponding to the protection walls 806 are further formed on the package substrate 900, and the protection walls 806 and the contact points 902 are connected together to connect the device wafer 800 and the package substrate 900.

According to the semiconductor device provided by the embodiment of the invention, the protection wall is formed, so that the effect of stress caused by deformation of the packaging substrate on the isolated bump can be limited in the packaging quality test, and the stress resistance of the isolated bump and the device is enhanced, so that the problems of cracking and peeling of the passivation layer, damage of the second passivation layer, deformation of the aluminum layer and the like are not easy to occur in the packaging chip quality test of the semiconductor device, and the reliability of the semiconductor device is improved.

EXAMPLE III

Yet another aspect of the present invention also provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. The semiconductor device is manufactured by the manufacturing method of the semiconductor device, or the semiconductor device is manufactured as described above.

The electronic component may be any electronic component such as a discrete device and an integrated circuit.

The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.

Fig. 10 shows an example of a cellular phone. The exterior of the cellular phone 1000 is provided with a display portion 1002, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like, which are included in a housing 1001.

The electronic device of the embodiment of the invention has better yield and performance because the included semiconductor devices have reduced micro-loading effect and line collapse problem. The electronic device also has similar advantages.

The electronic device according to the embodiment of the present invention has the advantages described above because the semiconductor device described above is used.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a device wafer, and forming a rewiring layer on the device wafer;

forming bumps for connecting with a packaging substrate on the device wafer, wherein the bumps comprise dense bumps and isolated bumps, and protective walls surrounding the isolated bumps are formed around the isolated bumps;

a protective layer is filled between the isolated bump and the protective wall, and the base of the protective wall is connected with a virtual rewiring layer, so that the protective wall is firmer; wherein the dummy rewiring layer is not electrically connected to the metal interconnect layer in the device wafer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein a shape of the protective wall is determined based on a positional distribution of the dense bumps and the isolated bumps.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the shape of the protective wall is circular, rectangular, square, diamond, or hexagonal.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the rewiring layer includes a first rewiring layer for connection with the bump and a second rewiring layer for connection with the protection wall.

5. The method of manufacturing a semiconductor device according to claim 4, wherein the second re-wiring layer is a dummy re-wiring layer that is not electrically connected to a metal interconnect layer in the device wafer.

6. The method for manufacturing a semiconductor device according to claim 4, wherein a surface area of the second rewiring layer is larger than a bottom area of the protection wall.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, further comprising:

providing a packaging substrate, wherein welding spots corresponding to the bumps are formed on the packaging substrate;

and completing the connection of the device wafer and the packaging substrate through the bumps and the welding spots.

8. The method for manufacturing a semiconductor device according to claim 7, further comprising:

forming a contact point corresponding to the protection wall on the package substrate,

and connecting the protection wall and the contact point while connecting the bump and the welding point.

9. The semiconductor device is characterized by comprising a device wafer, wherein bumps for connecting with a packaging substrate are formed on the device wafer, the bumps comprise dense bumps and isolated bumps, and protective walls surrounding the isolated bumps are formed around the isolated bumps;

a rewiring layer is further formed on the device wafer, a protective layer is filled between the isolated bump and the protective wall, and the base of the protective wall is connected with the rewiring layer in a dummy mode, so that the protective wall is firmer; wherein the dummy rewiring layer is not electrically connected to the metal interconnect layer in the device wafer.

10. The semiconductor device according to claim 9, wherein a shape of the protective wall corresponds to a positional distribution of the dense bumps and the isolated bumps.

11. The semiconductor device according to claim 10, wherein the shape of the protective wall is a circle, a rectangle, a square, a diamond, or a hexagon.

12. The semiconductor device according to claim 9, wherein the rewiring layer includes a first rewiring layer for connection with the bump and a second rewiring layer for connection with the protection wall.

13. The semiconductor device of claim 12, wherein the second re-wiring layer is a dummy re-wiring layer that is not electrically connected to metal interconnect layers in the device wafer.

14. The semiconductor device according to claim 12, wherein a surface area of the second re-wiring layer is larger than a bottom area of the protection wall.

15. The semiconductor device according to any one of claims 9 to 14, further comprising: and the packaging substrate is provided with welding spots corresponding to the bumps, and the bumps and the welding spots are connected together to realize the connection of the device wafer and the packaging substrate.

16. The semiconductor device of claim 15, wherein contacts corresponding to the protection walls are further formed on the package substrate, the protection walls and contacts being connected together to enable connection of the device wafer and the package substrate.

17. An electronic device comprising a semiconductor device according to any one of claims 9 to 16 and an electronic component connected to the semiconductor device.