CN205582891U - Chip testing structure of integrated encapsulation - Google Patents
Chip testing structure of integrated encapsulation Download PDFInfo
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- CN205582891U CN205582891U CN201620367664.6U CN201620367664U CN205582891U CN 205582891 U CN205582891 U CN 205582891U CN 201620367664 U CN201620367664 U CN 201620367664U CN 205582891 U CN205582891 U CN 205582891U
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Abstract
The utility model provides a chip testing structure of integrated encapsulation, including the chip, with bump structure that the chip is connected, with the base plate of bump structural connection and being located be used for connecting the tin ball of PCB board on the base plate, wherein, the bump structure still includes the bump, is located bump outlying triangle metab and respectively from the triangle metab extend and with the connection structure that the bump is connected, the axis direction of triangle metab is unanimous with the direction of the combined stress that the bump receives. Through the chip testing structure, solved among the prior art because the thermal expansion coefficient of plastic substrate and silicon mismatches the bigger deformation of plastic substrate emergence in test procedure for the bump bears bigger power, leads to the problem of chip because of the atress damage.
Description
Technical field
This utility model relates to a kind of test structure, particularly relates to the chip testing structure of a kind of integration packaging.
Background technology
Flip-chip packaging techniques is nineteen sixty IBM Corporation's exploitation, in order to reduce cost, improves speed, improves assembly reliability,
Directly components and parts are interconnected on substrate down by the salient point on chip, and by stannum ball, chip are connected with described PCB, contracting
Little package dimension, improves electrical property；And the effect of solder bump just act as between IC and circuit board mechanically interconnected, electric
Interconnect the hottest interconnection.
Flipchip-bumped structure is applied to the chip-packaging structure of 28nm, and salient point is used for connecting chip and substrate.Such as Fig. 1 extremely
Shown in Fig. 3, Fig. 1 is chip-packaging structure, and Fig. 2 is the chip-packaging structure deformed after high/low temperature loop test,
Fig. 3 is described salient point stress schematic diagram；Encapsulation chip is during high/low temperature loop test, owing to substrate 3 is plastics, and chip
1 is Si, and the thermal coefficient of expansion between substrate 3 and chip 1 does not mates, during high/low temperature, and plastic base 3 ratio Si chip
1 shrinks faster, causes substrate 3 that bigger deformation occurs, and this deformation result in bigger power and acts on salient point 2, salient point 2
This power is transferred to chip 1, finally results in wafer damage.It is known that owing to substrate 3 deforms upon, salient point 2 can bear
From X-axis and the power of Y-axis both direction, the pressure of the X-direction i.e. caused by substrate 3 deformation and the pulling force of Y direction,
Two power all can cause chip 1 badly damaged, comes off as quick property polyimides (PI) ruptures, and passivation layer damages and metallic aluminium pad
Deformation etc..
Technical staff uses ultrasonic microscope to be analyzed the encapsulation chip being damaged, and in terms of the inspection result of salient point, loses
Effect regional centralized is on the isolated salient point of corner regions, and compared to highdensity salient point region, low-density salient point region can be born
Bigger power, this region is also easier to be damaged；That is failed areas is relevant to the density of salient point, region salient point
Density is the lowest, and the power that this region is born when substrate deformation is the biggest, causes passivation layer in test process to rupture and deform,
Cause test crash.Owing to the structural requirement of 28nm product must arrange isolated salient point region in upper left and lower right field, this is just
Cause to solve this problem by increasing bump density.
In consideration of it, be necessary to design a kind of new bump structure in order to solve above-mentioned technical problem.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is that the chip testing providing a kind of integration packaging is tied
Structure, for solving owing to the thermal coefficient of expansion of plastic base and Si chip does not mates in prior art, plastics base in test process
There is bigger deformation, the problem causing wafer damage in plate.
For achieving the above object and other relevant purposes, this utility model provides the chip testing structure of a kind of integration packaging, described
Chip testing structure includes substrate, the Yi Jiwei that the bump structure that chip is connected is connected with described bump structure with described chip
For the stannum ball of connecting PCB board on described substrate, wherein, described bump structure also includes salient point, is positioned at described salient point periphery
Triangle metab and extend and the attachment structure that is connected with described salient point from triangle metab respectively, described triangle metal
Suffered by the axis direction of base and salient point, the direction of combined stress is consistent.
Preferably, described salient point is isolated salient point.
Preferably, described triangle metab is equilateral triangle metab.
Preferably, described combined stress is making a concerted effort of pulling force suffered by salient point and pressure.
Preferably, described attachment structure is the face structure that three angles from triangle metab each extend over and are connected with described salient point.
Preferably, described attachment structure is the face structure that three limits from triangle metab each extend over and are connected with described salient point.
Preferably, described attachment structure is the line structure that three angles from triangle metab each extend over and are connected with described salient point.
Preferably, described triangle metab is triangle copper pedestal.
Preferably, described attachment structure is copper attachment structure.
As it has been described above, the chip testing structure of a kind of integration packaging of the present utility model, have the advantages that described chip
Test structure by arranging triangle metab in salient point periphery, and by arranging attachment structure by described salient point and triangle metal bottom
Seat connects, it is achieved the part power born by described salient point transfers to triangle metab, and by triangle metab by described power
Discharge, for solving in prior art owing to the thermal coefficient of expansion of plastic base and Si chip does not mates, mould in test process
There is bigger deformation in material substrate so that salient point bears bigger power, ultimately results in the problem that chip damages because of stress.
Accompanying drawing explanation
Fig. 1 is shown as prior art chips encapsulating structure schematic diagram.
Fig. 2 is shown as the chip-packaging structure schematic diagram after deforming upon in prior art.
Fig. 3 is shown as salient point stress schematic diagram.
Fig. 4 is shown as the direction schematic diagram of combined stress suffered by salient point.
Fig. 5 is shown as the structural representation of this utility model embodiment one.
Fig. 6 is shown as the bump structure schematic diagram of this utility model embodiment one.
Fig. 7～Figure 11 is the making step that this utility model embodiment one tests structure.
Figure 12 is shown as the sectional view in the bump structure HH ' direction of this utility model embodiment one.
Figure 13 is shown as the bump structure schematic diagram of this utility model embodiment two.
Figure 14 is shown as the bump structure schematic diagram of this utility model embodiment three.
Element numbers explanation
1 chip
2 bump structures
21 salient points
22 triangle metabs
23 attachment structures
3 substrates
4 stannum balls
5 aluminum pads
6 passivation layers
7 polyimides
8 photoresists
9 solders
10 solder joints
11 non-conducting materials
Detailed description of the invention
Below by way of specific instantiation, embodiment of the present utility model being described, those skilled in the art can be by this specification institute
The content disclosed understands other advantages of the present utility model and effect easily.This utility model can also be by the most different tools
Body embodiment is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, at the not back of the body
Various modification or change is carried out under spirit of the present utility model.
Refer to Fig. 4 and Figure 14.It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., the most only in order to
Coordinating the content disclosed in description, understand for those skilled in the art and read, being not limited to this utility model can
The qualifications implemented, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the tune of size
Whole, under not affecting effect that this utility model can be generated by and the purpose that can reach, all should still fall and be taken off at this utility model
In the range of the technology contents shown obtains and can contain.Meanwhile, in this specification cited as " on ", D score, " left ",
The term of " right ", " middle " and " one " etc., be merely convenient to narration understand, and be not used to limit this utility model can
The scope implemented, being altered or modified of its relativeness, changing under technology contents without essence, can when being also considered as this utility model
The category implemented.
Embodiment one
Refer to the direction schematic diagram that Fig. 4 to Fig. 6, Fig. 4 are combined stress suffered by salient point, wherein AA ', BB ', CC ',
DD ', EE ', FF ', GG ' are the direction of combined stress suffered by salient point 21, and Fig. 5 is the structure of this utility model embodiment one
Schematic diagram, Fig. 6 is the bump structure schematic diagram of this utility model embodiment one.As shown in Figures 4 to 6, described chip testing
Structure includes substrate 3, the Yi Jiwei that the bump structure 2 that chip 1 is connected is connected with described bump structure 2 with described chip 1
For the stannum ball 4 of connecting PCB board on described substrate 3, wherein, described bump structure 2 also include salient point 21, be positioned at described
The triangle metab 22 of salient point 21 periphery and the company extending from triangle metab 22 respectively and being connected with described salient point 21
Access node structure 23, the direction of combined stress suffered by the axis direction of described triangle metab 22 and salient point 21 is consistent.
It should be noted that the center line that axis is triangle metab 22 of described triangle metab 22.
Concrete, described salient point 21 is isolated salient point.
It should be noted that owing to isolated salient point has bigger idle area compared to other salient points, this idle area is for realizing
Described bump structure provides space.
Concrete, described combined stress is making a concerted effort of pulling force suffered by salient point 21 and pressure.
It should be noted that owing to substrate 3 deforms upon, salient point 21 can bear from X-axis and the power of Y-axis both direction, i.e.
The pressure of the X-direction caused by substrate 3 deformation and the pulling force of Y direction；Design the axis side of described triangle metab 22
To with salient point 21 suffered by the direction of combined stress consistent, it is ensured that when described salient point 21 is by during from the pressure of substrate and pulling force,
Described triangle metab 22 can bear bigger power.
Concrete, described triangle metab 22 is triangle copper pedestal, and described attachment structure 23 is copper attachment structure.
Concrete, described attachment structure 23 is that three angles from triangle metab 22 each extend over and are connected with described salient point 21
Face structure.
It should be noted that described attachment structure 23 for being transferred to described triangle gold by the combined stress suffered by described salient point 21
Belong to base 22, eventually through described triangle metab 22, the combined stress suffered by salient point 21 is discharged；In the present embodiment,
Described attachment structure 23 is structure as a whole with described triangle metab 22, and described triangle metab 22 is equilateral triangle metal
Base；Use equilateral triangle metab, it is ensured that the length of three attachment structures 23 is identical so that described triangle metab
22 uniform stresseds.
In the present embodiment, described triangle metab 22, attachment structure 23 define a kind of new salient point with described salient point 21
Structure, in the case of lifting surface area is constant, by increasing the region contiguously of bump structure, thus increases described bump structure
Ability to bear to power, and accelerate the described bump structure rate of release to power, and then avoid in integrated chip packaging and testing
The problem that chip damages because of stress.
Under request in person the making step of the chip testing structure to a kind of integration packaging described in the utility model and carry out with reference to Fig. 7 to Figure 14
Explanation.As shown in Fig. 7 to Figure 12:
Step 1: provide a chip 1, forms one in the side of described chip 1 by physical gas-phase deposite methods such as sputtering, evaporations
Aluminium lamination, performs etching described aluminium lamination, forms aluminum pad 5.
Step 2: use chemical gaseous phase formation of deposits passivation layer 6, described passivation layer 6 covering part aluminum pad 5 on chip 1；
Step 3: coat a strata acid imide (PI) 7 on described passivation layer 6, then coating photoresist 8, and by photoetching,
Etching forms the pattern of bump structure 2, and polyimides 7 and photoresist 8 determine shape and the height of electroplating bumps structure 2.
Step 4: use electro-coppering (ECP) technology to be electroplated onto by solder 9 in the opening of described photoresist 8, described solder 9 is entered
Row cmp (CMP), forms bump structure 2, finally removes photoresist 8.
Step 5: use electroplating technology to form the solder joint 10 corresponding with bump structure 2 on the substrate 3, and tie at described salient point
Coated with flux on structure 2 and substrate 3, bonds the chip 1 in described step 4, then with the described substrate 3 with solder joint 10
Use non-conducting material 11 to fill chip bottom space, on described substrate 3, finally form stannum ball 4.
It should be noted that the most described solder 9 is Cu, in the present embodiment, described salient point 2 is copper post, described
Triangle metab 22 and attachment structure 23 are all steel structure.Described bump structure 2 includes salient point 21, triangle metab
22 and attachment structure 23, wherein, the height of described attachment structure 23 is identical with the height of described salient point 21.This utility model
The manufacture method of described test structure is not limited solely to said method, also includes making test knot described in this utility model simultaneously
Other method of structure.
Embodiment two
Refer to Figure 13, in the test structure described in the present embodiment two, the salient point being connected with described chip 1 including chip 1
Substrate 3 that structure 2 is connected with described bump structure 2 and be positioned on described substrate 3 the stannum ball 4 for connecting PCB board,
Wherein, described bump structure 2 also include salient point 21, the triangle metab 22 being positioned at described salient point 21 periphery and respectively from
The attachment structure 23 that triangle metab 22 extends and is connected with described salient point 21, the axis side of described triangle metab 22
To with salient point 21 suffered by the direction of combined stress consistent.Wherein, described attachment structure 23 is three from triangle metab 22
While the face structure each extending over and being connected with described salient point 21.Attachment structure 23 described in the present embodiment is by increasing with described
The contact area of triangle metab 22, accelerates the described bump structure rate of release to power, thus avoids integrated chip encapsulation to survey
The problem that examination chips is damaged because of stress.
Embodiment three
Refer to Figure 14, in the test structure described in the present embodiment three, the salient point being connected with described chip 1 including chip 1
Substrate 3 that structure 2 is connected with described bump structure 2 and be positioned on described substrate 3 the stannum ball 4 for connecting PCB board,
Wherein, described bump structure 2 also include salient point 21, the triangle metab 22 being positioned at described salient point 21 periphery and respectively from
The attachment structure 23 that triangle metab 22 extends and is connected with described salient point 21, the axis side of described triangle metab 22
To with salient point 21 suffered by the direction of combined stress consistent.Wherein, described attachment structure 23 is three from triangle metab 22
The line structure that angle each extends over and is connected with described salient point 21.Attachment structure 23 described in the present embodiment is described convex by increasing
The region contiguously of dot structure, it is achieved increase the described bump structure ability to bear to power, and accelerate described bump structure to power
Rate of release, thus avoid the problem that integrated chip packaging and testing chips damages because of stress.
In sum, this utility model provides a kind of bump structure eliminating integrated chip packaging and testing problem, described bump structure
By arranging described triangle metab and described attachment structure in the periphery of described salient point so that described bump structure is in stress
In the case of region is constant, increase the region contiguously of described bump structure, so that bump structure can bear bigger synthesis
Stress and the quickening bump structure release to suffered combined stress, it is achieved solve in prior art due to plastic base and Si chip
Thermal coefficient of expansion do not mate, there is bigger deformation in plastic base in test process so that salient point bears bigger power,
Cause the problem that chip damages because of stress eventually.
Above-described embodiment only illustrative principle of the present utility model and effect thereof, not for limiting this utility model.Any
Above-described embodiment all can be modified under spirit and the scope of the present utility model or change by those skilled in the art.
Therefore, such as art has usually intellectual without departing from the spirit disclosed in this utility model with under technological thought
All equivalences completed are modified or change, and must be contained by claim of the present utility model.
Claims (9)
1. the chip testing structure of an integration packaging, it is characterised in that: described chip testing structure includes chip and described chip even
Substrate that the bump structure connect is connected with described bump structure and be positioned on described substrate the stannum ball for connecting PCB board,
Wherein, described bump structure also includes salient point, is positioned at the peripheral triangle metab of described salient point and respectively from triangle metal bottom
Combined stress suffered by the attachment structure that seat extends and is connected with described salient point, the axis direction of described triangle metab and salient point
Direction is consistent.
The chip testing structure of integration packaging the most according to claim 1, it is characterised in that: described salient point is isolated salient point.
The chip testing structure of integration packaging the most according to claim 1, it is characterised in that: described triangle metab is equilateral
Triangle metab.
The chip testing structure of integration packaging the most according to claim 1, it is characterised in that: described combined stress is suffered by salient point
Making a concerted effort of pulling force and pressure.
The chip testing structure of integration packaging the most according to claim 1, it is characterised in that: described attachment structure is from triangle gold
Belong to the face structure that three angles of base each extend over and are connected with described salient point.
The chip testing structure of integration packaging the most according to claim 1, it is characterised in that: described attachment structure is from triangle gold
Belong to the face structure that three limits of base each extend over and are connected with described salient point.
The chip testing structure of integration packaging the most according to claim 1, it is characterised in that: described attachment structure is from triangle gold
Belong to the line structure that three angles of base each extend over and are connected with described salient point.
The chip testing structure of integration packaging the most according to claim 1, it is characterised in that: described triangle metab is triangle
Copper pedestal.
The chip testing structure of integration packaging the most according to claim 1, it is characterised in that: described attachment structure is that copper connects knot
Structure.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620367664.6U CN205582891U (en) | 2016-04-27 | 2016-04-27 | Chip testing structure of integrated encapsulation |
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| CN201620367664.6U CN205582891U (en) | 2016-04-27 | 2016-04-27 | Chip testing structure of integrated encapsulation |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108573885A (en) * | 2017-03-07 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic device |
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- 2016-04-27 CN CN201620367664.6U patent/CN205582891U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108573885A (en) * | 2017-03-07 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic device |
| CN108573885B (en) * | 2017-03-07 | 2021-03-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
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