CN1779969A - Integrated circuit structure with welding pad on top of active circuit - Google Patents
Integrated circuit structure with welding pad on top of active circuit Download PDFInfo
- Publication number
- CN1779969A CN1779969A CNA2004100947597A CN200410094759A CN1779969A CN 1779969 A CN1779969 A CN 1779969A CN A2004100947597 A CNA2004100947597 A CN A2004100947597A CN 200410094759 A CN200410094759 A CN 200410094759A CN 1779969 A CN1779969 A CN 1779969A
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- integrated circuit
- circuit structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
An IC structure with weld pads on active circuit is composed of a weld pad structure, at least one metallic interconnection wire layer, the first interlayer plug layer for electric connection between weld pad structure and metallic interconnection wire layer, and an active circuit under weld pad structure but on a semiconductor substrate. Said weld pad structure consists of a weldable metal pad, a top metallic interconnection wire layer, a buffering dielectric layer and at least one second interlayer plug for electric connection between top metallic inter connection wire layer and weldable metal pad.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit (integrated circuit) structure, relate in particular to a kind of integrated circuit structure that carries out top of active circuit welding (wire bonding over active circuit is designated hereinafter simply as BOAC).
Background technology
Along with the progress of semiconductor technology, the element minimum dimension of integrated circuit is constantly dwindled, and makes that also the volume of single wafer is more and more littler.Therefore the existing design that is dispersed in wafer perimeter switch-over soldering pad in a row (bonding pad) just becomes the obstacle that the wafer volume further dwindles.Therefore, a kind ofly can be laid with source circuit by the wafer area under switch-over soldering pad, so that the structure that the wafer volume is further dwindled, become the trend of current chip design and manufacturing.
As shown in Figure 1, Fig. 1 is existing BOAC integrated circuit structure generalized section.Existing BOAC integrated circuit structure 10 is to form a plurality of active circuits in semi-conductive substrate 12 tops; include I/O (I/O) element/circuit or electrostatic protection (ESD) element/circuit; and by a plurality of Semiconductor substrate 12 lip-deep metal-oxide-semiconductor transistor elements 14 that are made in; 16 and 18; shallow isolating trough (STI) 20 and 22; ion diffusion region 24; 26; 28 and 30; interlayer dielectric layer (ILD) 32; dielectric layer between metal layers (IMD) 34; 36 and 38 etc. and several layers of metal interconnecting wires (interconnection) layer 40; 42; 44; 46; 48; 50 and 52 formations, the part surface of the superiors' metal interconnecting wires layer 52 then is coated with a barrier layer 54 in addition; but a protective layer 56 and a weld metal pad 58.
As shown in Figure 1, in existing BOAC integrated circuit structure 10, but the superiors' metal interconnecting wires layer 52 is to be located at outside the covering scope of weld metal pad 58, and is electrically connected with the active circuit of below via outside circuit.Therefore, when carrying out routing welding (bonding), mechanical stress (mechanicalstress) but just can directly put on weld metal pad 58, this makes that easily but the bond of 52 on weld metal pad 58, barrier layer 54 and the superiors' metal interconnecting wires layer and the structure of below integrated circuit thereof are destroyed, and the outside circuit that is used to connect the superiors' metal interconnecting wires layer 52 and below active circuit that forms in addition is unfavorable for that also the wafer volume further dwindles.
Summary of the invention
Main purpose of the present invention is to provide a kind of BOAC integrated circuit structure, with the first interlayer connector (but connecting weld metal pad and the superiors' metal interconnecting wires layer) and the second interlayer connector (being connected welding pad structure and metal interconnecting wires layer) but be disposed at the below of weld metal pad.
According to purpose of the present invention, BOAC integrated circuit structure of the present invention is to comprise a welding pad structure, but this welding pad structure comprises a weld metal pad, one the superiors' metal interconnecting wires layer, but one is located at the buffer dielectric layer between weld metal pad and the superiors' metal interconnecting wires layer, and at least one first interlayer connector, but be arranged in the buffer dielectric layer of weld metal pad below, but be used for being electrically connected weld metal pad and the superiors' metal interconnecting wires layer, and this BOAC integrated circuit structure comprises at least one metal interconnecting wires layer in addition, at least one this welding pad structure below that is positioned at, be used for being electrically connected the second interlayer connector and an active circuit of welding pad structure and metal interconnecting wires layer, be located at welding pad structure below and be positioned on the semiconductor bottom.
But because the present invention increases by a buffer dielectric layer in weld metal pad and the superiors' metal interconnecting wires layer, so can be when routing welds, reduce the function influence that mechanical stress directly puts on the superiors' metal interconnecting wires layer, and then avoid the integrated circuit structure of below destroyed, and with the first interlayer connector (but connecting weld metal pad and the superiors' metal interconnecting wires layer) and the second interlayer connector (being connected welding pad structure and metal interconnecting wires layer) but be disposed at the below of weld metal pad, so just can reduce the area of wiring, significantly dwindle the volume of wafer, but more have than short lead between the active circuit owing to weld metal pad of the present invention and its below, so have preferable electrical performance.
In order to make those skilled in the art can further understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet appended graphic only for reference and explanation usefulness is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is existing BOAC integrated circuit structure generalized section;
Fig. 2 is the BOAC integrated circuit structure generalized section according to first preferred embodiment of the invention;
Fig. 3 is the BOAC integrated circuit structure generalized section according to second preferred embodiment of the invention;
Fig. 4 is the metal frame top view according to second preferred embodiment of the invention.
Embodiment
See also Fig. 2, Fig. 2 is the BOAC integrated circuit structure generalized section according to first preferred embodiment of the invention.As shown in Figure 2; BOAC integrated circuit structure 60 of the present invention includes a welding pad structure 62 and an active circuit zone 64; wherein but welding pad structure 62 also includes a weld metal pad 66; one the superiors' metal interconnecting wires layer 68; the first interlayer connector 70 and 72; but but be positioned at below and the electrical connection weld metal pad 66 and the superiors' metal interconnecting wires layer 68 that weld metal pad 66 protected seams 74 cover; and a buffer dielectric layer 76, but between weld metal pad 66 and the superiors' metal interconnecting wires layer 68.
Active circuit zone 64 can include I/O (I/O) element/circuit or electrostatic protection (ESD) element/circuit, and is made in Semiconductor substrate 77 lip-deep metal-oxide-semiconductor transistor elements 78,80 and 82, shallow isolating trough 84 and 86, ion diffusion region 88,90,92,94 and 96, interlayer dielectric layer 98, dielectric layer between metal layers 100,102,104 and 106 etc. and several layers of metal interconnecting wires layer 108,110,112,114,116,118 and 120 and is constituted by a plurality of.For convenience of description, following the preferred embodiments of the present invention are that example is done explanation with five layers of metal interconnecting wires, yet, it will be understood by those skilled in the art that category of the present invention is not limited thereto, but be as the criterion with the category described in the claim.The present invention also can be applicable to have in the integrated circuit of six, seven layers or more multi-layered metal interconnecting wires.
As shown in Figure 2, metal interconnecting wires layer 108 and 110 is to be defined in the interlayer dielectric layer 98, and with contact plunger 121 be made in Semiconductor substrate 77 lip-deep metal-oxide-semiconductor transistor elements 78,80 and 82, ion diffusion region 88,90,92,94 and 96 is electrically connected.Wherein interlayer dielectric layer 98 can for silicon dioxide, fluorine silex glass (fluoride silicate glass, FSG) or other advanced low-k materials.According to a preferred embodiment of the invention, the superiors' metal interconnecting wires layer 68 is the copper metal interconnecting wires with metal interconnecting wires layer 108,110,112,114,116,118 and 120, and inlays (copper damascene), dual damascene (dual damascene) technology manufacturing with the copper of standard.
As shown in Figure 2, metal interconnecting wires layer 112,114 and 116 is to be defined in the dielectric layer between metal layers 100 with copper enchasing technology, and the interlayer connector 122 that is electrically connected between metal interconnecting wires layer 108 and 112 is to be formed on simultaneously in the dielectric layer between metal layers 100 with copper enchasing technology and metal interconnecting wires layer 112.Dielectric layer between metal layers 100 is made of low-k or ultralow dielectric (ultra low-k) material.Herein, so-called ultra-low dielectric constant material is meant dielectric constant less than 2.5 dielectric material, and its structure is generally porousness and structure is comparatively fragile.Metal interconnecting wires layer 118 is to be defined in the dielectric layer between metal layers 102 with copper enchasing technology, and the interlayer connector 124 that is electrically connected between metal interconnecting wires layer 114 and 118 is to be defined in the dielectric layer between metal layers 102 with copper enchasing technology.Dielectric layer between metal layers 102 is made of advanced low-k materials.Metal interconnecting wires layer 120 is to be defined in the dielectric layer between metal layers 104 with copper enchasing technology, and the interlayer connector 126,128 and 130 that is electrically connected between metal interconnecting wires layer 118 and 120 is to be defined in the dielectric layer between metal layers 104 with copper enchasing technology.Dielectric layer between metal layers 104 is made of advanced low-k materials.The superiors' metal interconnecting wires layer 68 is to be defined in the dielectric layer between metal layers 106 with copper enchasing technology, but and weld metal pad 66 protected seams 74 cover below and the second interlayer connector 132,134 and 136 that is electrically connected between the superiors' metal interconnecting wires layer 68 and the metal interconnecting wires layer 120 also be to be defined in the dielectric layer between metal layers 106 with copper enchasing technology.Dielectric layer between metal layers 106 is made of advanced low-k materials.
But weld metal pad 66 is to be covered on the buffer dielectric layer 76, but and the first interlayer connector 70 and 72 that is electrically connected between the superiors' metal interconnecting wires layer 68 and the weld metal pad 66 is to be defined in the buffer dielectric layer 76.Buffer dielectric layer 76 is that the dielectric material with less holes such as silicon dioxide (less porous) or comparatively fine and close (denser) is constituted, so than each dielectric layer between metal layers densification, can be used to absorb the stress that is produced when welding.As previously mentioned, in the preferred enforcement of the present invention, but the weld metal pad 66 and the first interlayer connector 70 and 72 are aluminum metal, therefore are not to make with mosaic technology, but make with traditional aluminum metal lead technology.The superiors at BOAC integrated circuit structure 60 are protective layer 74; made by for example silicon nitride, polyimides (polyimide) or other protective material that equates; and protective layer 74 also has a welding opening, but exposes the upper surface of part weld metal pad 66 and form a welding window zone 138.
It should be noted that as shown in Figure 3 Fig. 3 is the BOAC integrated circuit structure generalized section according to second preferred embodiment of the invention.But connect the size in the first interlayer connector 70 of weld metal pad 66 and the superiors' metal interconnecting wires layer 68 and 72 also visual welding window zones 138 and be provided with, and on average be disposed at respectively in the buffer dielectric layer 76 of 138 belows, welding window zone, in addition, BOAC integrated circuit structure of the present invention is in 138 belows, welding window zone, can comprise one in addition by the made metal frame 140 of copper metal, be embedded in the dielectric layer between metal layers of the superiors metal interconnecting wires layer 68 below, for example dielectric layer between metal layers 104, be used as one and strengthen supporting construction, the stress that is produced when buffer dielectric layer 76 absorbs welding then can be offset by metal frame 140.As shown in Figure 4, Fig. 4 is metal frame 140 top views according to second preferred embodiment of the invention.Metal frame 140 is arranged in dielectric layer between metal layers 104.
Compared to prior art, BOAC integrated circuit structure of the present invention with the first interlayer connector (but connecting weld metal pad and the superiors' metal interconnecting wires layer) and the second interlayer connector (being connected welding pad structure and metal interconnecting wires layer) but be disposed at the below of weld metal pad, so can reduce the area of wiring, significantly dwindle the volume of wafer; But and in weld metal pad and the superiors' metal interconnecting wires layer, increase by a buffer dielectric layer, so can when routing welds, reduce the influence that mechanical stress directly puts on the superiors' metal interconnecting wires layer, avoid destroying the structure of integrated circuit; The present invention more increases by one by the made metal frame of copper metal in addition, is embedded in the dielectric layer between metal layers of the superiors metal interconnecting wires layer below, to strengthen the BOAC integrated circuit support structures; But more have than short lead between the active circuit owing to weld metal pad of the present invention and its below, so have preferable electrical performance.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (29)
1. a weld pad is located at the integrated circuit structure that top of active circuit welds, and comprising:
One welding pad structure;
At least one metal interconnecting wires layer;
At least one first interlayer connector is positioned at this welding pad structure below, is used for being electrically connected this welding pad structure and this metal interconnecting wires layer; And
One active circuit is located at this welding pad structure below and is positioned on the semiconductor bottom.
2. integrated circuit structure as claimed in claim 1, wherein this welding pad structure also comprises:
A but weld metal pad;
One the superiors' metal interconnecting wires layer;
One buffer dielectric layer, but be located between this weld metal pad and this superiors' metal interconnecting wires layer; And
At least one second interlayer connector, but be arranged in this buffer dielectric layer of this weld metal pad below, should weld metal pad and this superiors' metal interconnecting wires layer but be used for being electrically connected.
3. integrated circuit structure as claimed in claim 2 also comprises a protective layer, but covers on this buffer dielectric layer and this weld metal pad of part.
4. integrated circuit structure as claimed in claim 3, but wherein this first interlayer connector and this second interlayer connector all be positioned at be coated with this protective layer should weld metal pad the below.
5. integrated circuit structure as claimed in claim 3, wherein this protective layer also has a welding opening, is somebody's turn to do the upper surface of weld metal pad and forms a welding window zone but expose part.
6. integrated circuit structure as claimed in claim 5, wherein this second interlayer connector is to be positioned at this below, welding window zone.
7. integrated circuit structure as claimed in claim 3, wherein this protective layer is a silicon nitride.
8. integrated circuit structure as claimed in claim 3, wherein this protective layer is a polyimides.
9. integrated circuit structure as claimed in claim 2, wherein this buffer dielectric layer is a silicon dioxide.
10. integrated circuit structure as claimed in claim 2, but should the weld metal pad be an aluminum metal pad wherein.
11. integrated circuit structure as claimed in claim 6, wherein this second interlayer connector is an aluminium connector.
12. integrated circuit structure as claimed in claim 2 also comprises a metal frame, is embedded in the dielectric layer between metal layers of this superiors metal interconnecting wires layer below, is used as one and strengthens supporting construction.
13. integrated circuit structure as claimed in claim 12, wherein this buffer dielectric layer is to be used for absorbing the stress that is produced when welding, and is offset by this metal frame.
14. integrated circuit structure as claimed in claim 12, wherein this buffer dielectric layer is than this dielectric layer between metal layers densification.
15. integrated circuit structure as claimed in claim 12, wherein this metal interconnecting wires layer, this superiors' metal interconnecting wires layer and this metal frame are a damascene copper metal level.
16. integrated circuit structure as claimed in claim 1, wherein this semiconductor underlayer comprises at least one dielectric layer and semi-conductive substrate.
17. a weld pad is located at the integrated circuit structure of top of active circuit welding, comprising:
A but weld metal pad;
One the superiors' metal interconnecting wires layer, but be positioned at this weld metal pad below;
One buffer dielectric layer, but be located between this weld metal pad and this superiors' metal interconnecting wires layer;
At least one first interlayer connector, but be arranged in this buffer dielectric layer of this weld metal pad below, should weld metal pad and this superiors' metal interconnecting wires layer but be used for being electrically connected;
One protective layer, but cover this buffer dielectric layer and part should the weld metal pad on, and this protective layer also has a welding opening, but in order to expose the upper surface that part should the weld metal pad and to form a welding window zone;
At least one metal interconnecting wires layer is positioned at this superiors metal interconnecting wires layer below;
At least one second interlayer connector, but be positioned at the below of being somebody's turn to do the weld metal pad that is coated with this protective layer, be used for being electrically connected this superiors' metal interconnecting wires layer and this metal interconnecting wires layer; And
One active circuit, but be located at this weld metal pad below and be positioned on the semiconductor bottom.
18. integrated circuit structure as claimed in claim 17, but wherein this first interlayer connector is positioned at the below of being somebody's turn to do the weld metal pad that is coated with this protective layer.
19. integrated circuit structure as claimed in claim 17, wherein this first interlayer connector is positioned at this below, welding window zone.
20. integrated circuit structure as claimed in claim 17 also comprises a plurality of first interlayer connectors, but and those first interlayer connectors equidistantly be disposed at this weld metal pad below.
21. integrated circuit structure as claimed in claim 17, wherein this protective layer is a silicon nitride.
22. integrated circuit structure as claimed in claim 17, wherein this protective layer is a polyimides.
23. integrated circuit structure as claimed in claim 17, wherein this buffer dielectric layer is a silicon dioxide.
24. integrated circuit structure as claimed in claim 17, but should the weld metal pad be an aluminum metal pad wherein, and this first interlayer connector is an aluminium connector.
25. integrated circuit structure as claimed in claim 17 also comprises a metal frame, is embedded in the dielectric layer between metal layers of this superiors metal interconnecting wires layer below, is used as one and strengthens supporting construction.
26. integrated circuit structure as claimed in claim 25, wherein this buffer dielectric layer is to be used for absorbing the stress that is produced when welding, and is offset by this metal frame.
27. integrated circuit structure as claimed in claim 25, wherein this buffer dielectric layer is than this dielectric layer between metal layers densification.
28. integrated circuit structure as claimed in claim 25, wherein this metal interconnecting wires layer, this superiors' metal interconnecting wires layer and this metal frame are the damascene copper metal level.
29. integrated circuit structure as claimed in claim 17, wherein this semiconductor underlayer comprises at least one dielectric layer and semi-conductive substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100947597A CN100399564C (en) | 2004-11-17 | 2004-11-17 | Integrated circuit structure with welding pad on top of active circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100947597A CN100399564C (en) | 2004-11-17 | 2004-11-17 | Integrated circuit structure with welding pad on top of active circuit |
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| Publication Number | Publication Date |
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| CN1779969A true CN1779969A (en) | 2006-05-31 |
| CN100399564C CN100399564C (en) | 2008-07-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100947597A Active CN100399564C (en) | 2004-11-17 | 2004-11-17 | Integrated circuit structure with welding pad on top of active circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064155A (en) * | 2009-11-17 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN102130094A (en) * | 2009-12-28 | 2011-07-20 | 联发科技股份有限公司 | Integrated circuit chip |
| CN102184904A (en) * | 2011-04-12 | 2011-09-14 | 中颖电子股份有限公司 | Bonding disc structure aiming at BOAC frame and integrated circuit device structure |
| CN103000602A (en) * | 2011-09-12 | 2013-03-27 | 格罗方德半导体公司 | Strain-compensating fill patterns for controlling semiconductor chip package interactions |
| CN105489581A (en) * | 2015-12-25 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and fabrication method thereof |
| CN108447837A (en) * | 2017-02-16 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6444544B1 (en) * | 2000-08-01 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | Method of forming an aluminum protection guard structure for a copper metal structure |
| US20030020163A1 (en) * | 2001-07-25 | 2003-01-30 | Cheng-Yu Hung | Bonding pad structure for copper/low-k dielectric material BEOL process |
| US6762466B2 (en) * | 2002-04-11 | 2004-07-13 | United Microelectronics Corp. | Circuit structure for connecting bonding pad and ESD protection circuit |
| US6864124B2 (en) * | 2002-06-05 | 2005-03-08 | United Microelectronics Corp. | Method of forming a fuse |
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2004
- 2004-11-17 CN CNB2004100947597A patent/CN100399564C/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064155A (en) * | 2009-11-17 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN102064155B (en) * | 2009-11-17 | 2012-09-26 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN102130094A (en) * | 2009-12-28 | 2011-07-20 | 联发科技股份有限公司 | Integrated circuit chip |
| CN102130094B (en) * | 2009-12-28 | 2014-05-07 | 联发科技股份有限公司 | Integrated circuit chip |
| CN102184904A (en) * | 2011-04-12 | 2011-09-14 | 中颖电子股份有限公司 | Bonding disc structure aiming at BOAC frame and integrated circuit device structure |
| CN103000602A (en) * | 2011-09-12 | 2013-03-27 | 格罗方德半导体公司 | Strain-compensating fill patterns for controlling semiconductor chip package interactions |
| CN103000602B (en) * | 2011-09-12 | 2015-10-28 | 格罗方德半导体公司 | For controlling the interactional strain compensation filling pattern of semiconductor die package |
| CN105489581A (en) * | 2015-12-25 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and fabrication method thereof |
| CN105489581B (en) * | 2015-12-25 | 2018-06-29 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and preparation method thereof |
| CN108447837A (en) * | 2017-02-16 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices |
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| Publication number | Publication date |
|---|---|
| CN100399564C (en) | 2008-07-02 |
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