CN105489581A - Semiconductor structure and fabrication method thereof - Google Patents
Semiconductor structure and fabrication method thereof Download PDFInfo
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- CN105489581A CN105489581A CN201510996499.0A CN201510996499A CN105489581A CN 105489581 A CN105489581 A CN 105489581A CN 201510996499 A CN201510996499 A CN 201510996499A CN 105489581 A CN105489581 A CN 105489581A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
- H01L2224/02125—Reinforcing structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/03011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/03013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bonding area, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Abstract
The invention provides a semiconductor structure and a fabrication method thereof. A pseudo metal interconnection layer which is electrically insulated from a plurality of metal interconnection layers is formed when the plurality of metal interconnection layers are formed; the pseudo metal interconnection layer at least comprises a pseudo top metal pattern; the pseudo top metal pattern and a top metal pattern in the metal interconnection layers are located at the same layer; when a conductive plug is formed on the top metal pattern, a mesh metal support structure is formed on the pseudo top metal pattern; meshes of the mesh metal support structure are filled with a dielectric material; a welding pad is formed on the conductive plug and the mesh metal support structure; the welding pad comprises an edge region and an exposed central region; the edge region is covered by a passivation layer; the edge region of the welding pad is electrically connected with the metal interconnection layers; and the central region of the welding pad is supported by the mesh metal support structure. The dielectric material of which the mesh metal support structure is good in support effect and easy to crack is limited in the single mesh; and the crack is not amplified in the overall dielectric material due to the crack of the dielectric material in the single mesh, so that the chip reliability is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of semiconductor structure and preparation method thereof.
Background technology
In technical field of manufacturing semiconductors, integrated circuit (IC) encapsulation is a very important ring, and it is for provide electrical interconnection, mechanical support, machinery and environmental protection and passage of heat between chip and circuit board.Specifically, IC encapsulation is exactly utilize routing technique, weld pad (Pad) on chip draws bonding wire, and bonding wire is guided on the pin of package casing, these pins are connected with other devices by the wire on printed circuit board (PCB) again, thus realize the connection of inside chip and external circuit.
In recent years, along with the develop rapidly of semiconductor process techniques, the function of semiconductor chip is become stronger day by day, its pin number also increases thereupon, in order to meet the demand in market, there is wafer-level package (CSP) in chip encapsulation technology, and it is directly connected with circuit board with projection (Bumping) or tin ball (BallMount), owing to not needing the processing procedures such as routing, thus significantly decrease process costs.
But, no matter in bonding process, or projection or tin ball are directly connected in process, pressure welding strength (BondingForce) in prior art on weld pad is born by the interlayer dielectric layer (IMD) under it, this can cause interlayer dielectric layer to break (Crack), affects the reliability (Reliability) of chip under serious conditions.
Summary of the invention
The problem that the present invention solves how to provide a kind of semiconductor structure and preparation method thereof, avoids the interlayer dielectric layer under weld pad to break in pressure welding process, thus improve chip reliability.
For solving the problem, an aspect of of the present present invention provides a kind of semiconductor structure, comprising:
Semiconductor substrate, the surface of described Semiconductor substrate is formed with semiconductor device, described semiconductor device is formed with some layers of metal interconnecting layer;
Weld pad, is connected with the Portions of top layer metal pattern in described some layers of metal interconnecting layer, for being electrically connected with described semiconductor device by described some layers of metal interconnecting layer;
Wherein, described semiconductor structure also comprises:
With the pseudo-metal interconnecting layer of described some layers of metal interconnecting layer electric insulation, described pseudo-metal interconnecting layer at least comprises pseudo-top layer metal pattern, and the top-level metallic pattern in described pseudo-top layer metal pattern and described some layers of metal interconnecting layer is positioned at same layer; Described weld pad comprises the fringe region being passivated layer covering and the central area exposed by described passivation layer, the fringe region of described weld pad is electrically connected with the top-level metallic pattern in described metal interconnecting layer, between the central area of described weld pad and the pseudo-top layer metal pattern under it, there is net metal supporting construction, in the mesh of described net metal supporting construction, be filled with dielectric material.
Alternatively, described pseudo-metal interconnecting layer is equal with the number of plies of described metal interconnecting layer, is net metal supporting construction or multiple conductive plunger insulated by dielectric material between the pseudo-metal pattern of each layer of described pseudo-metal interconnecting layer and the pseudo-metal pattern under it.
Alternatively, the number of plies of described pseudo-metal interconnecting layer is less than the number of plies of described metal interconnecting layer, is part metals interconnection layer under described pseudo-metal interconnecting layer.
Alternatively, be net metal supporting construction or multiple conductive plunger insulated by dielectric material between the pseudo-metal pattern of each layer of described pseudo-metal interconnecting layer and the pseudo-metal pattern under it.
Alternatively, each width of mesh of described net metal supporting construction is equal, shape is identical.
Alternatively, each mesh of described net metal supporting construction is square, cross or circle.
Another aspect of the present invention provides a kind of manufacture method of semiconductor structure, comprising:
There is provided Semiconductor substrate, the surface of described Semiconductor substrate is formed with semiconductor device, and described semiconductor device is formed some layers of metal interconnecting layer, and the top layer of described some layers of metal interconnecting layer is top-level metallic pattern; When forming some layers of metal interconnecting layer, form the pseudo-metal interconnecting layer with described some layers of metal interconnecting layer electric insulation simultaneously, described pseudo-metal interconnecting layer at least comprises pseudo-top layer metal pattern, and the top-level metallic pattern in described pseudo-top layer metal pattern and described metal interconnecting layer is positioned at same layer;
Top-level metallic pattern and pseudo-top layer metal pattern form dielectric layer, and dielectric layer described in photoetching, dry etching forms the through hole exposing described top-level metallic pattern, and is positioned at multiple dielectric post of described pseudo-top layer metal pattern surface; In described through hole and between each dielectric post, insert metal, metal straight described in planarization is to the upper surface flush with described dielectric layer; The metal inserted in described through hole forms conductive plunger, and the metal inserted between described each dielectric post forms net metal supporting construction;
Form weld pad at described conductive plunger and net metal supporting construction upper surface, described weld pad is formed the passivation layer exposing weld pad central area, is net metal supporting construction under described weld pad central area.
Alternatively, when forming every layer of metal pattern, form every layer of pseudo-metal pattern in described pseudo-metal interconnecting layer simultaneously, described every layer of pseudo-metal pattern and every layer of metal pattern electric insulation, the conductive plunger formed between double layer of metal pattern forms net metal supporting construction between two-layer pseudo-metal pattern or multiple conductive plunger insulated by dielectric material simultaneously.
Alternatively, when forming the multiple layer metal pattern under top-level metallic pattern, form the pseudo-metal pattern of respective layer, described every layer of pseudo-metal pattern and every layer of metal pattern electric insulation simultaneously.
Alternatively, when forming the conductive plunger in the multiple layer metal pattern under top-level metallic pattern between double layer of metal pattern, form the net metal supporting construction between corresponding two-layer pseudo-metal pattern or multiple conductive plunger insulated by dielectric material simultaneously.
Compared with prior art, technical scheme of the present invention has the following advantages: 1) form the pseudo-metal interconnecting layer with this metal interconnecting layer electric insulation at formation multiple layer metal interconnection layer simultaneously, this pseudo-metal interconnecting layer at least comprises the pseudo-top layer metal pattern of one deck, and the top-level metallic pattern in this pseudo-top layer metal pattern and metal interconnecting layer is positioned at same layer; When top-level metallic pattern forms conductive plunger, pseudo-top layer metal pattern forms net metal supporting construction, in the mesh of this net metal supporting construction, is filled with dielectric material; Conductive plunger and net metal supporting construction form weld pad, this weld pad comprises fringe region that the passivation layer that formed by subsequent technique covers and the central area that this passivation layer exposes, side edges region is connected with top-level metallic pattern by conductive plunger, thus be electrically connected with metal interconnecting layer, weld pad central area is supported by net metal supporting construction.Net metal supporting construction is structure as a whole on the one hand, and thus support effect is good, and two aspects, owing to being formed on pseudo-top layer metal pattern, are not thus electrically connected with other device; The dielectric material easily broken in three aspects is limited in single mesh, can not break because of the dielectric material in single mesh, causes this crackle to amplify in full wafer dielectric material, improves chip reliability.
2) in possibility, a) pseudo-metal interconnecting layer can be equal with the number of plies of metal interconnecting layer, this kind of semiconductor structure is called non-circuit under pad (Non-CircuitUnderPad, Non-CUP), in such cases, can be net metal supporting construction between the pseudo-metal pattern of each layer of pseudo-metal interconnecting layer and the pseudo-metal pattern under it; Also can be multiple conductive plunger insulated by dielectric material; B) number of plies of pseudo-metal interconnecting layer can also be less than the number of plies of metal interconnecting layer, be metal interconnecting layer under pseudo-metal interconnecting layer, this kind of semiconductor structure is called circuit under pad (CircuitUnderPad, CUP), in such cases, can be net metal supporting construction between the pseudo-metal pattern of each layer of pseudo-metal interconnecting layer and the pseudo-metal pattern under it, also can be multiple conductive plunger insulated by dielectric material.
3), in possibility, each mesh of net metal supporting construction can be square, cross or circle, is easy to make.
Accompanying drawing explanation
Fig. 1 to Fig. 8 is the structural representation of semiconductor structure in each production phase of one embodiment of the invention;
Fig. 9 to Figure 10 is the structural representation of semiconductor structure in two production phases of another embodiment of the present invention;
Figure 11 to Figure 12 is the structural representation of semiconductor structure in two production phases of yet another embodiment of the invention.
Embodiment
As described in the background art, weld pad of the prior art easily causes the interlayer dielectric layer under it to break in pressure welding process, can affect the reliability of chip under serious conditions.Inventor by analysis, finds that its Producing reason is: the support of weld pad adopts conductive plunger, and conductive plunger is formed in interlayer dielectric layer.Interlayer dielectric layer is after breaking, and thus it break can be exaggerated owing to joining together, thus these interlayer dielectric layer insulation property are deteriorated, and affect reliability.
Based on above-mentioned analysis, the present invention adopts net metal supporting construction support pad, this net metal supporting construction is formed on the pseudo-metal interconnecting layer with other device electric insulation, and is limited in each mesh of net metal supporting construction by dielectric material, avoids above-mentioned integrity problem.In addition, above-mentioned net metal supporting construction is in weld pad central area support pad, and the conducting to be electrically connected with its fringe region by metal interconnect structure of weld pad is realized.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 1 to Fig. 8 is the structural representation of semiconductor structure in each production phase of one embodiment of the invention.Below in conjunction with Fig. 1 to Fig. 8, introduce semiconductor structure of an embodiment and preparation method thereof in detail.
First, with reference to shown in Fig. 1, provide Semiconductor substrate 10, the surface of Semiconductor substrate 10 is formed with semiconductor device (not shown), form some layers of metal interconnecting layer 11 on the semiconductor device, the top layer of some layers of metal interconnecting layer 11 is top-level metallic pattern 11a; When forming some layers of metal interconnecting layer 11, form the pseudo-metal interconnecting layer 12 with this some layers of metal interconnecting layer 11 electric insulation simultaneously, pseudo-metal interconnecting layer 12 comprises pseudo-top layer metal pattern 12a, and the top-level metallic pattern 11a in pseudo-top layer metal pattern 12a and metal interconnecting layer 11 is positioned at same layer.
Particularly, the material of semiconductor device substrate 10 can be silicon, germanium, silicon-on-insulator (SOI) etc.Semiconductor device is such as MOS transistor etc.With reference to shown in Fig. 1, the metal interconnecting layer 11 in the present embodiment is 7 layers, in other embodiment, also can be other number number of plies; Pseudo-metal interconnecting layer 12 only comprises pseudo-top layer metal pattern 12a.Top-level metallic pattern 11a in formation metal interconnecting layer 11 forms pseudo-top layer metal pattern 12a simultaneously.The material of top-level metallic pattern 11a, pseudo-top layer metal pattern 12a can be a) copper, and employing is filled out groove mode and formed; B) also can be aluminium, adopt photoetching, the formation of dry etching method.
The conductive plunger (sign) that metal interconnecting layer 11 comprises each layer metal pattern (sign) and is positioned on metal pattern.Interlayer dielectric layer (sign) is filled between each metal pattern, each conductive plunger.
Can find out in Fig. 1, pseudo-metal interconnecting layer 12 only comprises pseudo-top layer metal pattern 12a, and it is lower is part metals interconnection layer 11, and this kind of semiconductor structure is called circuit under pad (CircuitUnderPad, CUP).
Then, with reference to shown in Fig. 2, top-level metallic pattern 11a and pseudo-top layer metal pattern 12a form dielectric layer 13, and photoetching, dry etching dielectric layer 13 form the through hole 131 of exposed top layer metal pattern 11a, and are positioned at multiple dielectric post 132 on pseudo-top layer metal pattern 12a surface.
The material of dielectric layer 13 is such as silicon dioxide.After this step makes, in an embodiment, as shown in Figure 3, each dielectric post 132 shape size is consistent for the vertical view of pseudo-top layer metal pattern 12a, and cross section is circular.In another embodiment, as shown in Figure 4, the cross section of dielectric post 132 is cross to the vertical view of pseudo-top layer metal pattern 12a.In other embodiment, the cross section of each dielectric post 132 can also be other shape, and be such as square, the shape size of even each dielectric post 132 can be inconsistent, and each dielectric post 132 is discrete.
Afterwards, with reference to shown in Fig. 5, in through hole 131 and between each dielectric post 132, insert metal, this metal straight of planarization is to the upper surface flush with dielectric layer 13; The metal inserted in through hole 131 forms conductive plunger 141, and the metal inserted between each dielectric post 132 forms net metal supporting construction 142.As shown in Figure 6, the net metal supporting construction 142 formed after inserting metal between the dielectric post 132 shown in Fig. 4 as shown in Figure 7 for the net metal supporting construction 142 formed after inserting metal between dielectric post 132 shown in Fig. 3.Can find out, net metal supporting construction 142 is connected, and mesh is dielectric post 132.
In specific implementation process, can, by controlling dielectric post 132 size, the metallic member area occupied in net metal supporting construction 142 be made at least to be greater than the cross-sectional area summation of all dielectric post 132.
Afterwards, with reference to shown in Fig. 8, form weld pad 15 at conductive plunger 141 and net metal supporting construction 142 upper surface.The material of this weld pad 15 can be aluminium, and be specially deposition one deck aluminium lamination, rear employing photoetching, dry etching are formed.
Then, still with reference to shown in Fig. 8, weld pad 15 is formed the passivation layer 16 exposing weld pad central area 151, and weld pad central area is for 151 times net metal supporting construction 142.The electrical connection of weld pad 15 is realized by the conductive plunger 141 under fringe region 152 wherein.
Based on above-mentioned manufacture method, define a kind of semiconductor structure, with reference to shown in Fig. 8, this semiconductor structure comprises:
Semiconductor substrate 10, the surface of Semiconductor substrate 10 is formed with semiconductor device (not shown), this semiconductor device is formed with some layers of metal interconnecting layer 11;
With the pseudo-metal interconnecting layer 12 of some layers of metal interconnecting layer 11 electric insulation, pseudo-metal interconnecting layer 12 at least comprises pseudo-top layer metal pattern 12a, and the top-level metallic pattern 11a in pseudo-top layer metal pattern 12a and some layers of metal interconnecting layer 11 is positioned at same layer;
Weld pad 15, comprise and be passivated the fringe region 152 that layer 16 covers and the central area 151 being passivated layer 16 exposure, the fringe region 152 of weld pad is electrically connected with the top-level metallic pattern 11a in metal interconnecting layer 11, for being electrically connected with semiconductor device by some layers of metal interconnecting layer 11; Between weld pad central area 151 and the pseudo-top layer metal pattern 12a under it, there is net metal supporting construction 142, in the mesh of net metal supporting construction 142, be filled with dielectric material.
In above-mentioned semiconductor structure, the benefit of net metal supporting construction 142 is: 1) be structure as a whole, and thus support effect is good; 2) owing to being formed on pseudo-top layer metal pattern 12a, be not thus electrically connected with other device; 3) dielectric material easily broken is limited in single mesh, can not break because of the dielectric material in single mesh, causes this crackle to amplify in full wafer dielectric material, improves chip reliability.
Fig. 9 to Figure 10 is the structural representation of semiconductor structure in two production phases of another embodiment of the present invention.Composition graphs 9, with shown in Fig. 1, shown in Figure 10 and Fig. 8, can be found out, the pseudo-metal interconnecting layer 12 in the present embodiment, except comprising pseudo-top layer metal pattern 12a, also comprises the pseudo-metal pattern 12b of layer second from the bottom under it, the pseudo-metal pattern 12c of layer third from the bottom.Layer metal pattern 11c third from the bottom in the pseudo-metal pattern 12c of this layer third from the bottom and metal interconnecting layer 11 is formed in same operation; Layer metal pattern 11b second from the bottom in the pseudo-metal pattern 12b of layer second from the bottom and metal interconnecting layer 11 is formed in same operation.Making the conductive plunger on layer metal pattern 11c third from the bottom simultaneously, make the net metal supporting construction 17 on the pseudo-metal pattern 12c of layer third from the bottom, the manufacture method of this net metal supporting construction 17, referring to figs. 1 through the manufacture method of the net metal supporting construction 142 in Fig. 8 embodiment, is dielectric post in the mesh of net metal supporting construction 17.In other embodiment, this reticular supporting structure 17 also can replace with the conductive plunger in interlayer dielectric layer, as the conductive plunger on the layer metal pattern 11c third from the bottom of layer.Similarly, making the conductive plunger on layer metal pattern 11b second from the bottom simultaneously, make the net metal supporting construction 18 on the pseudo-metal pattern 12b of layer second from the bottom, the manufacture method of this net metal supporting construction 18, referring to figs. 1 through the manufacture method of the net metal supporting construction 142 in Fig. 8 embodiment, is dielectric post in the mesh of net metal supporting construction 18.In other embodiment, this net metal supporting construction 18 also can replace with the conductive plunger in interlayer dielectric layer, as the conductive plunger on the layer metal pattern 11b second from the bottom of layer.
In other embodiment, except three layers, the number of plies of pseudo-metal interconnecting layer 12 can be other number.
Figure 11 to Figure 12 is the structural representation of semiconductor structure in two production phases of yet another embodiment of the invention.In conjunction with shown in Figure 11 and Fig. 1, shown in Figure 12 and Fig. 8, can find out, the number of plies of the pseudo-metal interconnecting layer 12 in the present embodiment is equal with the number of plies of metal interconnecting layer 11, and namely the pseudo-metal pattern of each layer and metal pattern make in same operation.In conductive plunger manufacturing process on each layer metal pattern, made the net metal supporting construction on the pseudo-metal pattern of respective layer simultaneously.The manufacture method of this net metal supporting construction, referring to figs. 1 through the manufacture method of the net metal supporting construction 142 in Fig. 8 embodiment, is dielectric post in the mesh of each net metal supporting construction.In other embodiment, this net metal supporting construction also can replace with the conductive plunger in interlayer dielectric layer, as the conductive plunger on layer metal pattern.
With previous embodiment unlike, in semiconductor structure in Figure 12, its time of pseudo-metal interconnecting layer 12, without metal interconnecting layer, has conductive plunger although show in Figure 12 between the pseudo-metal pattern of ground floor and Semiconductor substrate 10, but this conductive plunger does not play electric action.In other words, this semiconductor structure is non-circuit under pad (Non-CircuitUnderPad, Non-CUP).
No matter semiconductor structure is circuit under pad, pseudo-metal interconnecting layer has how many layers, or be non-circuit under pad, due to pseudo-metal interconnecting layer and other device electric insulation, at least on pseudo-top layer metal pattern, form net metal supporting construction, weld pad center is supported, support effect is good on the one hand, on the other hand the dielectric material easily broken is limited in single mesh, can not break because of the dielectric material in single mesh, cause this crackle to amplify in full wafer dielectric material, improve chip reliability.Simultaneously conducting of weld pad still realizes by the connection between the side edges region that covers under passivation layer and metal interconnecting layer.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a semiconductor structure, comprising:
Semiconductor substrate, the surface of described Semiconductor substrate is formed with semiconductor device, described semiconductor device is formed with some layers of metal interconnecting layer;
Weld pad, is connected with the Portions of top layer metal pattern in described some layers of metal interconnecting layer, for being electrically connected with described semiconductor device by described some layers of metal interconnecting layer;
It is characterized in that, described semiconductor structure also comprises:
With the pseudo-metal interconnecting layer of described some layers of metal interconnecting layer electric insulation, described pseudo-metal interconnecting layer at least comprises pseudo-top layer metal pattern, and the top-level metallic pattern in described pseudo-top layer metal pattern and described some layers of metal interconnecting layer is positioned at same layer; Described weld pad comprises the fringe region being passivated layer covering and the central area exposed by described passivation layer, the fringe region of described weld pad is electrically connected with the top-level metallic pattern in described metal interconnecting layer, between the central area of described weld pad and the pseudo-top layer metal pattern under it, there is net metal supporting construction, in the mesh of described net metal supporting construction, be filled with dielectric material.
2. semiconductor structure according to claim 1, it is characterized in that, described pseudo-metal interconnecting layer is equal with the number of plies of described metal interconnecting layer, is net metal supporting construction or multiple conductive plunger insulated by dielectric material between the pseudo-metal pattern of each layer of described pseudo-metal interconnecting layer and the pseudo-metal pattern under it.
3. semiconductor structure according to claim 1, is characterized in that, the number of plies of described pseudo-metal interconnecting layer is less than the number of plies of described metal interconnecting layer, is part metals interconnection layer under described pseudo-metal interconnecting layer.
4. semiconductor structure according to claim 3, is characterized in that, is net metal supporting construction or multiple conductive plunger insulated by dielectric material between the pseudo-metal pattern of each layer of described pseudo-metal interconnecting layer and the pseudo-metal pattern under it.
5. semiconductor structure according to claim 1, is characterized in that, each width of mesh of described net metal supporting construction is equal, shape is identical.
6. semiconductor structure according to claim 5, is characterized in that, each mesh of described net metal supporting construction is square, cross or circle.
7. a manufacture method for semiconductor structure, is characterized in that, comprising:
There is provided Semiconductor substrate, the surface of described Semiconductor substrate is formed with semiconductor device, and described semiconductor device is formed some layers of metal interconnecting layer, and the top layer of described some layers of metal interconnecting layer is top-level metallic pattern; When forming some layers of metal interconnecting layer, form the pseudo-metal interconnecting layer with described some layers of metal interconnecting layer electric insulation simultaneously, described pseudo-metal interconnecting layer at least comprises pseudo-top layer metal pattern, and the top-level metallic pattern in described pseudo-top layer metal pattern and described metal interconnecting layer is positioned at same layer;
Top-level metallic pattern and pseudo-top layer metal pattern form dielectric layer, and dielectric layer described in photoetching, dry etching forms the through hole exposing described top-level metallic pattern, and is positioned at multiple dielectric post of described pseudo-top layer metal pattern surface; In described through hole and between each dielectric post, insert metal, metal straight described in planarization is to the upper surface flush with described dielectric layer; The metal inserted in described through hole forms conductive plunger, and the metal inserted between described each dielectric post forms net metal supporting construction;
Form weld pad at described conductive plunger and net metal supporting construction upper surface, described weld pad is formed the passivation layer exposing weld pad central area, is net metal supporting construction under described weld pad central area.
8. manufacture method according to claim 7, it is characterized in that, when forming every layer of metal pattern, form every layer of pseudo-metal pattern in described pseudo-metal interconnecting layer simultaneously, described every layer of pseudo-metal pattern and every layer of metal pattern electric insulation, the conductive plunger formed between double layer of metal pattern forms net metal supporting construction between two-layer pseudo-metal pattern or multiple conductive plunger insulated by dielectric material simultaneously.
9. manufacture method according to claim 7, is characterized in that, when forming the multiple layer metal pattern under top-level metallic pattern, forms the pseudo-metal pattern of respective layer, described every layer of pseudo-metal pattern and every layer of metal pattern electric insulation simultaneously.
10. manufacture method according to claim 9, it is characterized in that, when forming the conductive plunger in the multiple layer metal pattern under top-level metallic pattern between double layer of metal pattern, form the net metal supporting construction between corresponding two-layer pseudo-metal pattern or multiple conductive plunger insulated by dielectric material simultaneously.
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| CN109560119A (en) * | 2017-09-25 | 2019-04-02 | 新唐科技股份有限公司 | High voltage semiconductor element |
| CN117080163A (en) * | 2023-10-11 | 2023-11-17 | 芯耀辉科技有限公司 | Chip structure and forming method thereof, chip packaging structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106252313A (en) * | 2016-10-12 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | A kind of bond pad structure |
| CN106252313B (en) * | 2016-10-12 | 2018-12-11 | 上海华虹宏力半导体制造有限公司 | A kind of bond pad structure |
| CN109560119A (en) * | 2017-09-25 | 2019-04-02 | 新唐科技股份有限公司 | High voltage semiconductor element |
| CN109560119B (en) * | 2017-09-25 | 2021-11-16 | 新唐科技股份有限公司 | High voltage semiconductor element |
| CN117080163A (en) * | 2023-10-11 | 2023-11-17 | 芯耀辉科技有限公司 | Chip structure and forming method thereof, chip packaging structure and forming method thereof |
| CN117080163B (en) * | 2023-10-11 | 2024-02-23 | 芯耀辉科技有限公司 | Chip structure and forming method thereof, chip packaging structure and forming method thereof |
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| CN105489581B (en) | 2018-06-29 |
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