1247407 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體積體電路(integrated Circuit) 結構，尤指一種可進行主動電路正上方焊接(Wire bonding over active circuit，以下簡稱為BOAC)以及焊墊下方形成 有電容之積體電路結構。 【先前技術】 隨著半導體技術的進步以及積體電路的元件最小尺寸 不斷縮小，也使得單一晶片的體積越來越小。然而，此時 月欠佈在晶片周邊成排的轉接焊墊(bonding pad)卻成為晶片 體積進一步縮小的障礙。因為如熟習該項技藝者所知，一 般在轉接焊墊正下方的晶片區域是不容許佈設有主動電路 (active circuit)。這是由於晶片製造與設計者考量到當晶片 在進行打線焊接(bonding)時，須避免在轉接焊墊上所承受 的機械應力（mechanical stress)破壞到在轉接焊墊正下方的 積體電路。此外，目前功能性ic以及系統整合晶片（s〇c) 的需求越來越多，故如何解決晶片在進行打線焊接時，能 適當分散轉接焊墊上所承受的機械應力，同時能更有效應 1247407 用轉接焊塾下方之^間，以使轉接焊塾正下方的晶片區域 得以佈設主動電路或特定元件，俾使晶片體積得以進—步 縮小，業已成為當前晶片製造設計者努力的方向。 请參閱第1圖，第1圖為習知積體電路結構之上視圖。 積體電路晶片10中間為一核心區域12，其内部形成許多 主動電路元件’而積體電路晶片10表面周圍另配置有複數 個轉接焊墊14。其中，為了避免於轉接焊墊14進行打線 焊接(bonding)時，機械應力破壞轉接焊墊14下方的電路元 件’因此部份特定元件，例如電容16，係設置於各轉接焊 墊14與核心區域12之間。而為了解決習知積體電路晶片 10無法有效應用轉接焊墊下方空間之缺憾，韓國三星電子 股份有限公司（Samsung Electronics Ltd·)之美國專利第 6476459號，便揭露一種於焊墊下方形成電容之積體電路 結構’此電容結構為兩個不同電位之導體相重疊於不同平 面並且其中間具有一介電層，以構成一電容，進而改善轉 接焊墊下方的空間利用。 然而，美國專利第6476459號仍潛藏著支撐結構過於 薄弱以及製程步驟稍嫌繁瑣等缺點。因此，如何更妥呈利 用共平面之導體以形成電容，並同時強化積體電路進行打 1247407 ， 線焊接時之支撐結構，便為本發明所欲揭露之重點。 【發明内容】 本發明的主要目的在於提供一種B〇ac積體電路結 一 構，本發明之B〇AC積體電路結構具有至少一個由一對共 平面金屬電極所構成之金屬-金屬電容(metal-metal capacitor)，位於焊墊結構下方。 籲 根據本發明之目的，本發明之B0AC積體電路結構係 包3焊墊結構，此焊墊結構包含一可焊接金屬墊、一最 上層金屬内連線層、一設於可焊接金屬塾與最上層金屬内 連線層之間的緩衝介電層以及至少一第一介層插塞電連接 可焊接金屬塾與最上層金屬内連線層，此BOAC積體電路 〇構另外包合至少一金屬·金屬電容由至少一對共平面之❿ 金屬電極所構成’位於焊墊結構下方、至少一金屬内連線 層、至少一塗一人 一"層插塞電連接焊墊結構與金屬内連線層 _ 以及主動電路，設於焊魏構下方並位於—半導體底層 之上。 康本I明之目的，本發明更可形成多對兩兩共平面 8 1247407 之金屬電極彼此垂直堆疊以形成金屬-金屬電容。 由於本發明之金屬-金屬電容係由一對共平面之金屬 電極所構成，因此可利用一次標準銅鑲散(copper damascene)製程來製造，如此便能使製程簡化。另外本發 明可利用多對兩兩共平面之金屬電極彼此垂直堆疊以形成 金屬-金屬電容，所以可儲存大量之電荷於本發明之金屬-金屬電容中，另由於本發明之電容結構亦是一個良好的強 化支撐結構，可以保護其下方之主動電路。 為了使貴審查委員能更進一步了解本發明之特徵及 技術内容，請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與說明用，並非用來對本發明加以限 制者。 【實施方式】 請參閱第2圖，第2圖為依據本發明第一較佳實施例 之B0AC積體電路結構20剖面示意圖。如第2圖所示，本 發明之B0AC積體電路結構20包含有一焊墊結構22以及 一主動電路區域24。其中，焊墊結構22係為一增強 1247407 (reinforcement)結構，其包括有一可焊接金屬墊％、一最上 層金屬内連線層28、第一介層插塞30及32位於可焊接金 屬墊26下方並分別電連接可焊接金屬墊％與最上層金屬 内連線層28，以及一緩衝介電層36位於可焊接金屬墊％ 與最上層金屬内連線層28之間。 主動電路區域24包括有輸入/輸出（I/O)元件/線路或者 靜電保護(ESD)元件/線路，並且由複數個製作於半導體 底38表面上的金氧半導體電晶體元件40、42及44、、、土 隔離46及48、離子擴散區50、52、54、56及58、層間介 電層60、金屬層間介電層62、64、66及68、數居金屬 速線層7〇、72、74、76、78、80及82以及金屬_金屬電容 84等電子元件所構成。為方便說明，以下本發明之第—i 隹實施例以五層金屬内連線為例做說明，然而，熟習兮項i 技藝者應理解本發明之範疇不限於此，而係以申請專利= 圈中所述之範疇為準。本發明亦可應用於具有六、七層^ 更多層金屬内連線之積體電路中。 金屬内連線層70及72係定義於層間介電層6〇 、 以换觸插塞86與製作於半導體基底38表面上的金氣半導 艨電晶艨元件40、42及44、離子擴散區、52、μ、S6 1247407 及58電連接。其中層間介電層60可以為二氧化 # 玻璃（fluoride silicate glass，FSG)或其它低介電常數材料 根據本發明之較佳實施例，最上層金屬内連線層28與 、 金屬内連線層70、72、74、76、78、80及82係為銅金屬 -内連線’並以標準之銅鑲欲(copper damascene)製程製造。 例如，金屬内連線層74、76及78係以銅鑲嵌製程定義在 金屬層間介電層62中，而電連接金屬内連線層70與74之 ❿ 間的介層插塞88係以銅鑲嵌製程與金屬内連線層74、％ 及78同時形成在金屬層間介電層62中。金屬層間介電層 62由低介電常數或超低介電常數(uitra 1〇w_k)材料所構 成。此處’所謂超低介電常數材料係指介電常數小於2.5 之介電材質，其結構通常為多孔性且結構較為脆弱。 金屬内連線層80與金屬-金屬電容84係以銅鑲嵌製程定籲 義在金屬層間介電層64中，其中金屬-金屬電容84由一對 兩兩共平面且互相交錯之梳狀金屬電極89及91所形成。 為了使本發明之金屬-金屬電容的構造易於理解，請參閱第 3圖，第3圖為本發明b〇AC積體電路結構20之金屬-金 屬電容84立體示意圖，如第3圖所示，金屬_金屬電容84， 包含梳狀金屬陰極89與梳狀金屬陽極91係位於金屬層間 π 1247407 ., 介電層64中之同-平面上，因此可利用一次標準銅镶嵌製 程來製造，以簡化製程。 接著，請再參閱第2圖，電連接金屬内連線層78與8〇 . 之間的介層插塞90係以銅鑲嵌製程定義在金屬層間介電 - 層64中。金屬層間介電層64由低介電常數材料所構成。 金屬内連線層82係以銅鑲嵌製程定義在金屬層間介電層 66中，而電連接金屬-金屬電容84與金屬内連線層幻之間 _ 的介層插塞92、94、96與98係以銅鑲嵌製程與金屬内連 線層82同時形成在金屬層間介電層66中。其中，介層插 塞92與94係電連接一外部陰極（圖未示）與金屬_金屬電容 84之梳狀金屬陰極89,而介層插塞96與98係電連接一外 部陽極（圖未示）與金屬-金屬電容84之梳狀金屬陽極Μ。 此外，金屬層間介電層砧由低介電常數材料所構成 最上層金屬内連線層28係以銅鑲嵌製程定 金屬 間介電層68中，而位於可焊接金屬墊26被保 曰 /、咬增1〇〇覆 蓋的下方並且電連接最上層金屬内連線層28鱼 /、I屬内連 線層82之間的第二介層插塞1〇2、1〇4及1〇6 >係以銅鎮 嵌製程與最上層金屬内連線層28同時形成在金屬層門> 電層68中。金屬層間介電層68由低介電常數材料戶；， '所構成。 12 1247407 可焊接金屬墊26係覆蓋於緩衝介電層36上，而電連接 最上層金屬内連線層28與可焊接金屬墊％之間的第一介 層插基3G及32則係設在緩衝介電層％中。缓衝介電層 - 36疋由氧化石夕荨較無孔洞（kss p〇r〇us)或較為致密 (denser)之介電材料所構成’所以較各金屬層間介電層致 雄故可用來吸收焊接時所產生之應力。如前所述，本發 明之車乂佳實施中’可焊接金屬塾26與第一介層插塞如及鲁 32為銘金屬所構成，因此並非以銅鑲後製程製作，而是以 傳統之紹金屬導線製程製作’以相容於現行慣用之封裝製 程’然若能克服相關瓶頸技術’可焊接金屬塾％與第一介 層插塞3〇及32也可利用其他沉積金屬層並配合細等方 法製成。在本發明之B〇AC積體電路結構加的最上層為保 護層100,由例如氮化石夕、聚亞醯胺(p〇lyimide)或其它相等 之保護材料所製成，並且保護層100另具有一焊接開口， Φ 用以暴露出部分可详接金屬墊26之上表面而形成一焊接 窗口區域觸。而本發明之金屬-金屬電容84係位於焊接窗 口區域108下方。 氣 睛參閱第4圖，第4圖為依據本發明第二較佳實施例之 B〇AC積體電路結構剖面示意圖。第二較佳實施例與第一 13 1247407 較佳實施例的不同點在於本發明之金屬-金屬電容亦可由 被數對兩兩共平面之金屬電極彼此垂直堆疊所構成。 如第4圖所示，一 BOAC積體電路結構12〇，其包含 一主動電路區域122由形成於半導體基底124表面之金氧 半導體電晶體元件126、128及130、淺溝隔離132及134、 離子擴散區136、138、140、142及144、層間介電層146、 金屬層間介電層148、150、152及154、數層金屬内連線 層156、158、160、162及164以及金屬-金屬電容166與 168等電子元件所構成。同樣地，BOAC積體電路結構120 另包含一焊墊結構170，其包含有一可焊接金屬墊172、一 最上層金屬内連線層174、第一介層插塞176及178位於 可焊接金屬墊172下方，並且電連接可焊接金屬墊172與 最上層金屬内連線層174以及一緩衝介電層18〇位於可谭 接金屬墊172與最上層金屬内連線層174之間。另外第二 介層插塞182、184及186電連接最上層金屬内連線層 與金屬内連線層164，並位於覆蓋有保護層188之可烊接 金屬墊172的下方。 金屬-金屬電容166與168分別形成於金屬層間介電層 148與150中，其中金屬-金屬電容166係包含梳狀金屬陰 1247407 極190與梳狀金屬陽極192，金屬-金屬電容168係包含梳 狀金屬陰極194與梳狀金屬陽極196，其中梳狀金屬陰極 194係垂直堆疊於梳狀金屬陽極192正上方，同樣地，梳 狀金屬陽極196垂直堆疊於梳狀金屬陰極19〇正上方。因 -此，不但梳狀金屬陰極194、梳狀金屬陽極196與金屬層 - 間介電層150以及梳狀金屬陰極190、梳狀金屬陽極192 與金屬層間介電層148分別形成電容結構，而且本發明更 利用此種電路交錯配置的方式，而使梳狀金屬陰極19〇、 · 梳狀金屬陽極196與金屬層間介電層150以及梳狀金屬陰 極194、梳狀金屬陽極192與金屬層間介電層ι5〇再分別 形成電容結構，以加大電容面積。另外，本發明之b〇ac 積體電路結構可另包含一由銅金屬所製成之金屬框（圖未 不）’嵌於最上層金屬内連線層174下方之一金屬層間介電 (IMD)層與金屬-金屬電容168之間，例如金屬層間介電層 152中，用來作為-強化支撐結構，當緩衝介電層18〇吸 · 收焊接時所產生之應力，則可由此金屬框（圖未示）抵銷。 相較於習知技術，本發明之B〇AC積體電路結構具有 以下優點： 1·本發明之B〇AC積體電路結構之金屬-金屬電容配置於 可焊接金屬墊的下方，如此可以減少佈線的面積，大幅 15 1247407 縮小晶片之體積。 2·本發明之金屬_金屬電容係由一對共平面之金屬電極所 構成，因此可利用一次標準銅鑲嵌製程來製造，如此便 能使製程簡化。 3·本發明係利用多對兩兩共平面之金屬電極彼此垂直堆 疊以形成金屬-金屬電容，可儲存大量之電荷於本發明之 金屬-金屬電容中。 4·本發明之電容結構亦是一個良好的強化支撐結構，可以 保護其下方之主動電路。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知積體電路結構之上視圖。 第2圖為依據本發明第一較佳實施例之B〇AC積體電路結 構剖面示意圖。 第3圖為本發明B0AC積體電路結構之金屬_金屬電容立體 示意圖。 第4圖為依據本發明第二較佳實施例之b〇ac積體電路結 構剖面不意圖。 1247407 【主要元件符號說明】 10 積體電路晶片 12 核心區域 14 轉接焊墊 16 電容 20 BOAC積體電路結構 22 焊墊結構 24 主動電路區域 26 可焊接金屬墊 28 最上層金屬内連線層 30 第一介層插塞 32 第一介層插塞 36 緩衝介電層 38 半導體基底 40 金氧半導體電晶體元件 42 金氧半導體電晶體元件 44 金氧半導體電晶體元件 46 淺溝隔離 48 淺溝隔離 50 離子擴散區 52 離子擴散區 54 離子擴散區 56 離子擴散區 58 離子擴散區 60 層間介電層 62 金屬層間介電層 64 金屬層間介電層 66 金屬層間介電層 68 金屬層間介電層 70 金屬内連線層 72 金屬内連線層 74 金屬内連線層 76 金屬内連線層 78 金屬内連線層 80 金屬内連線層 82 金屬内連線層 84 金屬-金屬電容 86 接觸插塞 88 介層插塞 1247407 89 梳狀金屬陰極 91 梳狀金屬陽極 90 介層插塞 92 介層插塞 94 介層插塞 96 介層插塞 98 介層插塞 100 保護層 102 第二介層插塞 104 第二介層插塞 106 第二介層插塞 108 焊接窗口區域 120 BOAC積體電路結構 122 主動電路區域 124 半導體基底 126 金氧半導體電晶體元件 128 金氧半導體電晶體元件 130 金氧半導體電晶體元件 132 淺溝隔離 134 淺溝隔離 136 離子擴散區 138 離子擴散區 140 離子擴散區 142 離子擴散區 144 離子擴散區 146 層間介電層 148 金屬層間介電層 150 金屬層間介電層 152 金屬層間介電層 154 金屬層間介電層 156 金屬内連線層 158 金屬内連線層 160 金屬内連線層 162 金屬内連線層 164 金屬内連線層 166 金屬-金屬電容 168 金屬-金屬電容 170 焊墊結構 172 可焊接金屬墊 174 最上層金屬内連線層 176 第一介層插塞 178 第一介層插塞 1247407 180 緩衝介電層 182 第二介層插塞 184 第二介層插塞 186 第二介層插塞 188 保護層 190 梳狀金屬陰極 192 梳狀金屬陽極 194 梳狀金屬陰極 196 梳狀金屬陽極1247407 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor integrated circuit structure, and more particularly to a wire bonding over active circuit (hereinafter referred to as BOAC). And an integrated circuit structure in which a capacitor is formed under the pad. [Prior Art] As semiconductor technology advances and the minimum size of components of integrated circuits continues to shrink, the volume of a single wafer is becoming smaller and smaller. However, at this time, the bonding pad, which is arranged in a row around the wafer, becomes an obstacle to further shrinking the volume of the wafer. As is known to those skilled in the art, the area of the wafer directly below the transfer pads is generally not allowed to be provided with an active circuit. This is due to wafer fabrication and designer considerations. When the wafer is being bonded, it is necessary to avoid the mechanical stress on the adapter pad being destroyed to the integrated circuit directly under the adapter pad. . In addition, there is an increasing demand for functional ic and system integrated wafers (s〇c). Therefore, how to solve the problem that the wafer can properly disperse the mechanical stress on the adapter pad during wire bonding and can be more effective. 1247407 Using the lower part of the soldering pad to enable the active circuit or specific components to be placed on the wafer area directly under the soldering pad, so that the chip volume can be further reduced, which has become the direction of current chip manufacturing designers. . Please refer to FIG. 1 , which is a top view of a conventional integrated circuit structure. In the middle of the integrated circuit wafer 10 is a core region 12 in which a plurality of active circuit elements are formed, and a plurality of transfer pads 14 are disposed around the surface of the integrated circuit wafer 10. In order to avoid the bonding of the transfer pads 14 , the mechanical stress damages the circuit components under the transfer pads 14 so that some specific components, such as the capacitors 16 , are disposed on the respective pads 14 . Between the core area 12. In order to solve the problem that the conventional integrated circuit chip 10 cannot effectively use the space under the transfer pad, U.S. Patent No. 6,476,459 of Samsung Electronics Co., Ltd. discloses a capacitance formed under the pad. Integral circuit structure 'This capacitor structure is a conductor with two different potentials overlapping the different planes and having a dielectric layer in between to form a capacitor, thereby improving the space utilization under the adapter pad. However, U.S. Patent No. 6,476,459 still has the disadvantages that the support structure is too weak and the process steps are somewhat cumbersome. Therefore, how to more properly use the coplanar conductor to form the capacitor, and at the same time strengthen the integrated circuit to perform 1247407, the support structure during wire bonding, is the focus of the present invention. SUMMARY OF THE INVENTION The main object of the present invention is to provide a B〇ac integrated circuit structure, the B〇AC integrated circuit structure of the present invention has at least one metal-metal capacitor composed of a pair of coplanar metal electrodes ( Metal-metal capacitor, located below the pad structure. According to the purpose of the present invention, the BOAC integrated circuit structure of the present invention is a pad structure comprising a solderable metal pad, an uppermost metal interconnect layer, and a solderable metal layer. a buffer dielectric layer between the uppermost metal interconnect layers and at least one first via plug electrically connecting the solderable metal germanium and the uppermost metal interconnect layer, the BOAC integrated circuit structure additionally including at least one The metal/metal capacitor is composed of at least one pair of coplanar ❿ metal electrodes 'below the solder pad structure, at least one metal interconnect layer, at least one coated one" layer plug electrical connection pad structure and metal interconnect The line layer _ and the active circuit are disposed below the solder structure and on the semiconductor underlayer. For the purpose of Kang Benyi, the present invention can form a plurality of pairs of two-two coplanar electrodes. The metal electrodes of 8 1247407 are vertically stacked on each other to form a metal-metal capacitor. Since the metal-metal capacitor of the present invention is composed of a pair of coplanar metal electrodes, it can be fabricated by a standard copper damascene process, which simplifies the process. In addition, the present invention can utilize multiple pairs of bi-planar metal electrodes stacked vertically to form a metal-metal capacitor, so that a large amount of charge can be stored in the metal-metal capacitor of the present invention, and the capacitor structure of the present invention is also a A good reinforced support structure protects the active circuitry beneath it. In order to provide a more detailed understanding of the features and technical aspects of the present invention, the following detailed description of the invention and the accompanying drawings. The drawings are for illustrative purposes only and are not intended to limit the invention. [Embodiment] Please refer to Fig. 2, which is a cross-sectional view showing a structure of a BO integrated circuit structure 20 according to a first preferred embodiment of the present invention. As shown in FIG. 2, the BOAC integrated circuit structure 20 of the present invention includes a pad structure 22 and an active circuit region 24. The pad structure 22 is a reinforced 1247407 (reinforcement) structure including a solderable metal pad%, an uppermost metal interconnect layer 28, and first via plugs 30 and 32 located on the solderable metal pad 26. The solderable metal pad % and the uppermost metal interconnect layer 28 are electrically connected below and respectively, and a buffer dielectric layer 36 is located between the solderable metal pad % and the uppermost metal interconnect layer 28. The active circuit region 24 includes input/output (I/O) components/lines or electrostatic protection (ESD) components/lines, and is composed of a plurality of MOS transistor components 40, 42 and 44 fabricated on the surface of the semiconductor substrate 38. , , and soil isolation 46 and 48, ion diffusion regions 50, 52, 54, 56 and 58, interlayer dielectric layer 60, inter-metal dielectric layers 62, 64, 66 and 68, and plurality of metal velocity layers 7 72, 74, 76, 78, 80 and 82 and metal_metal capacitor 84 and other electronic components. For convenience of description, the following first embodiment of the present invention is described by taking a five-layer metal interconnection as an example. However, those skilled in the art should understand that the scope of the present invention is not limited thereto, and is applied for a patent = The categories stated in the circle shall prevail. The invention can also be applied to an integrated circuit having six or seven layers of metal interconnects. The metal interconnect layers 70 and 72 are defined by an interlayer dielectric layer 6 〇, a contact plug 86, and gold gas semiconducting silicon germanium elements 40, 42 and 44 fabricated on the surface of the semiconductor substrate 38, and ion diffusion. Zones, 52, μ, S6 1247407 and 58 are electrically connected. The interlayer dielectric layer 60 may be a fluoride silicate glass (FSG) or other low dielectric constant material. According to a preferred embodiment of the present invention, the uppermost metal interconnect layer 28 and the metal interconnect layer 70, 72, 74, 76, 78, 80 and 82 are copper metal-interconnects' and are manufactured in a standard copper damascene process. For example, the metal interconnect layers 74, 76, and 78 are defined in the inter-metal dielectric layer 62 by a copper damascene process, and the via plugs 88 electrically connected between the metal interconnect layers 70 and 74 are copper. The damascene process and metal interconnect layers 74, %, and 78 are simultaneously formed in the inter-metal dielectric layer 62. The inter-metal dielectric layer 62 is composed of a low dielectric constant or an ultra-low dielectric constant (uitra 1 〇 w_k) material. Here, the term "ultra-low dielectric constant material" means a dielectric material having a dielectric constant of less than 2.5, and its structure is generally porous and relatively fragile. The metal interconnect layer 80 and the metal-metal capacitor 84 are defined in the inter-metal dielectric layer 64 by a copper damascene process, wherein the metal-metal capacitor 84 is a pair of two-to-two co-planar and interdigitated comb-shaped metal electrodes. Formed by 89 and 91. In order to make the structure of the metal-metal capacitor of the present invention easy to understand, please refer to FIG. 3, which is a perspective view of the metal-metal capacitor 84 of the b〇AC integrated circuit structure 20 of the present invention, as shown in FIG. The metal-metal capacitor 84, comprising a comb-shaped metal cathode 89 and a comb-shaped metal anode 91, is located between the metal layers π 1247407. The dielectric layer 64 is on the same plane, and thus can be fabricated by using a standard copper damascene process to simplify Process. Next, referring to FIG. 2, the interlayer plug 90 electrically connected between the metal interconnect layers 78 and 8 is defined by the copper damascene process in the inter-metal dielectric-layer 64. The metal interlayer dielectric layer 64 is composed of a low dielectric constant material. The metal interconnect layer 82 is defined in the inter-metal dielectric layer 66 by a copper damascene process, and the via plugs 92, 94, 96 are electrically connected between the metal-metal capacitor 84 and the metal interconnect layer. The 98 series is formed in the inter-metal dielectric layer 66 by a copper damascene process and a metal interconnect layer 82. The interlayer plugs 92 and 94 are electrically connected to an external cathode (not shown) and a comb-shaped metal cathode 89 of the metal-metal capacitor 84, and the via plugs 96 and 98 are electrically connected to an external anode (not shown). Shown with a metal-metal capacitor 84 comb metal anode. In addition, the inter-metal dielectric interlayer anvil is composed of a low dielectric constant material, and the uppermost metal interconnect layer 28 is formed in the copper damascene process inter-metal dielectric layer 68, and the solderable metal pad 26 is protected. The second layer plugs 1〇2, 1〇4, and 1〇6 > between the uppermost metal interconnect layer 28 fish/ and the I inner interconnect layer 82 are electrically connected. The copper bonding process and the uppermost metal interconnect layer 28 are simultaneously formed in the metal layer gate > the electrical layer 68. The inter-metal dielectric layer 68 is composed of a low dielectric constant material; 12 1247407 solderable metal pad 26 is overlying the buffer dielectric layer 36, and the first via interposer 3G and 32 electrically connected between the uppermost metal interconnect layer 28 and the solderable metal pad % is Buffer dielectric layer %. The buffer dielectric layer - 36 疋 is composed of a oxidized stone 荨 荨 荨 ks ks ks ks ks ks ks ks ' 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以 所以Absorb the stress generated during welding. As described above, in the rut implementation of the present invention, the 'weldable metal crucible 26 and the first interlayer plug, such as the Lu 32, are made of metal, and therefore are not made by a copper inlay process, but are conventional. The manufacturing process of the metal wire is 'compatible with the current custom packaging process'. However, if the relevant bottleneck technology can be overcome, the solderable metal 塾% and the first interlayer plugs 3〇 and 32 can also be used with other deposited metal layers and fine Made by other methods. The uppermost layer added to the B〇AC integrated circuit structure of the present invention is a protective layer 100 made of, for example, nitride nitride, p〇lyimide or other equivalent protective material, and the protective layer 100 Having a soldering opening, Φ is used to expose a portion of the surface of the metal pad 26 to form a solder window area contact. The metal-to-metal capacitor 84 of the present invention is located below the soldering window region 108. 4 is a cross-sectional view showing a structure of a B〇AC integrated circuit according to a second preferred embodiment of the present invention. The second preferred embodiment differs from the preferred embodiment of the first 13 1247407 in that the metal-metal capacitor of the present invention may also be formed by vertically stacking a plurality of pairs of coplanar metal electrodes. As shown in FIG. 4, a BOAC integrated circuit structure 12A includes an active circuit region 122 formed of MOS transistors 126, 128 and 130, shallow trench isolations 132 and 134 formed on the surface of the semiconductor substrate 124, Ion diffusion regions 136, 138, 140, 142 and 144, interlayer dielectric layer 146, inter-metal dielectric layers 148, 150, 152 and 154, several metal interconnect layers 156, 158, 160, 162 and 164 and metal - Electronic components such as metal capacitors 166 and 168. Similarly, the BOAC integrated circuit structure 120 further includes a pad structure 170 including a solderable metal pad 172, an uppermost metal interconnect layer 174, and first via plugs 176 and 178 on the solderable metal pad. Below the 172, and electrically connected solderable metal pads 172 and uppermost metal interconnect layer 174 and a buffer dielectric layer 18 are located between the tantalum metal pad 172 and the uppermost metal interconnect layer 174. In addition, the second via plugs 182, 184 and 186 are electrically connected to the uppermost metal interconnect layer and the metal interconnect layer 164 and are located under the splicable metal pad 172 covered with the protective layer 188. The metal-metal capacitors 166 and 168 are respectively formed in the inter-metal dielectric layers 148 and 150, wherein the metal-metal capacitor 166 comprises a comb-shaped metal cathode 1247407 pole 190 and a comb-shaped metal anode 192, and the metal-metal capacitor 168 comprises a comb. The metal cathode 194 and the comb-shaped metal anode 196, wherein the comb-shaped metal cathode 194 are vertically stacked directly above the comb-shaped metal anode 192, likewise, the comb-shaped metal anode 196 is vertically stacked directly above the comb-shaped metal cathode 19'. Therefore, not only the comb-shaped metal cathode 194, the comb-shaped metal anode 196 and the metal-interlayer dielectric layer 150 and the comb-shaped metal cathode 190, the comb-shaped metal anode 192 and the inter-metal dielectric layer 148 form a capacitor structure, respectively. The present invention further utilizes the manner in which the circuits are staggered, such that the comb-shaped metal cathode 19, the comb-shaped metal anode 196 and the inter-metal dielectric layer 150, and the comb-shaped metal cathode 194, the comb-shaped metal anode 192, and the metal layer are interposed. The electrical layer ι5〇 separately forms a capacitor structure to increase the capacitance area. In addition, the b〇ac integrated circuit structure of the present invention may further comprise a metal frame made of copper metal (not shown) embedded in the metal interlayer between the uppermost metal interconnect layer 174 (IMD). Between the layer and the metal-metal capacitor 168, for example, the inter-metal dielectric layer 152, used as a reinforced support structure, when the buffer dielectric layer 18 is sucked and collected, the stress can be generated by the metal frame Offset (not shown). Compared with the prior art, the B〇AC integrated circuit structure of the present invention has the following advantages: 1. The metal-metal capacitor of the B〇AC integrated circuit structure of the present invention is disposed under the solderable metal pad, thereby reducing The area of the wiring is substantially 15 1247407 to reduce the size of the wafer. 2. The metal-metal capacitor of the present invention is composed of a pair of coplanar metal electrodes and can therefore be fabricated using a standard copper damascene process, which simplifies the process. 3. The present invention utilizes a plurality of pairs of bi-planar metal electrodes stacked vertically to form a metal-to-metal capacitor, which can store a large amount of charge in the metal-metal capacitor of the present invention. 4. The capacitor structure of the present invention is also a good reinforced support structure that protects the active circuitry beneath it. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. [Simple description of the drawing] Fig. 1 is a top view of a conventional integrated circuit structure. Fig. 2 is a cross-sectional view showing the structure of a B〇AC integrated circuit according to a first preferred embodiment of the present invention. Fig. 3 is a perspective view showing the metal-metal capacitor of the B0AC integrated circuit structure of the present invention. Fig. 4 is a cross-sectional view showing the structure of a b〇ac integrated circuit in accordance with a second preferred embodiment of the present invention. 1247407 [Description of main component symbols] 10 Integrated circuit chip 12 Core area 14 Adapter pad 16 Capacitor 20 BOAC integrated circuit structure 22 Pad structure 24 Active circuit area 26 Solderable metal pad 28 Uppermost metal interconnect layer 30 First via plug 32 First via plug 36 Buffer dielectric layer 38 Semiconductor substrate 40 Gold oxide semiconductor transistor component 42 Gold oxide semiconductor transistor component 44 Gold oxide semiconductor transistor component 46 Shallow trench isolation 48 Shallow trench isolation 50 ion diffusion region 52 ion diffusion region 54 ion diffusion region 56 ion diffusion region 58 ion diffusion region 60 interlayer dielectric layer 62 inter-metal dielectric layer 64 inter-metal dielectric layer 66 inter-metal dielectric layer 68 inter-metal dielectric layer 70 Metal interconnect layer 72 metal interconnect layer 74 metal interconnect layer 76 metal interconnect layer 78 metal interconnect layer 80 metal interconnect layer 82 metal interconnect layer 84 metal-metal capacitor 86 contact plug 88 Interlayer plug 1247407 89 Comb metal cathode 91 Comb metal anode 90 Interlayer plug 92 Interlayer plug 94 Interlayer plug 96 Interlayer plug 98 Layer plug 100 protective layer 102 second via plug 104 second via plug 106 second via plug 108 solder window region 120 BOAC integrated circuit structure 122 active circuit region 124 semiconductor substrate 126 MOS transistor Component 128 MOS transistor component 130 MOS transistor transistor element 132 shallow trench isolation 134 shallow trench isolation 136 ion diffusion region 138 ion diffusion region 140 ion diffusion region 142 ion diffusion region 144 ion diffusion region 146 interlayer dielectric layer 148 metal Interlayer dielectric layer 150 Intermetal dielectric layer 152 Intermetal dielectric layer 154 Interlayer dielectric layer 156 Metal interconnect layer 158 Metal interconnect layer 160 Metal interconnect layer 162 Metal interconnect layer 164 Metal interconnect Line layer 166 metal-metal capacitor 168 metal-metal capacitor 170 pad structure 172 solderable metal pad 174 uppermost metal interconnect layer 176 first via plug 178 first via plug 1247407 180 buffer dielectric layer 182 Second via plug 184 second via plug 186 second via plug 188 protective layer 190 comb metal cathode 192 comb gold Comb anode 194 cathode metal comb metal anode 196
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