KR20110050957A - Through via contact in semiconductor device and method of forming the same - Google Patents

Through via contact in semiconductor device and method of forming the same Download PDF

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KR20110050957A
KR20110050957A KR1020090107570A KR20090107570A KR20110050957A KR 20110050957 A KR20110050957 A KR 20110050957A KR 1020090107570 A KR1020090107570 A KR 1020090107570A KR 20090107570 A KR20090107570 A KR 20090107570A KR 20110050957 A KR20110050957 A KR 20110050957A
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South Korea
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pattern
conductive
via
via hole
buffer
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KR1020090107570A
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Korean (ko)
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박병률
안상훈
이종명
임동찬
최길현
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삼성전자주식회사
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Publication of KR20110050957A publication Critical patent/KR20110050957A/en

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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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Abstract

PURPOSE: A via contact passing through a semiconductor device and a manufacturing method thereof are provided to suppress the thermal expansion of first and second conductive patterns included in the via contact by including a buffer pattern. CONSTITUTION: A via hole(14) which passes through an interlayer insulation layer(12) and is extended to the lower side of a substrate(10) is formed on a substrate. A first conductive pattern(18a) is formed along the sidewall and the lower side of the via hole. A buffer pattern(22a) is formed on the first conductive pattern. A second conductive pattern(28a) covers the upper side of the buffer pattern. A capping layer(29) is formed on the first and second conductive patterns to protect the first and second conductive patterns.

Description

Through via contact in semiconductor device and method of forming The same

The present invention relates to a through via contact of a semiconductor device and a method of forming the same. More specifically, it relates to a via contact penetrating through a substrate and a method of forming the same.

As semiconductor devices are highly integrated and large in capacity, three-dimensional package technology for stacking individual chips is being developed. Among these, through silicon via contact technology is a package technology that forms a via hole through a substrate and forms an electrode in the via hole as a technology to replace a conventional wire bonding technology.

However, when the conductive material filled in the via hole is expanded by heat, the upper portion of the through-silicon via contact may protrude irregularly from the surroundings, and the protruding height is also very high, such as several micrometers. When the upper surface of the through silicon via contact protrudes, a problem may occur such that the upper thin films covering the through silicon via contact are lifted or cracked. This lowers the reliability of the semiconductor device including the through silicon via contact.

It is an object of the present invention to provide a through via contact having a flat top surface without protruding portions.

Another object of the present invention is to provide a method of forming a through via contact as described above.

Another object of the present invention is to provide a semiconductor device including the through via contact described above.

Another object of the present invention is to provide a method for manufacturing the semiconductor device.

Through-via contact according to an embodiment of the present invention for achieving the above object is provided with a substrate including a via hole. A first conductive pattern is provided along sidewalls and bottom surfaces of the via holes. A buffer pattern in which only a portion of the inside of the via hole is filled is provided on the first conductive pattern. And a second conductive pattern covering the upper surface of the buffer pattern in the via hole.

In one embodiment of the present invention, a first barrier metal film pattern may be provided between the first conductive pattern and the buffer pattern.

In one embodiment of the present invention, a second barrier metal film pattern may be provided along the lower surface of the second conductive pattern.

In one embodiment of the present invention, the buffer pattern may include a material having a lower coefficient of thermal expansion than the first conductive pattern. The buffer pattern may include a silicon material, an oxide, or a metal material.

In an embodiment of the present invention, semiconductor circuit patterns may be provided on the substrate. In addition, a lower interlayer insulating layer may be provided to cover the circuit patterns.

The via hole may have a shape extending downward from an upper surface of the lower interlayer insulating layer.

A capping layer covering the lower interlayer insulating layer, the second conductive pattern, and the first conductive pattern may be provided.

In one embodiment of the present invention, the first and second conductive patterns may include copper.

In one embodiment of the present invention, the via hole may have a depth of 10 to 100㎛.

In the method of forming a through via contact according to an embodiment of the present invention for achieving the above object, the substrate is etched to form a via hole extending below the surface of the substrate. A first conductive layer is formed along sidewalls and bottom surfaces of the via holes. A buffer pattern is formed on the first conductive layer to partially fill the via hole. A second conductive layer filling the via hole is formed on the buffer pattern. In addition, upper surfaces of the first and second conductive layers are removed to expose the upper portion of the via hole, thereby forming first and second conductive layer patterns provided in the via hole.

 In one embodiment of the present invention, in order to form the buffer pattern, a buffer film filling the via hole is formed on the first conductive film. Next, a portion of the buffer film is removed to have a height lower than that of the upper surface of the via hole.

In an embodiment of the present disclosure, a process of forming semiconductor circuit patterns on the substrate and a process of forming a lower interlayer insulating layer covering the circuit patterns may be further performed.

In addition, a capping layer and an upper interlayer insulating layer may be formed on the lower interlayer insulating layer and the first and second conductive patterns.

In an embodiment of the present invention, the first and second conductive patterns may be formed, and then a subsequent process performed at a temperature of 400 ° C. or more may be performed.

In an embodiment, a separation insulating layer may be formed on the sidewalls and the bottom of the via hole to insulate the via hole from the first conductive layer.

In one embodiment of the present invention, a first barrier metal film may be formed on the surface of the first conductive film.

In one embodiment of the present invention, a second barrier metal film may be formed on the upper surface of the buffer pattern and the first conductive layer positioned higher than the buffer pattern. In addition, a seed layer may be formed on the second barrier metal layer.

In accordance with another aspect of the present invention, a semiconductor device includes a first substrate including a via hole having a penetrating shape. First circuit pattern structures are provided on the first substrate. Second circuit pattern structures including a pad electrode are provided on the second substrate. A first conductive pattern having a cylinder shape covering the sidewall of the via hole and the bottom portion of the via hole and having the cylindrical bottom portion contacting the upper surface of the pad electrode is provided. A buffer pattern in which only a portion of the inside of the via hole is filled is provided on the first conductive pattern. A second conductive pattern is disposed on the buffer pattern to contact the first conductive pattern and cover the upper portion of the via hole.

In another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein first circuit pattern structures are formed on a first preliminary substrate. A via hole extends below the first circuit pattern structures and the first preliminary substrate surface. A through via including a first conductive pattern provided along the sidewalls and the bottom surface of the via hole in the via hole, a buffer pattern partially filled in the via hole on the first conductive pattern, and a second conductive pattern covering an upper surface of the buffer pattern Form a contact. The first preliminary substrate is polished to expose the bottom surface of the through via contact to form a first substrate. Second circuit pattern structures including a pad electrode are formed on the second substrate. In addition, the first and second substrates are bonded to contact the pad electrode and the first conductive pattern of the through via contact.

The through silicon via contact according to the present invention has a low coefficient of thermal expansion of some of the material filled in the via holes. Therefore, the problem that the top surface of the through silicon via contact is protruded by the thermal expansion is reduced, thereby reducing the process defects caused. In addition, the semiconductor device including the through silicon via contact has high reliability.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the drawings of the present invention, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, each layer (film), region, electrode, pattern or structures is formed on, "on" or "bottom" of the object, substrate, each layer (film), region, electrode or pattern. When referred to as being meant that each layer (film), region, electrode, pattern or structure is formed directly over or below the substrate, each layer (film), region or patterns, or other layer (film) Other regions, different electrodes, different patterns, or different structures may be additionally formed on the object or the substrate.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

That is, the present invention may be modified in various ways and may have various forms. Specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Through Via Contact

1A is a cross-sectional view illustrating a through via contact according to an embodiment of the present invention. FIG. 1B is a perspective view illustrating the through via contact illustrated in FIG. 1A.

1A and 1B, circuit patterns (not shown) are provided on the substrate 10. The substrate 10 may be a substrate made of a semiconductor material. For example, the substrate 10 may be a single crystal silicon substrate. The circuit patterns include semiconductor unit devices. For example, the circuit patterns may include a transistor, a diode, and the like. An interlayer insulating layer 12 covering the circuit patterns is provided on the substrate.

In the interlayer insulating layer 12 and the substrate 10, a via hole 14 penetrating the interlayer insulating layer 12 and extending below the surface of the substrate 10 is formed. The depth h1 of the via hole 14 is 10 to 100 μm. Preferably, the via hole 14 has a depth of 30 to 60㎛. In addition, the diameter of the via hole 14 is 5 to 30㎛, preferably 10 to 20㎛.

An insulating layer pattern 16a is provided along the sidewalls and the bottom profile of the via hole 14. The insulating layer pattern 16a insulates the conductive material between the substrate 10 and the via hole 14. It is preferable that the insulating film pattern 16a is made of silicon oxide.

A first barrier metal film pattern (not shown) is provided on the insulating film pattern 16a. The first barrier metal film pattern may be formed of a material such as Ta, TaN, Ti, TiN, Ru, Co, or the like. These may be used alone or in combination of two or more.

A first seed pattern (not shown) may be provided on the first barrier metal layer pattern. However, the first seed pattern may not be provided depending on the type of metal material formed in the via hole 14 and the method of forming the metal material.

The first conductive pattern 18a is disposed on the first barrier metal layer pattern along the sidewalls and the bottom profile of the via hole 14. That is, the conductive pattern 18a has a cylindrical shape. Since the first conductive pattern 18a must have a low resistance, the first conductive pattern 18a may be formed of a metal material. For example, the first conductive pattern 18a may be made of copper (Cu).

The second barrier metal film pattern 20a is provided on an upper surface of the first conductive pattern 18a. The second barrier metal layer pattern 20a may be formed of a material such as Ta, TaN, Ti, TiN, Ru, Co, or the like. These may be used alone or in combination of two or more. The second barrier metal layer pattern 20a prevents a reaction between the first conductive pattern 18a and the buffer pattern 22a filled in the via hole 14.

However, depending on the material used as the first conductive pattern 18a and the buffer pattern 22a, the reaction between the first conductive pattern 18a and the buffer pattern 22a may hardly occur. In this case, the second barrier metal film pattern 20a may not be provided.

A buffer pattern 22a is formed on the first conductive pattern 18a to fill only a portion of the inside of the via hole 14. That is, the buffer pattern 22a has a shape that fills the central portion of the via hole 14.

The buffer pattern 22a mitigates a mismatch in thermal expansion coefficient between silicon (Si) constituting a substrate and the first conductive pattern 18a, so that the first conductive pattern 18a thermally expands to protrude upward. Suppresses Therefore, the buffer pattern 22a includes a material having a lower coefficient of thermal expansion than the first conductive pattern 18a. Specifically, the buffer pattern 22a is preferably made of a material having a coefficient of thermal expansion of 16.7 × 10 −6 / ° C. or less at room temperature. In addition, the buffer pattern 22a preferably includes a material having a property of decreasing volume when heat is applied. The buffer pattern 22a may be made of a conductive material or an insulating material. Examples of the material that may be used as the buffer pattern 22a include spin-on glass (SOG) -based oxides, flowable silicon, titanium, aluminum, porous materials, and the like.

As the height of the buffer pattern 22a increases, the height h2 of the second conductive pattern 28a positioned on the buffer pattern 22a decreases. When the height h2 of the second conductive pattern 28a is reduced, the problem that the first and second conductive patterns 18a and 28a protrude above the interlayer insulating layer 12 is reduced. Therefore, in order to alleviate the problem that the top surface of the through via contact 60 protrudes, the height of the buffer pattern should be increased. However, if the height of the buffer pattern 22a is excessively increased, the thickness of the second conductive pattern 28a may be relatively low, thereby increasing the resistance of the through via contact 60.

Therefore, the height of the buffer pattern 22a is preferably higher than 50% of the total depth h1 of the via hole 14. In addition, the depth h2 of the inside of the via hole 14 when the buffer pattern 22a is formed is preferably smaller than 20 μm.

A third barrier metal layer pattern 26a and a second seed pattern (not shown) are provided on an upper surface of the buffer pattern 22a and sidewalls of the first conductive pattern 18a. The third barrier metal layer pattern 26a may be formed of a material such as Ta, TaN, Ti, TiN, Ru, Co, or the like. These may be used alone or in combination of two or more. The third barrier metal layer pattern 26a prevents a reaction between the buffer pattern 22a and the second conductive pattern 28a.

Depending on the material used as the buffer pattern 22a and the second conductive pattern 28a, the reaction between the buffer pattern 22a and the second conductive pattern 28a may hardly occur. In this case, the third barrier metal film pattern 26a may not be provided.

A second conductive pattern 28a is provided on the second seed pattern. The second conductive pattern 28a may be made of the same material as the first conductive pattern 18a. The second conductive pattern 28a is provided in the via hole 14, and the upper surface of the second conductive pattern 28a and the upper surface of the via hole 14 are flat to each other.

A capping layer 29 may be provided on the first conductive pattern 18a, the second conductive pattern 28a, and the interlayer insulating layer 12 to protect the first and second conductive patterns 18a and 28a. have. The capping layer 29 may be made of silicon nitride.

The through via contact 60 according to the present exemplary embodiment has a shape in which a sidewall, a bottom surface, and an upper surface of the via hole 14 are surrounded by the first conductive pattern 18a and the second conductive pattern 28a. In addition, a buffer pattern 22a is provided at the center of the through via contact 60.

As such, by including a buffer pattern in the through via contact, thermal expansion of the first and second conductive patterns included in the through via contact may be suppressed. Therefore, the first and second conductive patterns protrude higher than the upper surface of the interlayer insulating film, thereby preventing problems such as lifting, breaking, or cracking of the capping film.

2 through 8 are cross-sectional views illustrating a method of forming the through via contact shown in FIGS. 1A and 1B.

Referring to FIG. 2, circuit patterns (not shown) are formed on the substrate 10. In addition, an interlayer insulating layer 12 covering the circuit patterns is formed on the substrate 10. For example, the substrate 10 may perform front-end-of-line (FEOL) CMOS processes.

A photoresist film (not shown) is formed on the interlayer insulating film 12, and the photoresist film is patterned to form a photoresist pattern. The photoresist pattern may have a thickness of about 2 to 5㎛.

The interlayer insulating layer 12 and the substrate 10 are dry etched using the photoresist pattern as an etching mask. As a result, the via hole 14 penetrates the interlayer insulating layer 12 and extends below the surface of the substrate 10. Through via contacts are formed in the via holes 14 through a subsequent process.

If the depth of the via hole 14 is smaller than 10 μm, the depth of the through via contact is too small, making it difficult to manufacture a stacked semiconductor device. In addition, when the depth of the via hole 14 is greater than 100 μm, it is not easy to fill a conductive material in the via hole 14. Therefore, the via hole 14 has a depth of 10 to 100 mu m, and preferably has a depth of 30 to 60 mu m.

When the diameter of the via hole 14 is smaller than 5 μm, it is not easy to fill the conductive material in the via hole 14. In addition, when the diameter of the via hole 14 is 30 μm, the horizontal area occupied by the via hole 14 is increased, which is not preferable. Therefore, the via hole 14 has a diameter of 5 to 30 μm, preferably 10 to 20 μm.

After the via hole 14 is formed, the photoresist pattern is removed.

Referring to FIG. 3, the insulating layer 16 is formed along the profile of the sidewalls and the bottom surface of the via hole 14. The insulating layer 16 insulates the conductive material in the substrate 10 and the via hole 14. The insulating layer 16 may be formed to a thickness of 1 to 3㎛.

A first barrier metal film (not shown) is formed on the insulating film 16. The first barrier metal film may be formed of a material such as Ta, TaN, Ti, TiN, Ru, Co, or the like. The first barrier metal film may be formed to a thickness of 100 to 3000 kPa.

A first seed layer (not shown) is formed on the first barrier metal layer. The first seed film is a film used as an electrode in a plating process for forming a subsequent first conductive film. In the present embodiment, the first seed layer may be formed by depositing copper through physical vapor deposition.

A first conductive layer 18 is formed on the first seed layer along sidewalls and a bottom profile of the via hole 14. By adjusting the thickness of the first conductive layer 18, the resistance of the through via contact may be adjusted. The first conductive film 18 is formed of a low resistance metal material. In the present embodiment, the first conductive film 18 is formed by depositing copper by electroplating.

Referring to FIG. 4, a second barrier metal film 20 is formed on the first conductive film 18. The second barrier metal film 20 may be formed of a material such as Ta, TaN, Ti, TiN, Ru, Co, or the like. The second barrier metal film 20 may be formed to a thickness of 100 to 3000 kPa.

Referring to FIG. 5, a buffer layer 22 is formed on the second barrier metal layer 20 so as to completely fill the via hole 14. The buffer layer 22 may include a material having a lower coefficient of thermal expansion than the first conductive layer 18. The buffer film 22 is preferably made of a material having a characteristic that the volume is reduced when heat is applied. The buffer layer 22 may include silicon, silicon oxide, or a metal material. In addition, the buffer layer 22 should be filled without voids in the via hole 14 having a high aspect ratio. Therefore, the buffer film 22 should be formed of a material having excellent gap filling properties. Examples of the material that can be used as the buffer layer 22 include spin-on-glass oxides, flowable silicon, titanium, aluminum, porous materials, and the like.

Referring to FIG. 6, the buffer layer 22 is etched to form a buffer pattern 22a in the inside of the via hole 14. The buffer layer 22 may be etched by an anisotropic etching process or an isotropic etching process. The buffer pattern 22a should be formed to have a lower upper surface than the upper surface of the interlayer insulating layer 12.

The buffer pattern 22a preferably has a height higher than 50% of the total depth of the via hole 14. In addition, it is preferable that the depth of the inside of the via hole 14 in the state where the buffer pattern 22a is formed is smaller than 20 μm.

Referring to FIG. 7, a third barrier metal layer 26 is formed on the buffer pattern 22a and the second barrier metal layer 20 exposed on the buffer pattern 22a. The third barrier metal layer 26 may be formed of a material such as Ta, TaN, Ti, TiN, Ru, Co, or the like. The third barrier metal film 26 may be formed to a thickness of 100 to 3000 kPa.

A second seed layer (not shown) is formed on the third barrier metal layer 26. In the present embodiment, the second seed layer may be formed by depositing copper through physical vapor deposition.

Referring to FIG. 8, a second conductive layer 28 is formed on the second seed layer to completely fill the via hole 14. The second conductive film 28 is preferably formed of the same material as the first conductive film 18. In the present embodiment, the second conductive film 28 is formed by depositing copper by electroplating.

Referring back to FIG. 1, the second conductive layer 28, the first conductive layer 18, and the first to third barrier metal layers 20 and 26 are exposed to expose the upper surface of the interlayer insulating layer 12. Is polished through a chemical mechanical polishing process. Through the above process, the first conductive pattern 18a, the second conductive pattern 28a, the first barrier metal film pattern, the second barrier metal film pattern 20a, the third barrier metal film pattern 26a, and the insulating film pattern The through via contact 60 including the 16a and the buffer pattern 22a is completed. Thereafter, a capping layer 29 is formed to cover the interlayer insulating layer 12, the first and second conductive patterns 18a and 28a, and the second and third barrier metal layer patterns 20a and 26a. The capping layer 29 includes silicon nitride.

Unlike the present embodiment, the through via contact (see FIG. 14) having a general structure has a shape in which copper is filled in the entire via hole. When a high temperature process of 400 ° C. or more is performed on the through via contact having the general structure, copper filled in the through via contact protrudes to 0.5 μm or more. In addition, since the horizontal area of the protruding portion is the same as the diameter of the via hole, a problem of protruding by an area of several μm to lift thin films formed on the through via contact occurs.

However, the buffer via 22a is included in the through via contact 60 according to the present exemplary embodiment, thereby reducing thermal expansion of the first conductive pattern 18a. Therefore, even if a high temperature process of 400 ° C. or more is subsequently performed, the problem of protruding the top surface of the through via contact 60 may be reduced.

In addition, as the height of the conductive material filled in the through via contact 60 increases, the height at which the conductive material protrudes by a subsequent heat treatment process increases. However, the second conductive pattern 28a of the through via contact 60 according to the present exemplary embodiment has a height which is very low compared to the depth of the via hole 14. Therefore, the height at which the second conductive pattern 28a thermally expands and protrudes through a subsequent heat treatment process is reduced.

Therefore, according to the present exemplary embodiment, the upper surface of the through via contact may protrude, thereby effectively reducing a problem such as lifting or breaking of the upper layer positioned on the through via contact.

Semiconductor device

9 is a cross-sectional view illustrating a stacked semiconductor device according to an exemplary embodiment of the present invention.

The stacked semiconductor device includes a through via contact.

Referring to FIG. 9, the stacked semiconductor device includes a first semiconductor chip 50, a second semiconductor chip 150, and a contact member 110.

The first semiconductor chip 50 may include a first substrate 10a, circuit patterns 30, wires 32, and first interlayer insulating layers 34 provided on the first substrate 10a. A through via contact 60a penetrating through the first substrate 10a and a first pad electrode 42 electrically connected to the through via contact 60a are included.

The circuit patterns 30 may include a transistor, a diode, and the like. The wires 32 may include a contact, a pad, a conductive line, and the like. The device included in the first semiconductor chip 50 may be a memory device or a logic device. As another example, the device included in the first semiconductor chip 50 may be an image device.

The first substrate 10a may be a single crystal silicon substrate. The first substrate 10a has a thickness of 10 to 100 μm. The bottom surface of the first substrate 10a may be positioned on the same plane as the bottom surface of the through via contact 60a or lower than the bottom surface of the through via contact 60a.

Hereinafter, the through via contact penetrating the first substrate 10a will be described.

A via hole 14 extending from the top surface of the first substrate 10a to the bottom surface and penetrating the first substrate 10a is provided. The via hole 14 has a diameter of 5 to 30 μm, preferably 10 to 20 μm.

A separator pattern 16b is provided on a sidewall of the via hole 14. The separator pattern 16b is not provided on the bottom surface of the via hole 14. That is, the separator pattern 16b has a cylindrical shape with upper and lower surfaces open. A first barrier metal layer pattern (not shown) and a first seed pattern (not shown) are provided on the separator pattern 16b.

A cylindrical first conductive pattern 18a covering the sidewalls of the via holes 14 and the bottom surface of the via holes 14 is provided on the first seed pattern. That is, the bottom surface of the via hole 14 is blocked by the bottom surface of the cylindrical first conductive pattern 18a. That is, the bottom surface of the first conductive pattern 18a may be positioned on the same plane as the bottom surface of the first substrate 10a or protrude through the bottom surface of the first substrate 10a. Therefore, the bottom surface of the first conductive pattern 18a is exposed through the bottom surface of the first substrate 10a. The first conductive pattern 18a may be made of a metal material. For example, the first conductive pattern 18a may be made of copper.

The second barrier metal film pattern 20a is disposed on an upper surface of the first conductive pattern 18a. A buffer pattern 22a filling only a portion of the inside of the via hole 14 is provided on the second barrier metal layer pattern 20a. The buffer pattern 22a may have the same configuration as described with reference to FIGS. 1A and 1B.

A third barrier metal layer pattern 26a and a second seed pattern (not shown) are disposed on an upper surface of the buffer pattern 22a and sidewalls of the first conductive pattern 18a. In addition, a second conductive pattern 28a filling the via hole 14 is provided on the second seed pattern.

As described above, a through via contact 60a is provided in the via hole 14 penetrating the substrate. That is, in the through via contact 60a according to the present exemplary embodiment, the separation pattern 16a is not provided on the bottom of the via hole 14, except that the bottom surface of the first conductive pattern 18a is exposed. Is the same as the through via contact shown in FIGS. 1A and 1B.

A capping layer 36 is provided on the through via contact 60a and the first interlayer insulating layer 34 positioned at the top thereof. The capping layer 36 prevents diffusion of metal included in the through via contact 60a and protects the through via contact 60a. In addition, the capping layer 36 serves as an etch stop layer. The capping layer 36 may be made of silicon nitride.

An upper interlayer insulating layer 38 is provided on the capping layer 36. A contact plug 40 penetrates the upper interlayer insulating layer 38 and the capping layer 36 and contacts the upper surface of the through via contact 60a.

The first pad electrode 42 may be provided on the contact plug 40 to which a signal is applied from the outside. A first passivation layer pattern 44 is provided on the upper interlayer insulating layer 38 and the first pad electrode 42. The first passivation layer pattern 44 may be made of a polyimide material. In this case, the first passivation layer pattern 44 is not formed at a portion where the electrical connection is made in the first pad electrode 42. Although not shown, the first pad electrode 42 may be in contact with the printed circuit board or electrically connected to the lead frame by wire bonding.

Meanwhile, the second semiconductor chip 150 may include a second substrate 100, circuit patterns 102, wirings 104, second interlayer insulating layers 106, and the like provided on the second substrate 100. And a second pad electrode 108 to which a signal is applied through the through via contact 60a.

The semiconductor device included in the second semiconductor chip 150 may be the same semiconductor device as that included in the first semiconductor chip 50 or may be different semiconductor devices.

As illustrated, the second interlayer insulating layer 106 formed on the uppermost portion is provided with a second pad electrode 108 connected to the lower interconnections 104. The second pad electrode 108 is bonded to and electrically connected to the bottom surface of the through via contact 60a of the first substrate 10a.

The second passivation layer pattern 109 is disposed on the uppermost second interlayer insulating layer 106 and the second pad electrode 108. The second passivation pattern 109 may be made of a polyimide material. In this case, the second passivation layer pattern 109 is not provided at a portion of the second pad electrode 108 that contacts the through via contact 60a.

A conductive contact member 110 is interposed between the through via contact 60a included in the first semiconductor chip 50 and the second pad electrode 108 included in the second semiconductor chip 150. The through via contact 60a and the second pad electrode 108 are bonded to each other by the contact member 110. Examples of the material that can be used as the contact member include silver (Ag) solder paste.

That is, the semiconductor device according to the present exemplary embodiment has a structure in which first and second chips are stacked, and the first and second chips are electrically connected through through via contacts. In addition, the stacked device according to the present exemplary embodiment includes a through via contact having excellent thermal stability, thereby having high reliability.

10 to 14 are cross-sectional views illustrating a method of manufacturing the stacked semiconductor device illustrated in FIG. 9.

Referring to FIG. 10, circuit patterns 30, wires 32, and first interlayer insulating layers 34 are formed on the preliminary first substrate 9. In addition, a preliminary through via contact 59 penetrates through the first interlayer insulating layers 34 and extends below the preliminary first substrate 9. The preliminary through via contact 59 has the same structure as the through via contact of the first embodiment and is formed through the same method as the through via contact forming method of the first embodiment.

Referring to FIG. 11, a capping layer 36 covering the uppermost first interlayer insulating layer 34 and the preliminary through via contact 59 is formed. The capping layer 36 may be formed to a thickness of 300 to 1000 kPa.

An upper interlayer insulating layer 38 is formed on the capping layer 36. The upper interlayer insulating layer 38 may be formed of one layer or two or more layers.

The preliminary through via contact 59 includes a buffer pattern 22a, so that the preliminary through via contact 59 hardly protrudes upward. Therefore, the capping layer 36 and the upper interlayer insulating layer 38 covering the preliminary through via contact 59 may be normally formed without being lifted or broken.

Referring to FIG. 12, a portion of the upper interlayer insulating layer 38 and the capping layer 36 is etched to form a contact hole exposing an upper surface of the preliminary through via contact 59. Subsequently, a contact plug 40 is formed in the contact hole by filling and planarizing a conductive material in the contact hole. The conductive material includes a metal having low resistance.

The first pad electrode 42 is formed on the upper interlayer insulating layer 38 while contacting the contact plug 40. The first pad electrode 42 may be formed by forming and patterning a metal material having low resistance.

A first passivation layer (not shown) is formed to cover the first pad electrode 42 and the upper interlayer insulating layer 38. Next, the first passivation layer disposed on the upper surface of the portion where the signal is applied from the first pad electrode 42 is removed to form the first passivation layer pattern 44.

Referring to FIG. 13, the bottom surface of the preliminary first substrate 9 is ground and removed to expose the first conductive pattern 18a on the bottom surface. Through the above process, the first substrate 10a and the through via contact 60a are formed.

Specifically, the preliminary first substrate 9 is ground such that the distance between the bottom of the preliminary through via contact 59 and the bottom of the preliminary first substrate 9 is close to several μm. Subsequently, the preliminary first substrate 9 is etched to expose the insulating layer pattern 16a on the bottom surface of the preliminary through via contact 59. Next, the insulating layer pattern 16a exposed on the bottom surface and the preliminary first substrate 9 are etched together to form a first substrate 10a through which the first conductive pattern 18a is exposed.

When the polishing and etching processes are performed, the bottom surface of the insulating layer pattern 16a included in the preliminary through via contact 59 is removed to form a separation layer pattern 16b surrounding the inner wall of the via hole 14. As a result, the through via contact 60a including the separator pattern 16b is formed.

On the other hand, in order to reduce the overall thickness of the stacked device, it is preferable that the height of the preliminary through via contact 60a is lowered. However, as the height of the preliminary through via contact 60a is lowered, the thickness of the preliminary first substrate 9 to be removed through the grinding and etching increases. Therefore, the height of the preliminary through via contact 60a should be set in consideration of substrate grinding process deviation and the like.

Referring to FIG. 14, circuit patterns 102, wires 104, and second interlayer insulating layers 106 are formed on the second substrate 100.

A second pad electrode 108 is formed on the second interlayer insulating layer 106 to be electrically connected to the wires 104. The second pad electrode 108 is disposed to face the through via contact 60a formed in the first substrate 10a, respectively.

A second passivation layer (not shown) is formed to cover the second pad electrode 108 and the uppermost second interlayer insulating layer 106. Next, the second passivation layer 109 is formed by removing the second passivation layer on the upper surface of the portion where the signal is applied from the second pad electrode 108.

Referring to FIG. 9 again, the conductive contact member 110 is formed on the second pad electrode 108 of the second substrate 100 and then formed on the contact member 110 and the first substrate. The bottom portions of the through via contacts 60a are in contact with each other and compressed. As a result, as shown in FIG. 9, the stacked semiconductor device in which the first semiconductor chip 50 and the second semiconductor chip 150 are stacked is completed.

15 illustrates a through via contact of a general structure.

Referring to FIG. 15, an insulating layer pattern 51 and a barrier metal layer pattern (not shown) are provided on sidewalls and a bottom surface of the via hole, and a copper pattern 52 is provided to completely fill the via hole on the barrier metal layer pattern. do. The capping layer 54 and the upper interlayer insulating layer 56 are provided on the through via contact 70 and the interlayer insulating layer 12.

Copper extrusion experiment

Comparative Samples 1 through 3 of through via contacts having the structure shown in FIG. 15 were prepared. The comparative samples 1 to 3 have different through via contact depths d1, and the diameters are the same. The ratio of the depth and diameter of the comparative samples 1 to 3 is as follows.

 Diameter: Depth Comparison sample 1  2: 1.7 Comparison sample 2  2: 4.3 Comparison sample 3  2: 5.0

Comparative samples 1 to 3 prepared above were each heat-treated at a temperature of 450 ° C. for 30 minutes. Thereafter, in Comparative Samples 1 to 3, the height d2 at which the copper pattern protrudes over the interlayer insulating film was confirmed.

FIG. 16 is a graph showing the height at which the copper pattern protrudes in each of the comparative samples. FIG.

As shown in FIG. 16, it can be seen that as the depth of the copper filling in the through via contact hole increases, the height of the copper pattern protruding increases linearly.

That is, through the copper protrusion test, it was found that by lowering the effective height of the copper pattern to reduce the depth of the copper filling, it is possible to reduce the height of the copper pattern protruding.

Hypothetical comparison experiment

A through via contact sample was prepared according to one embodiment of the present invention having the structure shown in FIG. 1.

The through via contact of Sample 1 was formed through the same process as described with reference to FIGS. 2 to 8.

Specifically, the via hole was formed in a size of 20 μm in diameter and 50 μm in depth. The first conductive pattern was formed by depositing 5 μm thick copper in the via hole and subsequent polishing. The buffer pattern was formed by depositing an SOG-based oxide and then etching it to a thickness of about 35 μm. The second conductive pattern was formed by depositing 5 μm thick copper on the buffer pattern and subsequent polishing. The second conductive pattern was to have a thickness of 10 μm.

The prepared sample was heat treated at a temperature of 450 ° C. for 30 minutes.

In the sample after the heat treatment, the height at which the first and second conductive patterns protrude above the interlayer insulating film was simulated.

In the case of the prepared sample, the thickness of the second conductive pattern was substantially only 10 μm, and the copper film was filled to a depth of 10 μm to form the second conductive pattern. Therefore, the protruding thickness of the copper pattern after the heat treatment can be judged to be the same height as that derived when the copper film is filled to a depth of 10 μm. Therefore, the protrusion thickness of the copper pattern after the said heat processing was calculated to be about 2 micrometers.

As described above, in the through via contact sample according to one embodiment of the present invention having a diameter of 20 μm and a depth of 50 μm, the protruding thickness of the copper pattern after heat treatment is about 2 μm. On the other hand, in Comparative Sample 3 of the through via contact having a size of 20 mu m in diameter and 50 mu m in depth, the protruding thickness of the copper pattern after heat treatment was about 0.9 mu m.

As such, when the through via contact having the same size is formed, the through via contact according to the exemplary embodiment of the present invention has been found to have a significantly reduced protruding thickness compared to the conventional through via contact.

As described above, the through via contact according to the present invention can be used when manufacturing a stacked semiconductor device. The through via contact of the present invention can be applied to manufacturing various semiconductor devices, that is, memory devices, logic devices, image sensors, and the like. In particular, the through via contact of the present invention can be used when designing and manufacturing semiconductor devices having high integration, high speed operation, and low power consumption and high reliability.

1A is a cross-sectional view illustrating a through via contact according to an embodiment of the present invention.

FIG. 1B is a perspective view illustrating the through via contact illustrated in FIG. 1A.

2 through 8 are cross-sectional views illustrating a method of forming the through via contact shown in FIGS. 1A and 1B.

9 is a cross-sectional view illustrating a stacked semiconductor device according to an exemplary embodiment of the present invention.

10 to 14 are cross-sectional views illustrating a method of manufacturing the stacked semiconductor device illustrated in FIG. 9.

15 illustrates a through via contact of a general structure.

FIG. 16 is a graph showing the height at which the copper pattern protrudes in each of the comparative samples. FIG.

Claims (10)

  1. A substrate including via holes;
    A first conductive pattern provided along sidewalls and bottom surfaces of the via holes;
    A buffer pattern provided on the first conductive pattern and filling only a part of the inside of the via hole; And
    The through via contact of the semiconductor device including a second conductive pattern covering the upper surface of the buffer pattern in the via hole.
  2. The through via contact of claim 1, wherein a first barrier metal layer pattern is provided between the first conductive pattern and the buffer pattern.
  3. The through via contact of claim 1, wherein a second barrier film metal film pattern is provided along a lower surface of the second conductive pattern.
  4. The through via contact of claim 1, wherein the buffer pattern comprises a material having a lower coefficient of thermal expansion than the first conductive pattern.
  5. The through via contact of claim 1, wherein semiconductor circuit patterns are provided on the substrate, and a lower interlayer insulating layer covering the circuit patterns is provided.
  6. The through via contact of claim 5, wherein the via hole extends downward from an upper surface of the lower interlayer insulating layer.
  7. The semiconductor device of claim 6, wherein a capping layer covering the lower interlayer insulating layer, the second conductive pattern, and the first conductive pattern is provided.
  8. Etching the substrate to form via holes extending below the substrate surface;
    Forming a first conductive film along sidewalls and bottom surfaces of the via holes;
    Forming a buffer pattern on the first conductive layer to fill only a portion of the inside of the via hole;
    Forming a second conductive layer filling the via hole on the buffer pattern; And
    And removing the upper surfaces of the first and second conductive layers to expose the upper portion of the via holes, thereby forming first and second conductive layer patterns provided in the via holes. Forming method.
  9. The method of claim 8, wherein the forming of the buffer pattern comprises:
    Forming a buffer film filling the via hole on the first conductive film; And
    Removing a portion of the buffer layer to have a height lower than that of the upper surface of the via hole.
  10. The method of claim 8,
    Forming semiconductor circuit patterns on the substrate; And
    And forming a lower interlayer insulating layer covering the circuit patterns.
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