CN104779238B - A kind of detection structure and detection method of wafer bond quality - Google Patents
A kind of detection structure and detection method of wafer bond quality Download PDFInfo
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- CN104779238B CN104779238B CN201410012656.5A CN201410012656A CN104779238B CN 104779238 B CN104779238 B CN 104779238B CN 201410012656 A CN201410012656 A CN 201410012656A CN 104779238 B CN104779238 B CN 104779238B
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Abstract
The present invention relates to a kind of detection structures and detection method of wafer bond quality, in the detection structure, bottom wafers pass through bottom metal layers, bottom land and positioned between the two bottom through-hole formed interconnection architecture, lower half portion as the test structure, top pads and metal layer at top described in the wafer of top and form interconnection architecture positioned at top through-hole between the two, top half as test structure, the metal layer at top is as testing weld pad, after top wafer is thinned, testing weld pad is opened in the metal layer at top of top wafer.Test structure is made of 3 parts, the test structure of the left and right sides is respectively the first test target and the second test target, intermediate structure mainly plays lead, test structure is symmetrical structure, make in access that other extra resistances are equal other than test target, test structure kind of the present invention is simple and effective, and solving the problems, such as that Cu Cu engage resistance Rc in 3D IC cannot accurately test.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of detection structure of wafer bond quality and inspection
Survey method.
Background technology
In consumer electronics field, multifunctional equipment is increasingly liked by consumer, compared to the simple equipment of function,
Multifunctional equipment manufacturing process will be more complicated, for example need to integrate the chip of multiple and different functions in circuit version, thus go out
3D integrated circuits are showed（Integrated circuit, IC）Technology, 3D integrated circuits（Integrated circuit, IC）Quilt
It is defined as a kind of system-level integrated morphology, multiple chips are stacked in vertical plane direction, to save space, each chip
Marginal portion can draw multiple pins as needed, utilize these pins as needed, it would be desirable to the chip of interconnection
It is interconnected by metal wire, but aforesaid way still has many deficiencies, for example stacked chips quantity is more, and between chip
Connection relation it is more complicated, then just may require that using a plurality of metal wire, final wire laying mode is more chaotic, Er Qiehui
Volume is caused to increase.
3D IC be by the processor chip of former bare crystalline size, programmable logic lock (FPGA) chip, memory chip,
RF chip (RF) or optoelectronic wafers directly overlap after thinning, and through TSV drilling connections.Skill is overlapped in 3D IC solids
Art, under the assistance of key technologies/encapsulation spare part such as silicon hole (TSV), intermediate plate (Interposer), in limited areal into
The maximum chip superposition of row and integration, further reduce SoC chip areas/encapsulation volume and promote chip communication efficiency.
Therefore, the Cu-Cu engagements in wafer level（Wafer level Cu-Cu bonding）As one in 3DIC
Key technology is also in development phase at present, and how effective on-line checking engages（bonding）Quality and yield, how
It is accurate to measure engagement resistance（Rbonding）, it is the emphasis researched and developed at present.Especially answering on the high-end products such as 3D CIS
With the density of engagement is very high（One pixel needs at least one engagement-bonding）, effectively simply online test method is aobvious
It must be even more important.
Cu-Cu engagements in wafer current level（wafer level Cu-Cu bonding）Quality testing mainly adopt
With traditional resistance chain（Rc chain）Mode test, as shown in Figure 1, but traditional resistance chain（Rc chain）In test
Rc contain joint（bonding）, metal layer metal, through-hole（Via）Resistance value, Rc=Rbonding+RVia+Rmetal, and just
Normal engagement（bonding）The ratio that the resistance value brought accounts in Rc is smaller, only works as bond quality（bonding quality）
Engagement can be qualitatively reflected when poor（bonding）Quality, be unable to accurately measure engagement（bonding）
The contact resistance of itself can not accurately reflect engagement（bonding）Quality.
Although existing in the prior art to the Cu-Cu engagements in wafer level（wafer level Cu-Cubonding）'s
The detection structure of quality testing, but there are still various deficiencies, how effective on-line checking engages（bonding）Quality and
How yield accurately measures engagement resistance RbondingThe problem of as present urgent need to resolve.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
The present invention is in order to overcome the problems, such as that presently, there are provide a kind of detection structure of wafer bond quality, the structure
Including：
Bottom wafers, be provided in the bottom wafers bottom metal layers and above the bottom metal layers
One bottom land, the second bottom land and third bottom land, it is first bottom land, second bottom land, described
Third bottom land is electrically connected with the bottom metal layers respectively；
Top wafer is provided with top pads, including the first top pads, the second top weldering on the top crystal column surface
The back side of disk and third top pads, the top wafer is provided with testing weld pad, including the first testing weld pad, the second test weldering
Disk and third testing weld pad, first top pads, the second top pads and third top pads are welded with first test
Disk, the second testing weld pad and third testing weld pad are electrically connected, and the top wafer further includes being connected to first test
The first calibrating terminal and the second calibrating terminal of pad, the third calibrating terminal for being connected to second testing weld pad and the 4th survey
Examination terminal and the 5th calibrating terminal and the 6th calibrating terminal for being connected to the third testing weld pad；
Wherein, first top pads and first bottom land are completely superposed engagement, second top pads
It is completely superposed engagement with second bottom land, the third top pads and the third bottom land partially overlap and connect
It closes, to realize the engagement of the bottom wafers and the top wafer.
Preferably, the bottom metal layers, second bottom land, second top pads and described second
Testing weld pad forms interconnection structure, and the bottom wafers and the top wafer are formed access.
Preferably, the bottom metal layers, first bottom land, first top pads and the first test
Pad forms the first test target；
The bottom metal layers, the third bottom land, the third top pads and third testing weld pad are formed
Second test target.
Preferably, first test target, second test target are located at the both sides of the interconnection structure, shape
At symmetrical test structure, so that the extra resistance other than test target is equal.
Preferably, bottom through-hole is additionally provided in the bottom wafers, first bottom land, second bottom
Pad and the third bottom land are electrically connected by the bottom through-hole and the bottom metal layers.
Preferably, being additionally provided with top through-hole in the top wafer, the testing weld pad passes through the top through-hole
It is electrically connected respectively with first top pads, second top pads, the third top pads.
Preferably, the testing weld pad is the first metal layer of the top wafer, it is brilliant by being located at the top
Multiple metal layers and through-hole in circle are electrically connected with the top pads, and the top pads are the top-gold of the top wafer
Belong to layer.
Preferably, first bottom land, the shape of third bottom land, the first top pads and third top pads
Shape and area are all identical；
The shape and area of second bottom land and second top pads are all identical；
Wherein, the area of second bottom land and second top pads is more than first bottom land, the
The area of three bottom lands, the first top pads and third top pads.
Preferably, first bottom land, second bottom land, third bottom land, the first top pads,
Second top pads and third top pads shape are square, and the material of selection is copper.
Preferably, the size dimension of the third bottom land and the third top pads is L, at the top of the third
Shift value between pad and the third bottom land staggeredly is a, the L ﹥ a.
The present invention also provides a kind of detection methods for selecting above-mentioned detection structure：
Step（a）Apply stress voltage on first calibrating terminal and the third calibrating terminal, test described the
Voltage between three calibrating terminals and the 4th calibrating terminal, and calculate resistance value R1；
Step（b）Apply stress voltage on the third calibrating terminal and the 5th calibrating terminal, test described the
Voltage between four calibrating terminals and the 6th calibrating terminal, and calculate resistance value R2；
Step（c）The electricity of the engagement between the third top pads and the third bottom land is calculated according to R1 and R2
Resistance.
Preferably, the step（c）It further include following sub-step：
Step（c-1）R1=the RL+RS=2RPAD+RB1+RS, R2=RR+RS=2RPAD+RB2+RS, wherein the RLIt is first
The resistance value of test target, RRFor the resistance value of second test target, RSFor the first test target described in the test structure and
Extra resistance outside second test target, RPADFor the resistance of landing pad itself, the RB1For first bottom land
Engagement resistance between first top pads, the RB2For second bottom land and second top pads it
Between engagement resistance；
Step（c-2）Pass through step（c-1）In two formulas obtain R1-R2=RB1-RB2, the RB1And RB2Difference be face
Product size, RB1/RB2=（L-a）（L-a）/（L×L）；
Step（c-3）According to R1-R2=RB1-RB2And RB1/RB2=（L-a）（L-a）/（L×L）Calculate the RB1And RB2。
Preferably, the test structure uses Kelvin configuration method for testing resistance, to avoid by test probe and gold
Belong to the error that lead is brought.
The present invention provides a kind of detection structures and detection method of wafer bond quality, in the detection structure, bottom
Portion's wafer forms interconnection architecture by bottom metal layers, bottom land and positioned at bottom through-hole between the two, as described
The lower half portion of test structure, described in the top wafer top pads and metal layer at top and positioned between the two
Top through-hole forms interconnection architecture, the top half as the test structure, wherein the metal layer at top is welded as test
Testing weld pad is opened in after top wafer is thinned in the metal layer at top of top wafer by disk.
The test structure is made of 3 parts, and the test structure of the left and right sides is respectively that the first test target and second are surveyed
Target is tried, intermediate structure mainly plays lead, and the test structure of bottom wafers is guided in the wafer of top to be formed and is tested
Access, test structure are symmetrical structure, make in access that other extra resistances are equal other than test target, and test structure is using opening
The literary structural resistance test method of that can improve measuring accuracy to avoid the error brought by test probe and metal leads.
Test structure kind of the present invention is simple and effective, solve in 3D IC Cu-Cu engage resistance Rc cannot essence
Really the problem of test.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 is the structural schematic diagram of the detection structure of wafer bond quality in the prior art；
Fig. 2 a are the sectional view of the detection structure of wafer bond quality described in the embodiment of the invention；
Fig. 2 b are the vertical view of the detection structure of wafer bond quality described in the embodiment of the invention；
Fig. 3 is the detection structure equivalent circuit diagram of wafer bond quality described in the embodiment of the invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate crystalline substance of the present invention
The detection structure and its detection method of circle bond quality.Obviously, execution of the invention is not limited to the technology people of semiconductor applications
The specific details that member is familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or combination thereof.
Now, exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
The present invention provides a kind of wafer connexon to solve the problems, such as current semiconductor devices preparation process
The detection structure of amount, the structure include：
Bottom wafers, be provided in the bottom wafers bottom metal layers and above the bottom metal layers
One bottom land 202, the second bottom land and third bottom land, first bottom land, second bottom land, institute
Third bottom land is stated to be electrically connected with the bottom metal layers respectively；
Top wafer is provided with top pads, including the first top pads, the second top weldering on the top crystal column surface
The back side of disk and third top pads, the top wafer is provided with testing weld pad, including the first testing weld pad, the second test weldering
Disk and third testing weld pad, first top pads, the second top pads and third top pads are welded with first test
Disk, the second testing weld pad and third testing weld pad are electrically connected, and the top wafer further includes being connected to first test
The first calibrating terminal and the second calibrating terminal of pad, the third calibrating terminal for being connected to second testing weld pad and the 4th survey
Examination terminal and the 5th calibrating terminal and the 6th calibrating terminal for being connected to the third testing weld pad；
Wherein, first top pads and first bottom land are completely superposed engagement, second top pads
It is completely superposed engagement with second bottom land, the third top pads and the third bottom land partially overlap and connect
It closes, to realize the engagement of the bottom wafers and the top wafer.
Wherein, bottom through-hole, first bottom land, second bottom land are additionally provided in the bottom wafers
It is electrically connected by the bottom through-hole and the bottom metal layers with the third bottom land.
Wherein, top through-hole, first metal layer at top, second top-gold are additionally provided in the top wafer
Belong to layer and the third metal layer at top to weld with first top pads, second top respectively by the top through-hole
Disk, third top pads electrical connection.
Wherein, the bottom metal layers, the bottom through-hole, second bottom land, second top pads, institute
Top through-hole, second metal layer at top formation interconnection structure are stated, the bottom wafers and the top wafer are formed
Access；
The bottom metal layers, first bottom land, first top pads, the first metal layer at top shape
At the first test target, it is located at the left side of test structure；The bottom metal layers, the bottom through-hole, third bottom weldering
Disk, the third top pads, the top through-hole, the third metal layer at top form the second test target, are located at described
The test structure on the right side of test structure, the left and right sides is test target, and intermediate structure mainly plays lead, by bottom crystalline substance
Circle（bottom wafer）Test structure guide to top wafer（top wafer）Test access is formed, test structure is symmetrical
Structure, makes in access that other extra resistances are equal other than test target.Test structure uses Kelvin configuration resistance test side
Method can improve measuring accuracy to avoid the error brought by test probe and metal leads.
Embodiment 1
Test structure of the present invention is described further below in conjunction with the accompanying drawings.
First, with reference to Fig. 2 a-2b, in the test structure, including semiconductor substrate 201, the semiconductor substrate 201
It can be following at least one of the material being previously mentioned：Silicon, silicon-on-insulator（SOI）, silicon is laminated on insulator（SSOI）, absolutely
SiGe is laminated on edge body（S-SiGeOI）, germanium on insulator SiClx（SiGeOI）And germanium on insulator（GeOI）Deng.Partly lead
Active area can be defined in body substrate.
The test structure includes the bottom wafers 30 being interconnected and top wafer 40, the bottom wafers 30 and top
It is interconnected by pad between wafer 40, the engagement of the pad includes multiple mutually isolated pads, wherein at the bottom
In portion's wafer 30, including the first bottom land 202, the second bottom land 203, third bottom land 204, in the top wafer
It is corresponding in 40 to be provided with the first top pads 205, the second top pads 206 and third top pads 207, wherein described
One bottom land 202 and first top pads 205 engagement, second bottom land 203 and second top pads
206 engagements, the third bottom land 204 and third top pads 207 engage.
Preferably, first bottom land 202, the second bottom land 203, the 204, first top of third bottom land
The metal copper pad that pad 205, the second top pads 206 and third top pads 207 are square, and in each group up and down
Pad in wafer has same size, such as first bottom land 202 and first top pads 205 with identical
Size, the two is directed at engagement, is completely superposed completely；The ruler of second bottom land 203 and second top pads 206
It is very little identical, and alignment overlaps completely up and down；The size of the third bottom land 204 and third top pads 207 also complete phase
Together, but the two is not fully aligned, and is not completely superposed, with certain displacement, the third top weldering when the two engages
Displacement most a, the L ﹥ a between disk and the third bottom land staggeredly.
The third bottom land of second test target and the third top pads are to be set as technique typical sizes L
（2um）, middle leads effect interconnection architecture in landing pad（bonding PADsize）It can bigger reduction additional electric
Resistance, the engagement displacement between third bottom land and the third top pads described in the second test target of right side can basis
It needs that a variety of sizes are arranged, in this example by taking 0.2um as an example.
Preferably, first bottom land 202, third bottom land 204, the first top pads 205 and third top
The shape and area of portion's pad 207 are all identical；The shape of second bottom land 203 and second top pads 206 and
Area is all identical；
Wherein, the area of second bottom land 203 and second top pads 206 is welded more than first bottom
The area of disk 202, third bottom land 204, the first top pads 205 and third top pads 207.
Preferably, being engaged by the pad between the bottom wafers 30 and the top wafer, the bottom
Further include the first interlayer dielectric layer 208, first bottom land 202, the second bottom land 203, third bottom in wafer 30
Pad 204 is formed in first interlayer dielectric layer 208, further includes the second interlayer dielectric layer 209 in the top wafer 40,
Wherein described first top pads 205, the second top pads 206 and third top pads 207 are formed in second interlayer and are situated between
In electric layer 209, the engagement of the bottom wafers 30 and the top wafer 40 only includes the set of pad, does not include described
The engagement of first interlayer dielectric layer 208 and second interlayer dielectric layer 209, first interlayer dielectric layer 208 and described
Setting is isolated between two interlayer dielectric layers 20, certain gap is provided between the two, to avoid the contact of the two.
The structure further includes the bottom metal layers 210 being located in the bottom wafers 30, wherein the bottom metal layers
It is set in first interlayer dielectric layer 208, is located at first bottom land 202, the second bottom land 203, third bottom
The top of portion's pad 204, and be electrically connected with first bottom land 202, the second bottom land 203, third bottom land 204
It connects.
Preferably, the test structure still further comprises bottom through-hole 211, the bottom through-hole 211 is located at described
In first interlayer dielectric layer 208, for connecting the bottom metal layers 210 and first bottom land 202, the weldering of the second bottom
Disk 203, third bottom land 204, to form electrical connection.
The forming method of the wherein described bottom metal layers 210, bottom through-hole 211 and the bottom land can be in institute
It states and first deposits the first interlayer dielectric layer 208 in semiconductor substrate 201, then pattern and formed opening, sink in said opening
Product conductive material, to form the bottom metal layers 210；Then proceed to the first interlayer dielectric layer 208 of deposition, and pattern again
Change, forms multiple via openings, and expose the bottom metal layers 210, conductive material is filled in the via openings, with shape
At the bottom through-hole 211, the bottom land is re-formed by similar methods.
Preferably, after forming the bottom land, in order to when being engaged with top pads, between the dielectric layer
It can also includes the steps that further planarizing first interlayer dielectric layer 208 that will not contact with each other, described in exposed portion
Bottom land.
It should be noted that the forming method of the bottom metal layers 210, bottom through-hole 211 and the bottom land
It is not limited to above-mentioned example, those skilled in the art can be configured as needed.
It is formed to interconnect between bottom metal layers 210, bottom through-hole 211 and bottom land in the bottom wafers and be formed
The lower half portion of the test structure.Include first top pads the 205, second top weldering in the top wafer 40
Disk 206 and third top pads 207 are formed in second interlayer dielectric layer 209, to be engaged with the bottom wafers 30, institute
It further includes testing weld pad to state test, wherein the testing weld pad connects first top pads 205, the second top pads 206
With third top pads 207.
The testing weld pad described in the specific implementation mode of the present invention is the first metal layer of the top wafer, is led to
The multiple metal layers and through-hole crossed in the top wafer are electrically connected with the top pads, and the top pads are described
The metal layer at top of top wafer.
Specifically, the top pads described in the top wafer are the metal layer at top, in the metal layer at top
Lower section be provided with multiple metal layers, such as the n-th metal layer below the metal layer at top, the (n-1)th metal layer is always
To the first metal layer, n-th metal layer, the (n-1)th metal layer is connected between the first metal layer by through-hole, and described n-th
Metal layer, the (n-1)th metal layer to the first metal layer are set in second interlayer dielectric layer 209.
Wherein, the testing weld pad, including the first testing weld pad, the second testing weld pad and third testing weld pad, described
One top pads 205, the second top pads 206 and third top pads 207 and first testing weld pad, the second testing weld pad
It is electrically connected with third testing weld pad.
The top wafer further include be connected to first testing weld pad the first calibrating terminal and the second calibrating terminal,
It is connected to the third calibrating terminal of second testing weld pad and the 4th calibrating terminal and is connected to the third testing weld pad
The 5th calibrating terminal and the 6th calibrating terminal；
Preferably, top through-hole 212 is provided between the metal layer at top and the top pads, specifically,
In first testing weld pad, the second testing weld pad and third testing weld pad and first top pads the 205, second top weldering
Top through-hole 212 is provided between disk 206 and third top pads 207, to form electrical connection.
Further, the intermediate position on first testing weld pad, the second testing weld pad and third testing weld pad, preferably
Center is provided with separation layer, expose respectively first testing weld pad, the second testing weld pad and third testing weld pad two
End position, forms calibrating terminal.
Preferably, after forming the top wafer, by the way that the back side of top wafer is thinned, is formed and expose the first gold medal
The opening for belonging to layer M1, to form above-mentioned testing weld pad.
Wherein, the top pads described in the top wafer 40, the first metal layer and the top through-hole
Forming method can select the common preparation method of ability, it is not limited to a certain method.
In the test structure, test structure uses Kelvin configuration method for testing resistance, can be visited to avoid by test
The error that needle and metal lead wire are brought improves measuring accuracy, wherein positioned at left side, the bottom metal layers 210, bottom through-hole
211, first bottom land 202, first top pads 205, top through-hole and the first metal layer at top shape
At the first test target；In the right side of the structure, the bottom metal layers 210, bottom through-hole 211, the third bottom
Pad 204, the third top pads 207, top through-hole 212 and the third metal layer at top form the second test mesh
Mark.
Further, in the bottom metal layers of the centre of first test target and second test target
210, bottom through-hole 211, second bottom land 203, second top pads 206, top through-hole 212 and described
Two metal layer at top form interconnection structure, and the bottom wafers 30 are connected to the top wafer 40, form test access.
In the test structure, first test target, the second test target and the interconnection architecture positioned at centre
The test structure of formation is symmetrical structure, makes in access that other extra resistances are equal other than test target.
Embodiment 2
Above-mentioned test structure is selected to examine bottom wafers and top wafer engagement situation the present invention also provides a kind of
The method of survey, wherein Fig. 3 are the detection structure equivalent circuit diagram of wafer bond quality described in a specific implementation mode.
The method includes：
Step（a）Apply voltage on first calibrating terminal and the third calibrating terminal, tests the third and survey
The voltage between terminal and the 4th calibrating terminal is tried, and calculates resistance value R1；
Step（b）Apply voltage on the third calibrating terminal and the 5th calibrating terminal, test the described 4th is surveyed
The voltage between terminal and the 6th calibrating terminal is tried, and calculates resistance value R2；
Step（c）The electricity of the engagement between the third top pads and the third bottom land is calculated according to R1 and R2
Resistance.
Specifically, the step（c）It further include following sub-step：
Step（c-1）R1=the RL+RS=2RPAD+RB1+RS, R2=RR+RS=2RPAD+RB2+RS, wherein the RLIt is first
The resistance value of test target, RRFor the resistance value of second test target, RSFor the first test target described in the test structure and
Extra resistance outside second test target, RPADFor the resistance of pad itself, the RB1For first bottom land and institute
State the engagement resistance between the first top pads, the RB2Between second bottom land and second top pads
Engage resistance；
Step（c-3）By step（c-1）In two formulas obtain R1-R2=RB1-RB2, the RB1And RB2Difference be area
Size, RB1/RB2=（L-a）（L-a）/（L×L）；
Step（c-3）According to R1-R2=RB1-RB2And RB1/RB2=（L-a）（L-a）/（L×L）Calculate the RB1And RB2。
The third bottom land of second test target and the third top pads are to be set as technique typical sizes L
（2um）, middle leads effect interconnection architecture in landing pad（bonding PAD size）It can bigger reduction additional electric
Resistance, the engagement displacement between third bottom land and the third top pads described in the second test target of right side can basis
It needs that a variety of sizes are arranged, in this example by taking 0.2um as an example.
The present invention provides a kind of detection structures and detection method of wafer bond quality, in the detection structure, bottom
Portion's wafer forms interconnection architecture by bottom metal layers, bottom land and positioned at bottom through-hole between the two, as described
The lower half portion of test structure, described in the top wafer top pads and metal layer at top and positioned between the two
Top through-hole forms interconnection architecture, the top half as the test structure, wherein the metal layer at top is welded as test
Testing weld pad is opened in after top wafer is thinned in the metal layer at top of top wafer by disk.
The test structure is made of 3 parts, and the test structure of the left and right sides is respectively that the first test target and second are surveyed
Target is tried, intermediate structure mainly plays lead, and the test structure of bottom wafers is guided in the wafer of top to be formed and is tested
Access, test structure are symmetrical structure, make in access that other extra resistances are equal other than test target, and test structure is using opening
The literary structural resistance test method of that can improve measuring accuracy to avoid the error brought by test probe and metal leads.
Test structure kind of the present invention is simple and effective, solve in 3D IC Cu-Cu engage resistance Rc cannot essence
Really the problem of test.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of detection structure of wafer bond quality, the structure include：
Bottom wafers are provided with bottom metal layers and the first bottom above the bottom metal layers in the bottom wafers
Portion's pad, the second bottom land and third bottom land, first bottom land, second bottom land, the third
Bottom land is electrically connected with the bottom metal layers respectively；
Top wafer, is provided with top pads on the top crystal column surface, including the first top pads, the second top pads and
Third top pads, the back side of the top wafer are provided with testing weld pad, including the first testing weld pad, the second testing weld pad and
Third testing weld pad, first top pads, the second top pads and third top pads and first testing weld pad, the
Two testing weld pads and third testing weld pad are electrically connected, and the top wafer further includes being connected to first testing weld pad
First calibrating terminal and the second calibrating terminal, the third calibrating terminal and the 4th test lead that are connected to second testing weld pad
Son and the 5th calibrating terminal and the 6th calibrating terminal for being connected to the third testing weld pad；
Wherein, first top pads and first bottom land are completely superposed engagement, second top pads and institute
It states the second bottom land and is completely superposed engagement, the third top pads and the third bottom land partially overlap engagement, with
It realizes the engagement of the bottom wafers and the top wafer and realizes the detection of the engagement resistance of the wafer engagement.
2. detection structure according to claim 1, which is characterized in that the bottom metal layers, second bottom land,
Second top pads and second testing weld pad form interconnection structure, and the bottom wafers and the top are brilliant
Circle forms access.
3. detection structure according to claim 2, which is characterized in that the bottom metal layers, first bottom land,
First top pads and the first testing weld pad form the first test target；
The bottom metal layers, the third bottom land, the third top pads and third testing weld pad form second
Test target.
4. detection structure according to claim 3, which is characterized in that first test target, the second test mesh
Mark forms symmetrical detection structure in the both sides of the interconnection structure, so that the extra resistance other than test target is equal.
5. detection structure according to claim 1, which is characterized in that it is additionally provided with bottom through-hole in the bottom wafers,
First bottom land, second bottom land and the third bottom land pass through the bottom through-hole and the bottom
Metal layer is electrically connected.
6. detection structure according to claim 1, which is characterized in that top through-hole is additionally provided in the top wafer,
The testing weld pad by the top through-hole respectively with first top pads, second top pads, the third
Top pads are electrically connected.
7. detection structure according to claim 1, which is characterized in that the testing weld pad is the first of the top wafer
Metal layer is electrically connected by multiple metal layers in the top wafer and through-hole with the top pads, the top
Portion's pad is the metal layer at top of the top wafer.
8. detection structure according to claim 1, which is characterized in that first bottom land, third bottom land,
The shape and area of one top pads and third top pads are all identical；
The shape and area of second bottom land and second top pads are all identical；
Wherein, the area of second bottom land and second top pads is more than first bottom land, third bottom
The area of portion's pad, the first top pads and third top pads.
9. detection structure according to claim 1, which is characterized in that first bottom land, second bottom weldering
Disk, third bottom land, the first top pads, the second top pads and third top pads shape are square, selection
Material is copper.
10. detection structure according to claim 1, which is characterized in that at the top of the third bottom land and the third
The size dimension of pad is L, and the shift value between the third top pads and the third bottom land staggeredly is a, the L
﹥ a.
11. the detection method of the detection structure described in a kind of one of claims 1 to 10：
Step (a) applies stress voltage on first calibrating terminal and the third calibrating terminal, and test described second is surveyed
The voltage between terminal and the 4th calibrating terminal is tried, and calculates resistance value R1；
Step (b) applies stress voltage on the third calibrating terminal and the 5th calibrating terminal, and test the described 4th is surveyed
The voltage between terminal and the 6th calibrating terminal is tried, and calculates resistance value R2；
Step (c) according to R1 and R2 calculate engagement resistance between first bottom land and first top pads and
Engagement resistance between second bottom land and second top pads；
The step (c) further includes following sub-step：
Step (c-1) described R1=RL+RS=2RPAD+RB1+RS, R2=RR+RS=
2RPAD+RB2+RS, wherein the RLFor the resistance value of the first test target, RRFor the resistance value of second test target, RSFor
First test target described in the detection structure and the extra resistance outside second test target, RPADFor landing pad sheet
The resistance of body, the RB1For the engagement resistance between first bottom land and first top pads, the RB2For institute
State the engagement resistance between third bottom land and the third top pads；
Step (c-2) obtains R1-R2=R by two formulas in step (c-1)B1-RB2, the RB1And RB2Difference be area
Size, RB1/RB2=(L-a) (L-a)/(L × L)；
Step (c-3) is according to R1-R2=RB1-RB2And RB1/RB2=(L-a) (L-a)/(L × L) calculates the RB1And RB2。
12. according to the method for claim 11, which is characterized in that the detection structure uses Kelvin configuration resistance test
Method, to avoid the error brought by test probe and metal lead wire.
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| CN106443192A (en) * | 2016-10-31 | 2017-02-22 | 昆山国显光电有限公司 | Detection device and detection method for binding impedance of display screen |
| CN107046020B (en) * | 2016-12-13 | 2019-07-26 | 武汉新芯集成电路制造有限公司 | A kind of test structure and its distribution method |
| CN109422234B (en) * | 2017-09-01 | 2021-04-09 | 中芯国际集成电路制造(上海)有限公司 | Test structure and manufacturing method thereof |
| KR20240000635A (en) | 2019-01-30 | 2024-01-02 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Hybrid bonding using dummy bonding contacts |
| EP3850663A4 (en) * | 2019-01-30 | 2023-07-12 | Yangtze Memory Technologies Co., Ltd. | Hybrid bonding using dummy bonding contacts and dummy interconnects |
| CN111025130B (en) * | 2020-01-07 | 2021-07-16 | 电子科技大学 | SMT detection method for multilayer interconnected FPC |
| WO2022104805A1 (en) * | 2020-11-23 | 2022-05-27 | 江苏时代全芯存储科技股份有限公司 | Test structure and test method |
| CN117542837A (en) * | 2022-08-01 | 2024-02-09 | 长鑫存储技术有限公司 | Semiconductor structure and measuring method |
| CN117558714B (en) * | 2024-01-09 | 2024-03-22 | 盛合晶微半导体(江阴)有限公司 | Hybrid bonding packaging structure, offset testing method and chip mounter |
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