CN117542837A - Semiconductor structure and measuring method - Google Patents

Semiconductor structure and measuring method Download PDF

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Publication number
CN117542837A
CN117542837A CN202210918369.5A CN202210918369A CN117542837A CN 117542837 A CN117542837 A CN 117542837A CN 202210918369 A CN202210918369 A CN 202210918369A CN 117542837 A CN117542837 A CN 117542837A
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wafer
test
pad
test pad
length
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张志伟
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210918369.5A priority Critical patent/CN117542837A/en
Priority to PCT/CN2022/111771 priority patent/WO2024026914A1/en
Publication of CN117542837A publication Critical patent/CN117542837A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a measurement method. The semiconductor structure includes: the device comprises a first wafer, a second wafer and at least one group of test structures, wherein the test structures comprise: the first bonding pads and the at least two second testing pads are arranged in the second wafer at intervals along the first direction, the second bonding surfaces expose the surfaces of the second testing pads, the first testing pads are opposite to the interval areas between the two second testing pads, the first second testing pads are adjacent to the first end, and the second testing pads are adjacent to the second end; the minimum distance between the first second test pad and the first end is a first length, the minimum distance between the second test pad and the second end is a second length, the first length is equal to the second length, and the first length and the second length are both greater than zero and smaller than a preset value. The embodiment of the disclosure is at least beneficial to improving the alignment precision of wafer bonding.

Description

Semiconductor structure and measuring method
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a measuring method.
Background
The wafer bonding technology refers to that two polished homogeneous wafers or heterogeneous wafers are tightly bonded through chemical and physical actions, and atoms of a bonding interface react to form covalent bonds to be combined into a whole under the action of external force after the wafers are bonded, so that the bonding interface reaches specific bonding strength.
Wafer bonding needs to control the accuracy of wafer-to-wafer alignment, an alignment mark is usually required to be designed at the joint interface of two wafers, but the current alignment mark is utilized to align two wafers bonded together, so that the displacement amount of offset between the two wafers bonded together cannot be accurately known, and the alignment accuracy of the two wafers bonded together is poor, thereby affecting the performance of the bonded semiconductor structure.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a measuring method, which are at least beneficial to improving the alignment precision of wafer bonding.
An aspect of an embodiment of the present disclosure provides a semiconductor structure, including: a first wafer having a first bonding surface; the second wafer is provided with a second bonding surface bonded with the first bonding surface; at least one set of test structures, the test structures comprising: the first bonding surface exposes the surface of the first testing pad, and the first testing pad is provided with a first end and a second end which are opposite and exposed out of the first bonding surface in a first direction; the second bonding surface exposes the surface of the second test pad, the first test pad is opposite to the spaced area between the two second test pads, the first second test pad is adjacent to the first end, and the second test pad is adjacent to the second end; the minimum distance between the first second test pad and the first end is a first length, the minimum distance between the second test pad and the second end is a second length, the first length is equal to the second length, and the first length and the second length are both greater than zero and smaller than a preset value.
In some embodiments, each of the second test pads exposed from the second bonding surface has the same shape.
In some embodiments, the first test pad further comprises a third end and a fourth end arranged along a second direction, the test structure further comprises two second test pads arranged at intervals along the second direction, the first direction being different from the second direction; the third second test pad is adjacent to the third end, the fourth second test pad is adjacent to the fourth end, the minimum distance between the third second test pad and the third end is a third length, the minimum distance between the fourth second test pad and the fourth end is a fourth length, the third length is equal to the fourth length, and the third length and the fourth length are both greater than zero and smaller than a preset value.
In some embodiments, the third length is equal to the first length.
In some embodiments, the semiconductor structure has at least two sets of test structures, wherein a first direction in at least one set of test structures is an X-direction and a first direction in at least one other set of test structures is a Y-direction.
In some embodiments, the first wafer has a first middle region and a first edge region, the second wafer has a second middle region and a second edge region, the first middle region is opposite to the second middle region, the first edge region is opposite to the second edge region, the first middle region and the opposite second middle region have corresponding test structures, and the first edge region and the opposite second edge region also have corresponding test structures.
In some embodiments, the first wafer includes a plurality of first chips, and the second wafer includes a plurality of second chips, each first chip being directly opposite a corresponding second chip; part of the first chip and the opposite second chip are provided with corresponding test structures.
In some embodiments, the first chip and the second chip each have a chip middle region and a chip edge region, and the chip middle region of the first chip is opposite to the chip middle region of the opposite second chip, and the chip edge region of the first chip is opposite to the chip edge region of the opposite second chip, and the test structure is located in the opposite chip middle region and the opposite chip edge region.
In some embodiments, the first chip and the second chip each have a chip middle region, the chip middle region of the first chip is opposite to the chip middle region of the opposite second chip, the first wafer further includes a first scribe line at an edge of the first chip, the second wafer further includes a second scribe line at an edge of the second chip opposite to the corresponding first scribe line, the test structure is located in the opposite chip middle region, and the first scribe line and the opposite second scribe line.
In some embodiments, the material of the first test pad is the same as the material of the second test pad.
In some embodiments, the semiconductor structure further comprises: the first bonding surface exposes the first signal pad; the second bonding surface exposes the second signal pad, and the first signal pad is opposite to the second signal pad.
In some embodiments, the first bonding surface exposes a width of the first signal pad that is the same as a width of the second bonding surface exposing the second signal pad in the first direction.
In some embodiments, the test structures are adjacent to the first signal pads and the corresponding second signal pads.
Another aspect of the embodiments of the present disclosure further provides a measurement method, including: providing a first wafer and a second wafer in the semiconductor structure of any one of the above; attaching the first bonding surface to the second bonding surface for pre-alignment; after prealignment, a connection state between the first test pad and the first second test pad and a connection state between the first test pad and the second test pad are obtained, wherein if the first test pad and the first second test pad are in a disconnection state, the second wafer is judged to be displaced relative to the first wafer in the direction of the second end pointing to the first end, and if the first test pad and the second test pad are in a disconnection state, the second wafer is judged to be displaced relative to the first wafer in the direction of the first end pointing to the second end.
In some embodiments, the manner of obtaining the connection state of the first test pad and the specific second test pad includes: measuring the contact resistance of the first test pad and the specific second test pad; if the resistance value of the contact resistor is larger than or equal to the preset value, the first test pad and the specific second test pad are judged to be in a disconnected state.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the semiconductor structure comprises a first wafer and a second wafer which are bonded with each other, wherein the first bonding surface of the first wafer and the second bonding surface of the second wafer are bonded with each other, the first wafer and the second wafer which are bonded with each other are provided with test structures for measuring alignment deviation of the first wafer and the second wafer, the test structures comprise a first test bonding pad exposed on the first bonding surface and at least two second test bonding pads exposed on the second bonding surface, and two ends of the first test bonding pad and the two second test bonding pads are arranged at intervals along a first direction and are used for measuring displacement of the second wafer relative to the first wafer in a first direction. In addition, the first test pad is opposite to the interval area between the two second test pads, the first end of the first test pad corresponds to the first second test pad, the second end of the first test pad corresponds to the second test pad, the first second test pad is offset by a first length relative to the first end in a first offset direction parallel to the first direction, the second test pad is offset by a second length relative to the second end in a second offset direction, the first offset direction and the second offset direction are opposite directions, and the first offset direction is the direction in which the second test pad points to the first second test pad. The first length and the second length are both smaller than a preset value, the preset value can be the minimum dimension which can be measured by the measuring equipment, so that if the first end is connected with the first second test pad, the second wafer is judged to be displaced in the second offset direction relative to the first wafer, if the second end is connected with the second test pad, the second wafer is judged to be displaced in the first offset direction relative to the first wafer, and the displacement amount of the second wafer offset relative to the first wafer can be obtained according to the width of the part of the first test pad and the second test pad which are overlapped in the first direction. Therefore, whether the second wafer and the first wafer are aligned and bonded can be judged through the test structure, the displacement amount of the second wafer, which is offset relative to the first wafer, is obtained, and the bonding of the first wafer and the second wafer in the next semiconductor structure is calibrated according to the displacement amount, so that the alignment precision of the bonding of the first wafer and the second wafer in the semiconductor structure can be improved, and further the performance of the semiconductor structure can be improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of another semiconductor structure according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a structure of a portion of a second bonding surface illustrating a first test pad according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another configuration of a portion of a second bonding surface showing a first test pad provided by an embodiment of the present disclosure;
FIG. 5 is a schematic structural view of a portion of a second bonding surface illustrating a first test pad according to another embodiment of the present disclosure;
FIG. 6 is a schematic diagram of another configuration of a portion of a second bonding surface showing a first test pad provided by an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of another configuration of a portion of a second bonding surface showing a first test pad provided by an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a first wafer according to an embodiment of the disclosure;
fig. 9 is a schematic structural diagram of a positional relationship between a test structure and a first chip on a first wafer according to an embodiment of the disclosure;
fig. 10 is a schematic structural diagram of a positional relationship between a test structure and a first chip on a first wafer according to another embodiment of the disclosure;
FIG. 11 is a schematic diagram of a test structure in which a second wafer is offset with respect to a first wafer according to an embodiment of the present disclosure;
FIG. 12 is a schematic diagram of another test structure in which a second wafer is offset relative to a first wafer according to an embodiment of the present disclosure;
fig. 13 is a schematic diagram of a test structure in which a second wafer is offset with respect to a first wafer according to an embodiment of the disclosure.
Detailed Description
As known from the background art, the current alignment mark is used to align two wafers bonded together, so that the displacement of the two wafers bonded together cannot be accurately known, and the performance of the semiconductor structure is affected.
The embodiment of the disclosure provides a semiconductor structure and a measuring method. The semiconductor structure comprises a first wafer and a second wafer, wherein the first bonding surface of the first wafer is bonded with the second bonding surface of the second wafer, the first wafer and the second wafer which are bonded with each other are provided with a test structure for measuring the alignment deviation of the first wafer and the second wafer, the test structure comprises a first test bonding pad exposed on the first bonding surface and at least two second test bonding pads exposed on the second bonding surface, the first test bonding pad is opposite to the area of the interval between the two second test bonding pads, the first end of the first test bonding pad corresponds to the first second test bonding pad, the second end of the first test bonding pad corresponds to the second test bonding pad, the first second test bonding pad is offset by a first length relative to the first end in a first offset direction parallel to the first direction, the second test bonding pad is offset by a second length relative to the second end in a second offset direction, the first offset direction and the second offset direction are opposite directions, and the first offset direction is also the second offset direction points to the second test bonding pad. The first length and the second length are both smaller than a preset value, the preset value can be the minimum dimension which can be measured by the measuring equipment, so that if the first end is connected with the first second test pad, the second wafer is judged to be displaced in the second offset direction relative to the first wafer, if the second end is connected with the second test pad, the second wafer is judged to be displaced in the first offset direction relative to the first wafer, and the displacement amount of the second wafer offset relative to the first wafer can be obtained according to the width of the part of the first test pad and the second test pad which are overlapped in the first direction. Therefore, whether the second wafer is aligned and bonded with the first wafer or not can be judged through the test structure, the displacement of the second wafer relative to the first wafer is obtained, and the bonding of the first wafer and the second wafer in the next semiconductor structure is calibrated according to the displacement, so that the alignment precision of the bonding of the first wafer and the second wafer in the semiconductor structure can be improved, and further the performance of the semiconductor structure can be improved.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the embodiments of the present disclosure. However, the technical solutions claimed in the embodiments of the present disclosure can be implemented without these technical details and based on various changes and modifications of the following embodiments.
Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure; fig. 2 is a schematic structural diagram of another semiconductor structure according to an embodiment of the present disclosure; FIG. 3 is a schematic diagram of a structure of a portion of a second bonding surface illustrating a first test pad according to an embodiment of the present disclosure; FIG. 4 is a schematic diagram of another configuration of a portion of a second bonding surface showing a first test pad provided by an embodiment of the present disclosure; FIG. 5 is a schematic structural view of a portion of a second bonding surface illustrating a first test pad according to another embodiment of the present disclosure; FIG. 6 is a schematic diagram of another configuration of a portion of a second bonding surface showing a first test pad provided by an embodiment of the present disclosure; FIG. 7 is a schematic diagram of another configuration of a portion of a second bonding surface showing a first test pad provided by an embodiment of the present disclosure; fig. 8 is a schematic structural diagram of a first wafer according to an embodiment of the disclosure; fig. 9 is a schematic structural diagram of a positional relationship between a test structure and a first chip on a first wafer according to an embodiment of the disclosure; fig. 10 is a schematic structural diagram of a positional relationship between a test structure and a first chip on a first wafer according to another embodiment of the disclosure.
Referring to fig. 1, a semiconductor structure includes: a first wafer 100, the first wafer 100 having a first bonding surface; a second wafer 110, the second wafer 110 having a second bonding surface bonded to the first bonding surface; at least one set of test structures 120, the test structures 120 comprising: the first test pad 101, the first bonding surface exposes a surface of the first test pad 101, and the first test pad 101 has opposite first and second ends 200 and 201 exposed at the first bonding surface in a first direction; at least two second test pads 111, the two second test pads 111 are arranged in the second wafer 110 at intervals along the first direction, the second bonding surface exposes the surface of the second test pad 111, the first test pad 101 is opposite to the spaced area between the two second test pads 111, the first second test pad 111 is adjacent to the first end 200, and the second test pad 111 is adjacent to the second end 201; the minimum distance between the first second test pad 111 and the first end 200 is a first length, the minimum distance between the second test pad 111 and the second end 201 is a second length, the first length is equal to the second length, and the first length and the second length are both greater than zero and smaller than a preset value.
Referring to fig. 1, a first test pad 101 and a second test pad 111 arranged at intervals along a first direction are used to measure an amount of displacement by which a second wafer 110 is offset in the first direction with respect to a first wafer 100. When the first wafer 100 and the second wafer 110 are aligned and bonded, the first second test pad 111 is offset by a first length in a first offset direction parallel to the first direction with respect to the first end 200, the second test pad 111 is offset by a second length in a second offset direction with respect to the second end 201, the first offset direction and the second offset direction are opposite directions, and the first offset direction is also the direction in which the second test pad 111 points to the first second test pad 111. And the first end 200 and the first second test pad 111 are in a disconnected state, and the second end 201 of the first test pad 101 and the second test pad 111 are in a connected state.
Therefore, taking the first direction as the X direction, the first offset direction as the-X direction, and the second offset direction as the +x direction as an example, if the second wafer 110 is displaced in the +x direction relative to the first wafer 100, the first second test pad 111 is offset in the +x direction relative to the first terminal 200, the first second test pad 111 is connected to the first terminal 200, and the second test pad 111 is still disconnected from the second terminal 201. Referring to fig. 2, if the second wafer 110 is displaced in the-X direction with respect to the first wafer 100, the first second test pad 111 is displaced in the-X direction with respect to the first terminal 200, the first second test pad 111 is disconnected from the first terminal 200, and the second test pad 111 is connected to the second terminal 201. Obviously, the different offsets between the first wafer 100 and the second wafer 110 in the X direction make the connection state of the second test pad 111 and the first test pad 101 show different variation trends. In this way, according to the connection state of the second test pad 111 and the first test pad 101 in the test structure 120, it can be determined whether the second wafer 110 and the first wafer 100 are aligned and bonded, and determine the offset direction when the second wafer 110 and the first wafer 100 are offset. And according to the width of the overlapping portion of the first test pad 101 and the second test pad 111 in the first direction, the displacement of the second wafer 110 relative to the first wafer 100 can be obtained, and according to the displacement, the bonding between the first wafer 100 and the second wafer 110 in the next semiconductor structure is calibrated, so that the alignment accuracy of the bonding between the first wafer 100 and the second wafer 110 in the semiconductor structure can be improved, and further the performance of the semiconductor structure can be improved.
In addition, the preset value may be the minimum dimension that can be measured by the measuring device, when the first wafer 100 and the second wafer 110 are aligned and bonded, the first length and the second length are the same length that is greater than zero and less than the preset value, so that when the first length is longer and the first second test pad 111 is in a disconnected state, the second end 201 and the second test pad 111 are also in a disconnected state, and no matter in which direction the second wafer 110 is parallel to the first direction relative to the second wafer 110, the measured first wafer 100 and the measured second wafer 110 are in a more accurate displacement relationship relative to the first wafer 100 and the second wafer 110 when the first wafer 100 and the second wafer 110 are aligned and bonded, because if the first length is longer and the second length is shorter, the first end 200 is offset to the first second test pad 111 by a larger displacement amount, the first end 200 and the first second test pad 111 can be connected, and the second end 201 is offset to the second wafer 111 by a smaller displacement amount relative to the second wafer 110, and the measured second end 201 and the second wafer 110 have a more accurate displacement relationship. Therefore, when the bonding is aligned, the first length is the same as the second length, which is beneficial to improving the testing accuracy of the testing structure 120.
The first wafer 100 and the second wafer 110 are wafers with semiconductor devices or circuits fabricated thereon, and in some embodiments, the wafers may be wafers with silicon as a substrate to fabricate semiconductor devices or circuits thereon. In other embodiments, the substrate of the wafer may also be other semiconductor materials or other materials that may be used as a substrate.
The first wafer 100 is bonded to the second wafer 110 such that the semiconductor devices or circuits in the first wafer 100 are electrically connected to the semiconductor devices or circuits in the second wafer 110. Specifically, the first bonding surface of the first wafer 100 and the second bonding surface of the second wafer 110 are disposed opposite to each other and bonded to each other, the first bonding surface may expose a pad that leads out a semiconductor device or circuit in the first wafer 100, the second bonding surface may expose a pad that leads out a semiconductor device or circuit in the second wafer 110, the first wafer 100 is bonded to the second wafer 110, the first bonding surface is in contact with the second bonding surface, the pad on the first bonding surface is in contact with a pad on the corresponding second bonding surface, and connection between the semiconductor device or circuit in the first wafer 100 and the semiconductor device or circuit in the second wafer 110 is achieved by connection between the pad and the pad.
The interface state of the first bonding surface and the second bonding surface has a certain influence on the electrical performance and the structural stability of the bonded semiconductor structure. Therefore, the structural stability of the first wafer 100 and the second wafer 110 may be improved by improving the stress matching degree between the first bonding surface and the second bonding surface, or the structural stability of the bonding interface formed by the first bonding surface and the second bonding surface may be improved by avoiding the occurrence of impurities or bubbles at the bonding interface formed by the first bonding surface and the second bonding surface. In addition, the electrical performance of the semiconductor structure may be improved by improving the alignment accuracy of the first wafer 100 and the second wafer 110.
The test structure 120 in the semiconductor structure provided in the embodiments of the present disclosure is a structure for improving the alignment accuracy of the first wafer 100 and the second wafer 110. The test structure 120 includes a first test pad 101 and at least two second test pads 111 arranged at intervals along a first direction, where the first direction may be any direction parallel to the surface of the first wafer 100 or the second wafer 110, and if the first direction is an X direction, two ends of the first test pad 101 in the first direction and the corresponding two second test pads 111 arranged in the first direction may measure an offset of the second wafer 110 relative to the first wafer 100 in the X direction. Therefore, the first direction may be defined according to the test requirements, so as to measure the displacement of the second wafer 110 relative to the first wafer 100 in any direction parallel to the surface of the first wafer 100 or parallel to the surface of the second wafer 110.
Taking the first direction as the X direction as an example, the second wafer 110 is offset relative to the first wafer 100 in the X direction, where one case is that the second wafer 110 is displaced relative to the first wafer 100 in the +x direction, and another case is that the second wafer 110 is displaced relative to the first wafer 100 in the-X direction, in the semiconductor structure provided in the embodiment of the disclosure, a group of test structures 120 are disposed in the X direction, so that two displacement conditions of the second wafer 110 relative to the first wafer 100 in the X direction can be measured, and thus, there is no need to dispose more test structures 120 in the first wafer 100 and the second wafer 110 to measure more offset directions, so that a larger disposition area for the test structures 120 is avoided in the first wafer 100 and the second wafer 110, which is beneficial to reducing the manufacturing difficulty of the test structures 120.
In some embodiments, referring to fig. 1, the first wafer 100 and the second wafer 110 each include an insulating layer 130, and the material of the insulating layer 130 may be silicon oxide or silicon nitride. The first bonding surface exposes the insulating layer 130 of the first wafer 100, the first test pad 101 is located in the insulating layer 130, and the material of the first test pad 101 is a conductive material, for example, copper, tungsten or aluminum. The second bonding surface exposes the insulating layer 130 of the second wafer 110, and the second test pad 111 is located in the insulating layer 130 of the second wafer 110, and the material of the second test pad 111 is also a conductive material, for example, copper, tungsten or aluminum.
In some embodiments, the material of the first test pad 101 is the same as the material of the second test pad 111. In this way, the first test pad 101 and the second test pad 111 are formed by using the same manufacturing process and using the same source material, and the manufacturing difficulty of the first test pad 101 and the second test pad 111 is reduced.
Referring to fig. 3 to 5, in some embodiments, each of the second test pads 111 exposed from the second bonding surface has the same shape. The second test pad 111 is usually formed by using a photolithography process and an etching process, where the photolithography process is used to define the feature size of the second test pad 111, but when the photoresist of the photolithography process is exposed, the incident light used for exposure may generate undesired reflected light or refracted light, which may cause the photoresist that is not desired to be exposed to light, and after development, the formed photoresist pattern has an error with the photoresist pattern that is preset to be formed. And, the intensity and direction of the reflected light or the refracted light are also related to the photoresist pattern formed in advance, if the photoresist pattern formed in advance is different, the error of the photolithography process is also different, so if the shape of each second test pad 111 is different, the photoresist pattern formed in advance related to the second test pad 111 is also different, and the different photoresist patterns formed in advance may cause different photoresist errors of different second test pads 111, and further cause different setting errors between different second test pads 111, which affects the test accuracy of the second test pad 111. Therefore, each second test pad 111 exposed from the second bonding surface is set to have the same shape, so that different size errors caused by different photoetching errors between the second test pads 111 with different shapes can be avoided, the size errors between the different second test pads 111 can be reduced, and further, the alignment accuracy of wafer bonding can be measured more accurately by using the second test pad 111 with smaller size errors.
In some embodiments, referring to fig. 3, the first test pad 101 exposed from the first bonding surface has a square shape; the second test pad 111 exposed from the second bonding surface is also square, and the length direction of the square first test pad 101 is parallel to the first direction, the width direction is perpendicular to the first direction, and the length direction of the square second test pad 111 is parallel to the first direction, and the width direction is perpendicular to the first direction. In this way, if the second wafer 110 is offset in the first direction relative to the first wafer 100, the pattern of the overlapping portion of the second test pad 111 and the first test pad 101 is square, and the square area of the overlapping portion of the second test pad 111 and the first test pad 101 is in a linear relationship with the displacement amount of the second test pad 111 relative to the first test pad 101 in the first direction, so that the displacement amount of the second wafer 110 offset relative to the first wafer 100 is easier to be deduced according to the square area of the overlapping portion of the second test pad 111 and the first test pad 101, which is beneficial to reducing the measurement difficulty of the displacement amount.
In some embodiments, referring to fig. 4, taking the first direction as the X direction as an example, in a direction perpendicular to the first direction, the first bonding surface exposes a first test pad 101 having a smaller width than the second bonding surface exposes a second test pad 111. The direction perpendicular to the first direction may be the Y direction, in the Y direction, if the width of the first test pad 101 is the same as the width of the second test pad 111, when the first test pad 101 is offset relative to the second test pad 111 in the X direction, and the first test pad 101 is also displaced relative to the second test pad 111 in the Y direction, the overlapping area of the first test pad 101 and the second test pad 111 and the displacement amount of the second test pad 111 relative to the first test pad 101 do not have a relatively simple linear relationship, and only the displacement amount can be obtained according to the width of the first test pad 101 and the second test pad 111 overlapped in the first direction, so that the width of the first test pad 101 is smaller than the width of the second test pad 111 in the direction perpendicular to the first direction, which is beneficial to judging the displacement amount of the first wafer 100 offset relative to the second wafer 110 according to the overlapping area of the first test pad 101 and the second test pad 111, and further beneficial to reducing the test difficulty of the displacement amount.
It can be appreciated that, in some embodiments, referring to fig. 5, in a direction perpendicular to the first direction, the width of the first test pad 101 exposed from the first bonding surface may be larger than the width of the second test pad 111 exposed from the second bonding surface, so that the displacement amount of the first wafer 100 relative to the second wafer 110 can be determined according to the overlapping area of the first test pad 101 and the second test pad 111, which is beneficial to reducing the testing difficulty of the displacement amount.
In some embodiments, the shape of the first test pad 101 exposed by the first bonding surface or the shape of the second test pad 111 exposed by the second bonding surface may also be circular or other shapes.
In some embodiments, referring to fig. 3-5, a semiconductor structure may have at least two sets of test structures 120, wherein a first direction in at least one set of test structures 120 is an X-direction and a first direction in at least one other set of test structures 120 is a Y-direction.
It should be noted that, the Y direction and the X direction are different directions, at least two sets of test structures 120 are disposed in the semiconductor structure, a first direction in one set of test structures 120 is the X direction, a first direction in another set of test structures 120 is the Y direction, the test structures 120 with the first direction being the X direction are used to measure the displacement condition of the second wafer 110 relative to the first wafer 100 in the X direction, and the test structures 120 with the first direction being the Y direction are used to measure the displacement condition of the second wafer 110 relative to the first wafer 100 in the Y direction, so that the displacement condition of the second wafer 110 relative to the first wafer 100 can be measured in multiple directions, thereby being beneficial to improving the alignment accuracy of the first wafer 100 and the second wafer 110 by using the test structures 120 in multiple directions.
In some embodiments, the Y direction is perpendicular to the X direction, and the displacement of the first wafer 100 and the second wafer 110 in all directions parallel to the surface of the first wafer 100 can be measured by combining the displacement measured by the two sets of test structures 120 disposed in the semiconductor structure, so that the alignment accuracy of the first wafer 100 and the second wafer 110 is improved by using the test structures 120.
In some embodiments, referring to fig. 6 and 7, the first test pad 101 further includes a third end 202 and a fourth end 203 arranged along a second direction, and the test structure 120 further includes two second test pads 111 arranged at intervals along the second direction, the first direction being different from the second direction; the third second test pad 111 is adjacent to the third end 202, the fourth second test pad 111 is adjacent to the fourth end 203, the minimum distance between the third second test pad 111 and the third end 202 is a third length, the minimum distance between the fourth second test pad 111 and the fourth end 203 is a fourth length, the third length is equal to the fourth length, and the third length and the fourth length are both greater than zero and smaller than a preset value.
In this way, according to the third end 202, the fourth end 203, the third second test pad 111 and the fourth second test pad 111 which are arranged at intervals in the second direction, the state that the second wafer 110 is offset in the second direction relative to the first wafer 100 and the displacement amount that the second wafer 110 is offset in the second direction relative to the first wafer 100 can be determined, and the displacement condition of the second wafer 110 relative to the first wafer 100 can be measured in multiple directions by using a group of test structures 120, so that there is no need to provide more test structures 120 in the first wafer 100 and the second wafer 110, and a larger setting area is avoided to be reserved for the test structures 120 in the first wafer 100 and the second wafer 110, which is beneficial to reducing the manufacturing difficulty of the test structures 120.
In some embodiments, the Y direction is perpendicular to the X direction, and the displacements of the first wafer 100 and the second wafer 110 in all directions parallel to the surface of the first wafer 100 can be measured by using a set of test structures 120, so that more test structures 120 are avoided from being disposed in the first wafer 100 and the second wafer 110, which is beneficial to reducing the manufacturing difficulty of the test structures 120.
In some embodiments, the third length is equal to the first length. If the third length is longer and the first length is shorter, the test structure 120 can measure the displacement when the second wafer 110 is offset by a larger displacement in the first direction relative to the first wafer 100, and the test structure 120 can measure the displacement when the second wafer 110 is offset by a smaller displacement in the second direction relative to the first wafer 100, so that the positional relationship between the first wafer 100 and the second wafer 110 measured by the test structure 120 in different directions has errors. Similarly, if the first length is longer and the third length is shorter, the positional relationship between the first wafer 100 and the second wafer 110 measured by the test structure 120 in different directions also has an error, so that the first length is the same as the second length when the first wafer 100 and the second wafer 110 are aligned and bonded, which is beneficial to improving the test accuracy of the test structure 120.
In some embodiments, referring to fig. 6 and 7, the maximum length of the first end 200 to the second end 201 is the same as the maximum length of the third end 202 to the fourth end 203. In this way, the difficulty in setting the first test pad 101 and the second test pad 111 is reduced.
In some embodiments, referring to fig. 1, taking the first direction as the X direction as an example, the width of the first test pad 101 may be 100nm to 10000nm, for example, 250nm, 450nm, 500nm, 5400nm, 8900nm, etc. along the first direction. The width of the second test pad 111 may be 100nm to 10000nm, for example, 100nm, 1500nm, 2500nm, 4500nm, 9500nm, etc. Specifically, the widths of the first test pad 101 and the second test pad 111 in the first direction may be reasonably set according to the sizes of the first wafer 100 and the second wafer 110 in the first direction.
In some embodiments, referring to fig. 1, taking the first direction as the X direction as an example, the length of the first test pad 101 is 100nm to 1000nm along the direction perpendicular to the first direction, for example, may be 250nm, 300nm, 450nm, 500nm, 800nm, etc. The second test pad 111 has a length of 100nm to 1000nm, and may be, for example, 450nm, 360nm, 480nm, 550nm, 760nm, or the like. Similarly, the widths of the first test pad 101 and the second test pad 111 in the first direction may be reasonably set according to the sizes of the first wafer 100 and the second wafer 110 in the direction perpendicular to the first direction.
In some embodiments, referring to fig. 1, the semiconductor structure further comprises: a first signal pad 102, the first bonding surface exposing the first signal pad 102; the second signal pad 112, the second bonding surface exposes the second signal pad 112, and the first signal pad 102 is opposite to the second signal pad 112.
The first signal pad 102 may be a pad for providing a test signal for a semiconductor device or circuit in the first wafer 100, and the second signal pad 112 may be a pad for providing a test signal for a semiconductor device or circuit in the second wafer 110, where the opposite first signal pad 102 and second signal pad 112 are connected to each other, so that the semiconductor device or circuit in the first wafer 100 and the semiconductor device or circuit in the second wafer 110 share one signal lead, which is beneficial to reducing complexity of lead layout in a semiconductor structure and reducing manufacturing difficulty of the semiconductor structure.
In some embodiments, referring to fig. 1, in a first direction, the first bonding surface exposes a width of the first signal pad 102 that is the same as a width of the second bonding surface exposes the second signal pad 112. Taking the first direction as the X direction as an example, the first signal pads 102 and the second signal pads 112 with the same width and opposite directions in the first direction can be used as positioning marks in the process of setting the first test pads 101 and the second test pads 111, which is beneficial to accurately setting the first test pads 101 in the first wafer 100 and accurately setting the second test pads 111 in the second wafer 110 by utilizing the existing pads in the semiconductor structure, avoids setting additional positioning marks, and is beneficial to reducing the manufacturing difficulty of the first test pads 101 and the second test pads 111.
In some embodiments, referring to fig. 1, the test structures 120 are adjacent to the first signal pads 102 and the corresponding second signal pads 112. The first signal pad 102 and the second signal pad 112 may also be pads for providing working signals for devices or circuits in the semiconductor structure, and the test structure 120 is disposed adjacent to the first signal pad 102 and opposite to the first signal pad 102, that is, the alignment state of the first signal pad 102 and the second signal pad 112 may be measured by using the test structure 120, and the displacement amount of the second signal pad 112 relative to the first signal pad 102 may be obtained by using the test structure 120, and the first signal pad 102 and the opposite second signal pad 112 may be precisely aligned and bonded according to the displacement amount, so that the connection area between the aligned first signal pad 102 and the second signal pad 112 is larger, which is beneficial to improving the transmission speed of the test signals or working signals through the first test pad 101 and the second test pad 111, and further is beneficial to improving the transmission speed of the test signals in the semiconductor structure, improving the test efficiency, or improving the running speed of devices or circuits in the semiconductor structure, and improving the performance of the semiconductor structure.
In some embodiments, referring to fig. 1, the first signal pad 102 is also disposed within the insulating layer 130 of the first wafer 100, the second signal pad 112 is also disposed within the insulating layer 130 of the second wafer 110, the first signal pad 102 is the same material as the second signal pad 112, and the material of the first signal pad 102 or the second signal pad 112 may include copper, tungsten, or aluminum. Also, the surface of the first wafer 100 opposite to the first bonding surface also exposes the first signal pad 102, and the surface of the second wafer 110 opposite to the second bonding surface also exposes the second signal pad 112, so that it is advantageous to provide an electrical signal to the first signal pad 102 using the exposed first signal pad 102 and to provide an electrical signal to the second signal pad 112 using the exposed second signal pad 112.
In some embodiments, referring to fig. 8, the first wafer 100 has a first middle region 103 and a first edge region 104, the second wafer 110 has a second middle region and a second edge region, the first middle region 103 is opposite to the second middle region, the first edge region 104 is opposite to the second edge region, the first middle region 103 and the opposite second middle region have respective test structures 120, and the first edge region 104 and the opposite second edge region also have respective test structures. The first middle region 103 is a region near the center of the first wafer 100, and the first edge region 104 is a region near the edge of the first wafer 100. The second middle region is a region located near the center of the second wafer 110, and the second edge region is a region near the edge of the second wafer 110.
In this way, the center of the first wafer 100 and the center of the second wafer 110 are aligned and measured by using the test structures 120 in the middle of the first wafer 100 and the second wafer 110, the edge of the first wafer 100 and the edge of the second wafer 110 are aligned and measured by using the test structures 120 on the edge of the first wafer 100 and the edge of the second wafer 110, and the alignment and measurement of the center and the edge can realize the whole alignment and measurement of the first wafer 100 and the second wafer 110, which is beneficial to the accurate measurement of the bonding of the first wafer 100 and the second wafer 110 by using the limited number of test structures 120. It should be noted that the second middle area and the second edge area of the second wafer 110 are similar to the first wafer 100, and the second middle area and the second edge area of the second wafer 110 are not shown.
In some embodiments, the first middle region 103 and the opposing second middle region are provided with multiple sets of test structures 120, and the first edge region 104 and the opposing second edge region are also provided with multiple sets of test structures 120. More test structures 120 are advantageous for improving alignment accuracy of the first wafer 100 and the second wafer 110.
In some embodiments, referring to fig. 9 and 10, the first wafer 100 includes a plurality of first chips 105, and the second wafer 110 includes a plurality of second chips, each first chip 105 being directly opposite a corresponding second chip; part of the first chip 105 and the opposing second chip have corresponding test structures 120.
In this way, not only the displacement of the second wafer 110 relative to the whole first wafer 100 can be measured by using the test structure 120, but also the displacement of the second chip relative to the corresponding first chip 105 can be measured, which is favorable for accurately obtaining the displacement between the second chip and the first chip 105 by using the test structure 120, and further realizing the accurate alignment bonding of the second chip and the first chip 105, and the first chip 105 and the second chip with higher alignment precision are favorable for improving the performance of the semiconductor structure. It should be noted that the second chips of the second wafer 110 are similar to the arrangement of the first chips 105 in the first wafer 100, and thus, the structure of the second chips in the second wafer 110 is not shown.
In some embodiments, referring to fig. 9, the first chip 105 and the second chip each have a chip middle region and a chip edge region, and the chip middle region of the first chip 105 is opposite to the chip middle region of the opposite second chip, and the chip edge region of the first chip 105 is opposite to the chip edge region of the opposite second chip, and the test structure 120 is located in the opposite chip middle region and the opposite chip edge region.
The chip middle region is a region located near the center of the first chip 105 or the second chip, and the chip edge region is a region near the edge of the first chip 105 or the second chip. In order to improve the measurement of the alignment accuracy of the first chip 105 and the second chip opposite to the first chip 105, at least two sets of corresponding test structures 120 may be disposed in a first chip 105 and a second chip opposite to the first chip, and the two sets of test structures 120 may be located in a middle area of the chip and an edge area of the chip, respectively. Therefore, the alignment state between the middle part of the first chip 105 and the middle part of the second chip can be measured by using the test structure 120 in the middle part area of the chip, and the alignment state between the edge of the first chip 105 and the edge of the second chip can be measured by using the test structure 120 in the edge area of the chip, so that the accurate measurement of the bonding alignment condition between the first chip 105 and the right second chip can be facilitated by using the test structure 120.
In some embodiments, referring to fig. 10, the first chip 105 and the second chip each have a chip middle region, the chip middle region of the first chip 105 and the chip middle region of the opposing second chip are opposing, the first wafer 100 further includes a first scribe line 106 at an edge of the first chip 105, the second wafer 110 further includes a second scribe line at an edge of the second chip and opposing the corresponding first scribe line 106, the test structure 120 is located in the opposing chip middle region, and the first scribe line 106 and the opposing second scribe line. The chip middle region is a region located near the center of the first chip 105 or the second chip.
Thus, the alignment state between the middle of the first chip 105 and the middle of the second chip can be measured by using the test structure 120 in the middle area of the chip, and the alignment state between the edge of the first chip 105 and the edge of the second chip can be measured by using the first scribe line 106 at the edge of the chip and the test structure 120 in the second scribe line.
It will be appreciated that in some embodiments, the test structures 120 are the test structures 120 shown in fig. 3 to 5, that is, one set of test structures 120 only tests the offset of the second wafer 110 relative to the first wafer 100 in the first direction, and if, for example, the alignment condition of bonding the first chip 105 and the middle portion of the second chip opposite to the first chip is measured, at least two sets of test structures 120 may be disposed in the middle portion of the first chip 105 and the middle portion of the second chip opposite to the first direction in the two sets of test structures 120 may be the X direction and the Y direction perpendicular to each other, respectively. In this way, the displacement of the middle of the first chip 105 and the middle of the opposite second chip in each direction can be measured. Similarly, the test structures 120 for measuring the displacement of the edge of the first chip 105 and the edge of the opposite second chip in each direction may be provided with at least two sets of test structures 120 with different first directions at the edge of the first chip 105 and the edge of the opposite second chip, and the first directions in the two sets of test structures 120 may be the X direction and the Y direction perpendicular to each other, respectively.
In some embodiments, the separation distance between adjacent test structures 120 may be smaller, in one example, a first chip 105 having adjacent sets of test structures 120 with a second chip facing. In other embodiments, the separation distance between adjacent test structures 120 may be greater, in one example, a first chip 105 having only one set of adjacent test structures 120 with an opposing second chip.
In the semiconductor structure provided in the above embodiment, the semiconductor structure includes the first wafer 100 and the second wafer 110 bonded to each other, and the first bonding surface of the first wafer 100 and the second bonding surface of the second wafer 110 are bonded to each other, the first wafer 100 and the second wafer 110 bonded to each other have the test structure 120 for measuring the alignment deviation between the first wafer 100 and the second wafer 110, the test structure 120 includes one first test pad 101 exposed at the first bonding surface and at least two second test pads 111 exposed at the second bonding surface, and both ends of the first test pad 101 and the two second test pads 111 are arranged at intervals along the first direction for measuring the displacement of the second wafer 110 relative to the first wafer 100 in the first direction. In addition, the first test pad 101 is opposite to the region spaced between the two second test pads 111, the first end 200 of the first test pad 101 corresponds to the first second test pad 111, the second end 201 of the first test pad 101 corresponds to the second test pad 111, the first second test pad 111 is offset by a first length with respect to the first end 200 in a first offset direction parallel to the first direction, the second test pad 111 is offset by a second length with respect to the second end 201 in a second offset direction, the first offset direction and the second offset direction are opposite directions, and the first offset direction is also the direction in which the second test pad 111 points to the first second test pad 111. The first length and the second length are both smaller than a preset value, the preset value may be a minimum dimension that can be measured by the measuring device, so if the first end 200 is connected to the first second test pad 111, it is determined that the second wafer 110 is displaced in the second offset direction relative to the first wafer 100, if the second end 201 is connected to the second test pad 111, it is determined that the second wafer 110 is displaced in the first offset direction relative to the first wafer 100, and according to a partial width of the first test pad 101 and the second test pad 111 that overlap in the first direction, a displacement amount of the second wafer 110 that is offset relative to the first wafer 100 can be obtained. In this way, the test structure 120 can determine whether the second wafer 110 is aligned with the first wafer 100, and obtain the displacement of the second wafer 110 relative to the first wafer 100, and calibrate the bonding of the first wafer 100 and the second wafer 110 in the next semiconductor structure according to the displacement, so as to improve the alignment accuracy of the bonding of the first wafer 100 and the second wafer 110 in the semiconductor structure, thereby being beneficial to improving the performance of the semiconductor structure.
Accordingly, another aspect of the embodiments of the present disclosure further provides a measurement method, which may measure the semiconductor structure provided in the foregoing embodiments. It should be noted that, in the same or corresponding parts as the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, and details will not be repeated.
FIG. 11 is a schematic diagram of a test structure in which a second wafer is offset with respect to a first wafer according to an embodiment of the present disclosure; FIG. 12 is a schematic diagram of another test structure in which a second wafer is offset relative to a first wafer according to an embodiment of the present disclosure; fig. 13 is a schematic diagram of a test structure in which a second wafer is offset with respect to a first wafer according to an embodiment of the disclosure.
Referring to fig. 1, 7, 11 to 13, the measurement method includes: providing a first wafer 100 and a second wafer 110 in the semiconductor structure of any one of the above; attaching the first bonding surface to the second bonding surface for pre-alignment; after the pre-alignment is performed, a connection state between the first test pad 101 and the first second test pad 111 is obtained, and a connection state between the first test pad 101 and the second test pad 111 is obtained, wherein if the first test pad 101 and the first second test pad 111 are in a disconnected state, it is determined that the second wafer 110 is displaced relative to the first wafer 100 in a direction in which the second end 201 points to the first end 200, and if the first test pad 101 and the second test pad 111 are in a disconnected state, it is determined that the second wafer 110 is displaced relative to the first wafer 100 in a direction in which the first end 200 points to the second end 201.
Specifically, referring to fig. 1 and 11, taking the first direction as the X direction, the first offset direction as the-X direction, and the second offset direction as the +x direction as an example, if the first end 200 is disconnected from the first second test pad 111 and the second end 201 is connected to the second test pad 111, it is determined that the second wafer 110 is offset in the-X direction with respect to the first wafer 100.
Referring to fig. 1 and 12, taking the first direction as the X direction, the first offset direction as the-X direction, and the second offset direction as the +x direction as an example, if the first end 200 is connected to the first second test pad 111 and the second end 201 is disconnected from the second test pad 111, it is determined that the second wafer 110 is offset in the +x direction with respect to the first wafer 100.
In some embodiments, the first test pad 101 in the test structure 120 further includes a third end 202 and a fourth end 203, referring to fig. 1 and 13, taking the first direction as the X direction, the first offset direction as the-X direction, the second offset direction as the +x direction, the second direction as the Y direction, the third offset direction as the-Y direction, the fourth offset direction as the +y direction, for example, the third offset direction and the fourth offset direction are opposite directions parallel to the second direction, and the third offset direction is also the direction in which the fourth second test pad 111 points to the third second test pad 111. If the first end 200 is connected to the first second test pad 111, the second end 201 is disconnected from the second test pad 111, and the fourth end 203 is connected to the fourth second test pad 111, and the third end 202 is disconnected from the third second test pad 111, it is determined that the second wafer 110 is offset in the +x direction with respect to the first wafer 100, and the second wafer 110 is also offset in the-Y direction with respect to the first wafer 100.
In addition, according to the overlapping area of the first test pad 101 and the corresponding second test pad 111, the displacement amount of the second wafer 110 shifted relative to the first wafer 100 is obtained by analysis, so that the bonding between the next first wafer 100 and the bonded second wafer 110 is advantageously calibrated according to the displacement amount, so that the first wafer 100 and the second wafer 110 have smaller shift, and the performance of the semiconductor structure is advantageously improved.
In some embodiments, the manner of obtaining the connection state of the first test pad 101 and the specific second test pad 111 includes: measuring the contact resistance of the first test pad 101 and the specific second test pad 111; if the resistance of the contact resistor is greater than or equal to the preset value, it is determined that the first test pad 101 and the specific second test pad 111 are in the disconnected state.
Specifically, a lead may be provided to lead out the first test pad 101 and the second test pad 111, and test currents are provided to the first test pad 101 and the second test pad 111 through the lead, and when the first wafer 100 and the second wafer 110 are aligned and bonded, for example, in the embodiment shown in fig. 7, resistance values of contact resistances of the first test pad 101 and the four second test pads 111 are infinite, and then the first test pad 101 and the four second test pads 111 are in an off state.
Taking the embodiment shown in fig. 13 as an example, if the contact resistance between the first test pad 101 and the first second test pad 111 in the test structure 120 is a specific resistance that can be measured, the contact resistance between the first test pad 101 and the fourth second test pad 111 is also a specific resistance that can be measured, and the contact resistance between the first test pad 101 and the remaining two second test pads 111 is infinite, the first test pad 101 and the first second test pad 111 are in a connection state, the first test pad 101 and the fourth second test pad 111 are in a connection state, the first test pad 101 and the second test pad 111 are in a disconnection state, and the first test pad 101 and the third second test pad 111 are in a disconnection state.
In addition, the larger the contact resistance of the first test pad 101 and the corresponding second test pad 111, the smaller the overlapping area of the first test pad 101 and the corresponding second test pad 111.
In some embodiments, the facing areas of the first test pad 101 and the corresponding second test pad 111 may also be measured by infrared measurement.
In the measurement method provided in the above embodiment, the displacement state of the second wafer 110 relative to the first wafer 100 can be determined by measuring the connection state of the first test pad 101 and the corresponding second test pad 111, and the displacement amount of the second wafer 110 relative to the first wafer 100 can be determined by measuring the overlapping area of the first test pad 101 and the corresponding second test pad 111, so that the bonding between the next first wafer 100 and the bonded second wafer 110 is calibrated by using the measured displacement amount, so that the first wafer 100 and the second wafer 110 have smaller offset, which is beneficial to improving the performance of the semiconductor structure.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Variations and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should therefore be assessed only by that of the appended claims.

Claims (15)

1. A semiconductor structure, comprising:
a first wafer having a first bonding surface;
a second wafer having a second bonding surface bonded to the first bonding surface;
at least one set of test structures, the test structures comprising:
a first test pad, the first bonding surface exposing the first test pad surface, and the first test pad having opposite first and second ends exposed to the first bonding surface in a first direction;
at least two second test pads, two of which are arranged in the second wafer at intervals along the first direction, the second bonding surface exposes the surface of the second test pad, and the first test pad and the two of which are arranged at intervals along the first direction
The spaced apart regions between the second test pads are directly opposite and a first one of said second test pads is adjacent said first end and a second one of said second test pads is adjacent said second end;
the minimum distance between the first second test pad and the first end is a first length, the minimum distance between the second test pad and the second end is a second length, the first length is equal to the second length, and the first length and the second length are both greater than zero and smaller than a preset value.
2. The semiconductor structure of claim 1, wherein each of said second test pads exposed by said second bonding surface is the same shape.
3. The semiconductor structure of claim 1, wherein the first test pad further comprises a third end and a fourth end arranged along a second direction, the test structure further comprising two second test pads arranged at intervals along the second direction, the first direction being different from the second direction;
the third test pad is adjacent to the third end, the fourth test pad is adjacent to the fourth end, the minimum distance between the third test pad and the third end is a third length, the minimum distance between the fourth test pad and the fourth end is a fourth length, the third length is equal to the fourth length, and the third length and the fourth length are both greater than zero and smaller than a preset value.
4. The semiconductor structure of claim 3, wherein the third length is equal to the first length.
5. The semiconductor structure of claim 1, wherein said semiconductor structure has at least two sets of said test structures, wherein said first direction in at least one set of said test structures is an X-direction and said first direction in at least one other set of said test structures is a Y-direction.
6. The semiconductor structure of claim 1, wherein the first wafer has a first middle region and a first edge region, the second wafer has a second middle region and a second edge region, the first middle region is opposite the second middle region, the first edge region is opposite the second edge region, the first middle region and the opposite second middle region have respective test structures, and the first edge region and the opposite second edge region also have respective test structures.
7. The semiconductor structure of claim 1, wherein the first wafer comprises a plurality of first chips and the second wafer comprises a plurality of second chips, each of the first chips being directly opposite a corresponding one of the second chips; and part of the first chip and the opposite second chip are provided with corresponding test structures.
8. The semiconductor structure of claim 7, wherein the first die and the second die each have a die center region and a die edge region, and the die center region of the first die is directly opposite the die center region of the directly opposite second die, and the die edge region of the first die is directly opposite the die edge region of the directly opposite second die, and the test structure is located in the directly opposite die center region and the directly opposite die edge region.
9. The semiconductor structure of claim 7, wherein the first die and the second die each have a die center region, the die center region of the first die and the die center region of the second die facing each other, the first wafer further comprises a first scribe line at an edge of the first die, the second wafer further comprises a second scribe line at an edge of the second die and facing the corresponding first scribe line, the test structure is located in the die center region facing each other, and the first scribe line and the second scribe line facing each other.
10. The semiconductor structure of claim 1, wherein a material of the first test pad is the same as a material of the second test pad.
11. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: a first signal pad, the first bonding surface exposing the first signal pad; the second bonding surface exposes the second signal pad, and the first signal pad is opposite to the second signal pad.
12. The semiconductor structure of claim 11, wherein a width of the first signal pad exposed by the first bonding surface is the same as a width of the second signal pad exposed by the second bonding surface along the first direction.
13. The semiconductor structure of claim 11, wherein the test structure is adjacent to the first signal pad and the corresponding second signal pad.
14. A method of measurement, comprising:
providing the first wafer and the second wafer in the semiconductor structure of any one of claims 1-13;
attaching the first bonding surface and the second bonding surface to perform pre-alignment;
After the pre-alignment is performed, a connection state between the first test pad and the first second test pad is obtained, and a connection state between the first test pad and the second test pad is obtained, wherein if the first test pad and the first second test pad are in a disconnection state, it is judged that the second wafer is displaced relative to the first wafer in a direction that the second end points to the first end, and if the first test pad and the second test pad are in a disconnection state, it is judged that the second wafer is displaced relative to the first wafer in a direction that the first end points to the second end.
15. The method of measuring of claim 14, wherein the manner of obtaining the connection state of the first test pad to a particular second test pad comprises: measuring the contact resistance of the first test pad and the specific second test pad;
and if the resistance value of the contact resistor is larger than or equal to a preset value, judging that the first test pad and the specific second test pad are in a disconnected state.
CN202210918369.5A 2022-08-01 2022-08-01 Semiconductor structure and measuring method Pending CN117542837A (en)

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