JP2839469B2 - Pattern for measuring mask misalignment and method for measuring the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a mask alignment in a manufacturing process of a semiconductor device, and more particularly to a pattern for measuring a mask alignment shift and a measuring method thereof.

[0002]

2. Description of the Related Art Generally, in a lithography process which is one of the manufacturing processes of a semiconductor device, a plurality of masks are used.
A predetermined circuit pattern is formed on a semiconductor substrate. Therefore, conventionally, a monitor pattern is provided on a wafer separately from a circuit pattern for each mask process to measure a mask alignment deviation, and the measurement result is used for wafer lot management and the like.

FIG. 3 shows one of the measuring methods. First,
After a pattern 1 for monitoring is formed on a semiconductor substrate via a first mask, a pattern 2 smaller than the pattern 1 is formed via a second mask. Then, the positional relationship between the pattern 1 and the pattern 2 with respect to the reference position indicated by the dotted line is checked with an optical microscope to visually determine the amount of shift of the mask.

On the other hand, as a measurement method for numerically expressing the amount of mask displacement, a method using a vernier pattern shown in FIG. 4 is known. The vernier pattern 5 is a comb-shaped main scale pattern 3 in which the peak width is W and the valley width is arranged at P1, and a comb-shaped vernier pattern in which the valley width is W and the peak width is arranged at P2 different from P1. The main scale pattern 3 and the sub scale pattern 4 are formed on a semiconductor substrate through different masks. Then, a shift amount of the mask is calculated by observing a shift between the main scale pattern 3 and the sub scale pattern 4 formed on the semiconductor substrate with an optical microscope.

In the method, when no misalignment of the mask occurs, as shown in FIG.
The patterns 3a and 4a, which are the reference patterns at the center of the vernier pattern 4, overlap with each other, and the shift amount of the mask at this time is "0". However, when a mask misalignment occurs, as shown in FIG. 3B, the patterns 3b and 4b other than the patterns 3a and 4a, which are reference patterns of the main scale pattern 3 and the sub scale pattern 4, may overlap. become. At this time, the shift amount of the mask is obtained by counting the number N of patterns from the reference patterns 3a and 4a to the patterns 3b and 4b (N = 2 in this embodiment), and this N is the difference between P1 and P2. Is calculated by multiplying A specific calculation formula is as follows: shift amount = N × (P1−P2).

[0006]

However, any of the above methods has the following problems. For example, in the first method shown in FIG. 3, since the shift of the monitor pattern is visually observed, a long time is required for the inspection, and semiconductor devices manufactured in large quantities are measured for each lot and each wafer. Otherwise, the throughput will be very poor. In addition, since only the positional relationship between the pattern 1 and the pattern 2 is observed, the amount of displacement of the mask cannot be quantified.

In the second method shown in FIG. 4, the amount of mask displacement can be quantified by using the vernier pattern 5. Since the deviation is visually observed, the throughput becomes extremely poor as a result. Further, in order to double the detection accuracy of the mask shift amount, the pitch between the main scale pattern 3 and the sub scale pattern 4 must be narrow, which is difficult in terms of design rules.

[0008] In view of the above problems, an object of the present invention is to provide
An object of the present invention is to provide a measurement pattern capable of electrically measuring a mask misalignment without using an optical microscope, and a measurement method thereof.

[0009]

The present invention has the following configuration to achieve the above object. That is, the mask misalignment measurement pattern of the present invention is the same as the mask misalignment measurement pattern of the semiconductor device formed through at least two mask alignments, and is different from the first conductivity type impurity region formed in different mask alignment steps. And multiple second
And a conductive type impurity region, wherein the plurality of second conductive type impurity regions are arranged around the first conductive type impurity region.

In the mask misalignment measuring pattern according to the present invention, the first conductivity type impurity region has a cross shape, and the plurality of second conductivity type impurity regions have a cross shape of the first conductivity type. It is characterized by being arranged in four regions separated by impurity regions.
Further, in the mask misalignment measuring method according to the present invention, a plurality of impurity regions of the second conductivity type are formed in different mask aligning steps by the first method.
A shift amount is formed by forming around the impurity region of the conductivity type and electrically measuring the breakdown voltage between the plurality of impurity regions of the second conductivity type and the impurity region of the first conductivity type.

According to the mask misalignment measuring pattern of the present invention, a plurality of second conductivity type impurity regions are formed around a first conductivity type impurity region through different mask alignment steps on a surface layer portion of a semiconductor substrate on which a semiconductor element is formed. An impurity region is formed. Then, a withstand voltage is measured by applying a predetermined voltage between the impurity region of the first conductivity type and the plurality of impurity regions of the second conductivity type. Generally, there is a correlation between the breakdown voltage and the distance between the impurity regions, and the distance between the impurity regions between the PN junctions can be obtained from the breakdown voltage.

Since the distance between the impurity regions is electrically measured, the amount of misalignment of the mask alignment can be accurately obtained.

[0013]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention.
It is shown in the plan view of FIG. In the plan view of FIG. 3A, the insulating film and the electrodes are omitted to clarify the mask misalignment measurement pattern. As shown in FIG. 1A, a bipolar transistor and a MOS transistor constituting an integrated circuit (not shown) are formed on a surface layer portion of an N ⁻ type semiconductor substrate 11.
A mask misalignment measurement pattern 12 is formed. Mask misalignment measurement pattern 12 is composed of an impurity region 13 of the N ⁺ type P ⁺ -type impurity regions 14 _{1-14 4.} The N ⁺ -type impurity region 13 and the P ⁺ -type impurity regions 14 _{1-14 4} of are formed in separate steps through a mask used for different masks. Therefore, the relative deviation of the mask alignment is directly reflected in the deviation of the impurity regions 13 and the impurity region 14 _{1-14 4.} In this case, the relative deviation of the mask alignment be formed in any of the previous impurity regions 13 and the impurity region 14 _{1-14 4} is reflected.

[0014] Next, as shown in A-A cross-sectional view of FIG. 1 (b), except for some impurity regions 13 and the impurity region 14 _3, 14 _4, the surface of the semiconductor substrate 11 is covered with an oxide film 15 Have been done. Further, the impurity region 13 and the impurity region 14
_3, the 14 _4, the electrodes 16 and 17 electrically connected through a contact hole of the oxide film 15 is formed.

A method for measuring a shift amount using the mask alignment shift measurement pattern 12 of the present invention will be described. In this embodiment, the impurity region 13 has a regular cross shape, and the region where the measurement pattern is formed is divided into four. The impurity region 14 is arranged so as to be arranged in each of the four divided regions.
_{1-14 4} are collectively formed of a different mask process from the impurity regions 13. After the electrodes 16 and 17 formed on the impurity regions 13 and the impurity region 14 _{1-14 4,} FIG. 1
(B), the measured breakdown voltage between the P-N junction by applying a voltage between the electrodes 16 and 17 are formed by impurity regions 13 and the impurity region 14 _3, 14 _4. In this embodiment, FIG. 1 the breakdown voltage between the impurity regions 13 and the impurity region 14 _{1-14 4}
The measurement is performed between the regions indicated by arrows d1 to d8 in FIG.

The breakdown voltage and distance between the PN junctions are as follows:
For example, there is a certain correlation as shown in FIG. 2, and by measuring the breakdown voltage, the impurity region 13 and the impurity regions 141 to ₁ are measured.
4 ₄ Distance can be calculated. In the case of the correlation shown in FIG. 2, when the value of the breakdown voltage is 17 (V), the distance between the PN junctions is 4 (μm). The actual measurement is performed using the correlation diagram shown in FIG.
3 and the impurity regions 14 ₁ calculates the distance between to 14 _4, x in Figure 1 of the impurity regions 14 _{1-14 4} to the impurity region 13 by comparing each distance, the deviation amount in the y direction of the mask and The direction can be obtained, and as a result, the amount of mask misalignment can be measured.

In particular, the impurity region 13 has a regular cross shape,
Impurity regions 141 to ₁ are arranged so as to be arranged in the divided regions.
4 ₄ since the form can be obtained shift amount and direction of the mask alignment accuracy. In the present embodiment, the impurity regions 14 and the impurity region 13 and N ⁺ -type and a conductive type of the P ⁺ -type impurity regions 1 and the impurity regions 13 and P ⁺ -type
4 may be an N ⁺ conductivity type.

[0018]

As described above, according to the mask misalignment measuring pattern and the method for measuring the misalignment according to the present invention, according to the method of manufacturing a semiconductor device, a different mask aligning step is performed on the surface layer of a semiconductor substrate on which a semiconductor element is formed. Through this, a plurality of second conductivity type impurity regions are formed around the first conductivity type impurity region, and the withstand voltage between the first conductivity type impurity region and the plurality of second conductivity type impurity regions is electrically measured. Then, since each distance is calculated, the shift amount of the mask alignment can be accurately measured.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an embodiment of the present invention.

FIG. 2 is a correlation diagram for explaining the measurement method of the present invention.

FIG. 3 is a plan view showing a conventional method.

FIG. 4 is a plan view showing a conventional method.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 semiconductor substrate 12 mask misalignment measurement pattern 13 first conductivity type impurity region 14 _{1 to} 14 ₄ second conductivity type impurity region polycrystalline silicon film 15 oxide film 16, 17 electrode

Claims (3)

(57) [Claims] In a mask misalignment measurement pattern of a semiconductor device formed through at least two mask alignment steps, a first conductivity type impurity region and a plurality of second conductivity type impurity regions formed in different mask alignment steps are provided. An impurity region, wherein the plurality of second conductivity type impurity regions are arranged around the first conductivity type impurity region. 2. The mask misalignment measurement pattern according to claim 1, wherein the first conductivity type impurity region has a cross shape, and the plurality of second conductivity type impurity regions have a cross shape. A mask misalignment measurement pattern, which is arranged in four regions separated by impurity regions of a mold. 3. A plurality of second conductivity type impurity regions are formed around the first conductivity type impurity regions by different mask alignment steps, and the plurality of second conductivity type impurity regions and the first conductivity type impurities are formed. A mask alignment shift measuring method for calculating a shift amount by electrically measuring a withstand voltage between regions.