KR100187661B1 - Forming method of monitoring bar for semiconductor chip area - Google Patents
Forming method of monitoring bar for semiconductor chip area Download PDFInfo
- Publication number
- KR100187661B1 KR100187661B1 KR1019950052516A KR19950052516A KR100187661B1 KR 100187661 B1 KR100187661 B1 KR 100187661B1 KR 1019950052516 A KR1019950052516 A KR 1019950052516A KR 19950052516 A KR19950052516 A KR 19950052516A KR 100187661 B1 KR100187661 B1 KR 100187661B1
- Authority
- KR
- South Korea
- Prior art keywords
- bar
- critical dimension
- measuring
- forming
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
본 발명은 반도체 소자의 임계치수 측정용 바아 형성 방법에 관한 것으로, 셀 영역과 스크라이브 라인의 토폴러지의 차이에 의해 임계치수가 달라지는 문제점을 해결하기 위하여, 스크라이브 라인(scribe line) 내에 임계치수 측정용 바아(bar)를 형성할 때, 셀 영역에 형성되는 패턴의 다양한 토폴리지(topology)에 대응되는 다수의 바아를 형성하므로써, 반도체 소자의 제조공정에 안정화를 기할 수 있고 다양한 토폴러지별로 모니터링이 가능한 모니터링이 가능한 반도체 소자의 임계치수 측정용 바아 형성방법이 제시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bar for measuring a critical dimension of a semiconductor device. In order to solve the problem of changing the critical dimension due to a difference in the topology of a cell region and a scribe line, a bar for measuring a critical dimension in a scribe line is provided. When forming a bar, by forming a plurality of bars corresponding to various topologies of the pattern formed in the cell region, it is possible to stabilize the manufacturing process of the semiconductor device and to monitor by various topologies A method for forming a bar for measuring the critical dimension of a semiconductor device capable of this is provided.
Description
제1도는 본 발명의 일 실시예에 의한 반도체 소자의 임계치수 측정용 바아가 제2폴리실리콘층에 적용된 경우의 형성방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a method of forming a case where a bar for measuring a critical dimension of a semiconductor device according to an embodiment of the present invention is applied to a second polysilicon layer.
제2도는 액티브 상에 형성된 임계치수 측정용 바아의 평면도.2 is a plan view of a threshold measurement bar formed on an active phase.
제3도는 제1폴리실리콘층 상에 형성된 임계치수 측정용 바아의 평면도.3 is a plan view of a critical dimension measurement bar formed on the first polysilicon layer.
제4도는 제1 및 제2폴리실리콘층 상에 형성된 임계치수 측정용 바아의 평면도.4 is a plan view of a critical dimension measurement bar formed on the first and second polysilicon layers.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film
3 : 제1절연막 4 : 제1폴리실리콘층3: first insulating film 4: first polysilicon layer
5 : 제2절연막 6 : 제2폴리실리콘층5: second insulating film 6: second polysilicon layer
10A, 10B, 10C : 제1 내지 제3임계치수 측정용 바아10A, 10B, 10C: bar for measuring the first to third critical dimensions
본 발명은 반도체 소자의 임계치수 측정용 바아(bar) 형성방법에 관한 것으로, 특히 셀 영역의 토폴러지(topology)를 고려하여 임계치수 측정용 바아를 형성하므로써, 셀 영역에 형성된 패턴의 임계치수를 정확히 알 수 있는 반도체 소자의 임계치수 측정용 바아 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bar for measuring a critical dimension of a semiconductor device, and in particular, by forming a bar for measuring a critical dimension in consideration of the topology of a cell region, a critical dimension of a pattern formed in a cell region is determined. It relates to a method for forming a bar for measuring the critical dimension of a semiconductor device that can be accurately known.
일반적으로, 레티클 제작 후에 설계상 사이즈(size)와 제작된 레티클 사이즈와 오차를 확인하기 위하여, 스크라이브 라인 상에 임계치수 측정용 바아를 만들어 임계치수를 측정한다. 또한, ASIC 소자는 메모리 소자와 달리 셀 내에 반복되는 패턴이 거의 없기 때문에, 반도체 소자의 제조 공정에서 포토마스크 작업 및 식각 공정 후, 임계치수 측정용 바아를 측정하여 셀 내의 패턴 사이즈의 임계치수를 확인한다.In general, in order to check the design size (size) and the manufactured reticle size and error after the reticle fabrication, a critical measurement bar is made on the scribe line to measure the critical dimension. In addition, since ASIC devices have almost no repeating patterns in a cell unlike memory devices, after measuring a photomask and an etching process in a semiconductor device manufacturing process, a measurement bar for measuring a critical dimension measures a critical dimension of a pattern size in a cell. do.
종래의 임계치수 측정용 바아는 셀 영역에 형성된 패턴의 토폴러지를 고려하지 않고 평판과 같은 조건으로 설계하여 스크라이브 라인 내에 만들었다. 이와 같은 방법으로 임계치수 측정용 바아를 형성하게 되면, 레티클 제작을 목적으로 사용할 때에는 문제되지 않지만 반도체 소자의 제조 공정에서는 스크라이브 라인과 셀 영역의 토폴러지가 다르기 때문에 셀 영역의 토폴러지는 높고, 스크라이브 라인 내의 토폴러지는 낮아지게 된다. 이에 따라 포토레지스트 도포시, 셀 영역에서는 얇게 도포되고 스크라이브 라인에는 두껍게 도포되어, 셀과 스크라이브 라인 내의 임계치수 측정용 바아의 임계치수가 다르게 되는 벌크(bulk) 효과가 발생하게 된다.Conventional critical dimension measurement bars are designed in the scribe line under the same conditions as the flat plate without considering the topology of the pattern formed in the cell region. If the bar for measuring the critical dimension is formed in this manner, it is not a problem when used for the purpose of manufacturing the reticle, but in the manufacturing process of the semiconductor device, the topology of the scribe line and the cell region is different, so that the topology of the cell region is high and the scribe The topology in the line is lowered. Accordingly, when the photoresist is applied, it is thinly applied in the cell region and thickly applied to the scribe line, thereby generating a bulk effect in which the critical dimensions of the bar for measuring the critical dimension in the cell and the scribe line are different.
또한, 같은 셀 내에서도 액티브 위의 패턴과 필드 산화막 위의 패턴은 다른 포토바이어스(photo bias)가 적용되기 때문에 종래의 임계치수 측정용 바아는 이러한 경우를 모두 모니터링(monitoring)할 수 없는 문제점이 있다.In addition, since a photo bias is applied to the pattern on the active layer and the pattern on the field oxide layer in the same cell, the conventional bar for measuring the dimension may not monitor all of these cases.
따라서, 본 발명은 셀 영역의 토폴러지를 고려하여 임계치수 측정용 바아를 형성하므로써, 셀 영역에 형성된 패턴의 임계치수를 정확히 측정할 수 있는 반도체 소자의 임계치수 측정용 바아 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method for forming a bar for measuring a critical dimension of a semiconductor device capable of accurately measuring the critical dimension of a pattern formed in a cell region by forming a bar for measuring a critical dimension in consideration of the topology of the cell region. There is a purpose.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 임계치수 측정용 바아 형성방법은 스크라이브 라인 상에 형성되는 임계치수 측정용 바아를 셀 영역에 형성되는 패턴의 다양한 토폴러지에 대응되도록 다수개 형성하는 것을 특징으로 한다.In order to achieve the above object, a method for forming a bar for measuring a critical dimension of a semiconductor device according to the present invention includes forming a plurality of bar for measuring a critical dimension formed on a scribe line so as to correspond to various topologies of a pattern formed in a cell region. Characterized in that.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도는 본 발명의 일 실시예에 의한 반도체 소자의 임계치수 측정용 바아가 제2폴리실리콘층에 적용된 경우의 형성방법을 설명하기 위한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining a method of forming a case where a bar for measuring a critical dimension of a semiconductor device according to an embodiment of the present invention is applied to a second polysilicon layer.
셀 영역의 토폴러지와 스크라이브 라인의 토폴러지를 갖게 하기 위하여, 셀 형성 공정에 따라 스크라이브 라인의 실리콘 기판(1)에도 필드 산화막(2), 제1절 연막(3), 제1폴리실리콘층(4), 제2절연막(5) 및 제2폴리실리콘층(6)이 형성된다.In order to have the topologies of the cell region and the topologies of the scribe lines, the field oxide film 2, the first insulation film 3, and the first polysilicon layer are also applied to the silicon substrate 1 of the scribe line according to the cell formation process. 4), the second insulating film 5 and the second polysilicon layer 6 are formed.
필드 산화막(2)을 형성한 후 제2도에 도시된 바와 같이, 액티브 상에 제1임계치수 측정용 바아(10A)가 형성된다. 제1폴리실리콘층(4)은 제1임계치수 측정용 바아(10A)가 식각되지 않는 범위에서 패턴닝되고, 제3도에 도시된 바와 같이 제1폴리실리콘층(4) 상에 제2임계치수 측정용 바아(10B)가 형성된다.After the field oxide film 2 is formed, as shown in FIG. 2, a first critical dimension measurement bar 10A is formed on the active phase. The first polysilicon layer 4 is patterned in a range in which the first critical dimension measurement bar 10A is not etched, and as shown in FIG. 3, the second threshold on the first polysilicon layer 4 is shown. A water measuring bar 10B is formed.
제2폴리실리콘층(6)은 제1 및 제2임계치수 측정용 바아(10A 및 10B)가 식각되지 않는 범위 내에서 패턴닝되고, 제4도에 도시된 바와 같이 제2폴리실리콘층(6)상에 제3임계치수 측정용 바아(10C)가 형성된다.The second polysilicon layer 6 is patterned within a range where the first and second critical dimension measuring bars 10A and 10B are not etched, and as shown in FIG. 4, the second polysilicon layer 6 The third critical dimension measurement bar 10C is formed on the?
제1 내지 제3임계치수 측정용 바아(10A, 10B 및 10C) 각각의 모양은 T 형으로 형성되며, 각각 임계치수 측정용 바아의 선폭 L1, L2 및 L3 각각은 셀의 해당 패턴의 최소 사이즈(Minimum Feature Size)와 동일하게 하여 셀의 패턴 임계치수를 대체할 수 있게 한다.The shape of each of the first to third critical dimension measuring bars 10A, 10B and 10C is formed in a T shape, and each of the line widths L1, L2 and L3 of the critical dimension measuring bar is the minimum size of the corresponding pattern of the cell ( The minimum feature size) can be used to replace the cell's pattern threshold.
이와 같이, 제2폴리실리콘층에서 임계치수 측정용 바아를 적용할 경우, 임계치수 측정용 바아의 개수는 토톨러지 종류별로 형성한다. 즉, 액티브 상부, 제1폴리실리콘층 상부 및 제2폴리실리콘층 상부에 각각 형성한다. 형성 방법은 액티브 마스트, 제1폴리실리콘층 마스크에서 각각 임계치수 측정용 바아가 형성될 위치가 식각되지 않도록 이미 형성된 임계치수 측정용 바아를 부분적으로 포토레지스트 박스로 덮는다.As described above, when the bar for measuring the critical dimension is applied to the second polysilicon layer, the number of the bar for measuring the critical dimension is formed according to the type of tortoise. That is, it is formed on the active top, the first polysilicon layer and the second polysilicon layer, respectively. The formation method partially covers the already formed threshold measurement bar with a photoresist box so that the position where the threshold measurement bar is to be formed in each of the active mask and the first polysilicon layer mask is not etched.
만약, 제1폴리실리콘층에서 임계치수 측정 바아를 적용할 경우에도, 임계치수 측정 바아의 형성 개수는 토폴러지 종류별로 형성된다. 즉, 액티브 상부 및 필드 산화막 상부에 2종류로 만든다. 형성 방법은 액티브 마스크에서 임계치수 측정용 바아가 형성될 위치가 식각되지 않도록 이미 형성된 임계치수 측정용 바아를 부분적으로 보포레지스트 박스로 덮는다.If the critical dimension measurement bar is applied to the first polysilicon layer, the number of formation of the critical dimension measurement bar is formed for each type of topology. That is, two kinds are formed on the active top and the field oxide film. The forming method partially covers the already formed threshold measurement bar with the bore resist box so that the position where the threshold measurement bar is to be formed in the active mask is not etched.
마찬가지로, 금속 배선 콘택의 경우에는 액티브 상부, 제1폴리실리콘층 상부, 제2폴리실리콘층 상부 및 제3폴리실리콘층 상부 등에 임계치수 측정용 바아를 하부층 상관관계에 따라 종류별로 형성할 수 있다.Similarly, in the case of a metal wiring contact, a critical dimension measuring bar may be formed for each active type, an upper part of the first polysilicon layer, an upper part of the second polysilicon layer, and an upper part of the third polysilicon layer according to the lower layer correlation.
상술한 바와 같이 본 발명에 따르면, 임계치수 측정용 바아의 임계치수 값과 셀 영역의 임계치수 값의 차이를 줄이므로써, 반도체 소자의 제조 공정에 안정화를 기할 수 있으며, 임계치수 측정용 바아의 종류가 토폴러지별로 형성되므로 토폴러지별로 모니터링이 가능한 효과가 있다.According to the present invention as described above, by reducing the difference between the critical dimension value of the threshold measurement bar and the critical dimension value of the cell area, it is possible to stabilize the manufacturing process of the semiconductor device, Since types are formed by topologies, there is an effect that can be monitored by each topology.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950052516A KR100187661B1 (en) | 1995-12-20 | 1995-12-20 | Forming method of monitoring bar for semiconductor chip area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950052516A KR100187661B1 (en) | 1995-12-20 | 1995-12-20 | Forming method of monitoring bar for semiconductor chip area |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970048921A KR970048921A (en) | 1997-07-29 |
| KR100187661B1 true KR100187661B1 (en) | 1999-06-01 |
Family
ID=19441725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950052516A KR100187661B1 (en) | 1995-12-20 | 1995-12-20 | Forming method of monitoring bar for semiconductor chip area |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100187661B1 (en) |
-
1995
- 1995-12-20 KR KR1019950052516A patent/KR100187661B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970048921A (en) | 1997-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7190824B2 (en) | Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same | |
| US6498401B2 (en) | Alignment mark set and method of measuring alignment accuracy | |
| KR20000035176A (en) | Electronic device and semiconductor device, and electrode forming method | |
| KR100187661B1 (en) | Forming method of monitoring bar for semiconductor chip area | |
| US7136520B2 (en) | Method of checking alignment accuracy of patterns on stacked semiconductor layers | |
| JPH0795543B2 (en) | Etching method | |
| KR100519374B1 (en) | Method for measuring overlay of semiconductor device | |
| US20220392768A1 (en) | Patterning method and overlay mesurement method | |
| US6403978B1 (en) | Test pattern for measuring variations of critical dimensions of wiring patterns formed in the fabrication of semiconductor devices | |
| KR0172287B1 (en) | Focusing measurement of exposure apparatus and reiteration accuracy by detecting mark | |
| US20230378082A1 (en) | Overlay mark | |
| KR100232216B1 (en) | Capacitor manufacturing method using thr over lay pattern for align measurement | |
| KR100213227B1 (en) | Overlay key of semiconductor apparatus and manufacturing method of the same | |
| KR20060107653A (en) | Semiconductor device having overlay mark of multi-layer | |
| KR20070038301A (en) | Mark for measuring overlay | |
| KR100881813B1 (en) | A method for forming a overlay vernier of a semiconductor device | |
| KR100232236B1 (en) | Method for making overlay pattern for measuring allignment | |
| JP2839469B2 (en) | Pattern for measuring mask misalignment and method for measuring the same | |
| KR100304441B1 (en) | Forming method for a align mark of semiconductor device | |
| KR100564563B1 (en) | Semiconductor device having multi-layered overlay key structure | |
| KR100542692B1 (en) | Overlap Error Mark | |
| TWI424466B (en) | Overlay mark and manufacturing method thereof | |
| KR100668730B1 (en) | Overlay Key of Semiconductor Device | |
| KR20070071657A (en) | Method for forming overlay vernier of semiconductor device | |
| KR100527558B1 (en) | A method for forming a overlay vernier of a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20061211 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |