KR100527558B1 - A method for forming a overlay vernier of a semiconductor device - Google Patents
A method for forming a overlay vernier of a semiconductor device Download PDFInfo
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- KR100527558B1 KR100527558B1 KR10-2003-0096362A KR20030096362A KR100527558B1 KR 100527558 B1 KR100527558 B1 KR 100527558B1 KR 20030096362 A KR20030096362 A KR 20030096362A KR 100527558 B1 KR100527558 B1 KR 100527558B1
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- forming
- storage electrode
- mark
- electrode contact
- overlap mark
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
- H01L2223/5446—Located in scribe lines
Abstract
본 발명은 반도체소자의 중첩마크 형성방법에 관한 것으로, 중첩마크의 선명도를 증가시켜 중첩도 측정을 용이하게 실시할 수 있도록 하기 위하여, 중첩마크 영역에 중첩마크를 형성하는 방법에 있어서, 소자분리막이 없는 중첩마크 영역 상에 게이트전극 물질층을 오픈하여 단차를 형성하고 상기 단차를 포함한 전체표면상부에 저장전극 콘택홀 층간절연막을 형성한 다음, 저장전극 콘택마스크를 이용한 사진식각공정으로 상기 층간절연막을 식각하여 바아 인 박스 중첩마크의 바깥바아와 같은 평면구조의 저장전극 콘택홀을 형성하고 전체표면상부에 상기 게이트전극 물질층의 단차 및 저장전극 콘택홀의 단차가 형성된 저장전극용 산화막을 형성하여 상기 바깥바아를 형성함으로써 중첩마크의 선명도를 향상시키고 그에 따른 중첩도 측정을 용이하게 하며 후속 공정의 공정마진을 향상시키고 반도체소자의 고집적화를 용이하게 하는 기술이다.The present invention relates to a method for forming a superimposed mark of a semiconductor device, in order to increase the sharpness of the superimposed mark so that the superimposition can be easily measured, in the method of forming an overlap mark in the superimposed mark region, A step is formed by opening a gate electrode material layer on the non-overlapping mark region, and a storage electrode contact hole interlayer insulating film is formed on the entire surface including the step, and then the interlayer insulating film is formed by a photolithography process using a storage electrode contact mask. Etching is performed to form a storage electrode contact hole having a planar structure as an outer bar of a bar overlapping box, and an oxide film for the storage electrode having a step of the gate electrode material layer and a step of the storage electrode contact hole formed on an entire surface thereof. By forming a bar, the sharpness of the overlapping mark is improved and the overlapping measurement is easy. And to a technique that improves the processing margin in the subsequent steps and facilitate the higher integration of semiconductor devices.
Description
본 발명은 반도체소자의 중첩마크 형성방법에 관한 것으로, 특히 반도체소자의 저장전극 형성공정시 형성되는 중첩마크의 계측 능력을 향상시킬 수 있도록 하는 기술에 관한 것이다.The present invention relates to a method of forming an overlap mark of a semiconductor device, and more particularly, to a technique for improving the measurement capability of the overlap mark formed during a storage electrode forming process of a semiconductor device.
일반적으로, 중첩마크 ( overlay vernier ) 는 반도체소자의 셀부와 같은 형태로 여유면적이 있는 스크라이브 라인 ( scribe line ) 과 주변회로부에 형성하되, 셀부와 같은 공정으로 형성한다.In general, an overlay vernier is formed in a scribe line and a peripheral circuit part having a free area in the same shape as a cell part of a semiconductor device, and is formed by the same process as a cell part.
도 1 은 저장전극용 바아 인 박스 ( bar in box ) 형태의 중첩마크 형성공정시 사용되는 중첩마크 영역만을 도시한 평면도이다. FIG. 1 is a plan view illustrating only an overlap mark region used in a process of forming an overlap mark in the form of a bar in box for a storage electrode.
도 1 을 참조하면, 반도체기판(도시안됨)에 활성영역을 정의하는 소자분리막(11)을 형성한다. Referring to FIG. 1, an isolation layer 11 defining an active region is formed on a semiconductor substrate (not shown).
상기 반도체기판 상의 다른 부분에 중첩키를 형성하며 상기 중첩마크 영역을 매립하는 절연막(13)을 형성한다. An insulating key 13 is formed in another portion on the semiconductor substrate to fill up the overlap mark region.
그 다음, 상기 절연막(13)을 포함하는 전체표면상부에 게이트전극용 물질층(15)을 형성한다. Next, a gate electrode material layer 15 is formed on the entire surface including the insulating layer 13.
이때, 상기 중첩마크 영역의 상측에도 상기 게이트전극용 물질층(15)이 형성된다. In this case, the gate electrode material layer 15 is also formed on the overlap mark region.
그리고, 상기 게이트전극용 물질층(15) 상에 바아 인 박스 ( bar in box ) 형태의 바깥 바아인 제1중첩마크(17)를 형성한다. The first overlap mark 17, which is an outer bar in the form of a bar in box, is formed on the gate electrode material layer 15.
이때, 상기 제1중첩마크(17)의 형성공정인 저장전극 콘택 공정의 식각공정시 식각깊이가 깊어 상기 게이트전극용 물질층(15)이 식각되거나 상기 제1중첩마크(17)의 선명도가 떨어지게 된다. In this case, the etching depth of the storage electrode contact process, which is the process of forming the first overlap mark 17, is deep so that the gate electrode material layer 15 is etched or the sharpness of the first overlap mark 17 is inferior. do.
후속 공정으로 상기 바아 인 박스 중첩마크의 안박스로 사용되는 제2중첩마크(19)를 형성함으로써 상기 제1중첩마크(17)와 제2중첩마크(19)로 형성되는 바아 인 박스 중첩마크를 형성한다. In a subsequent process, the bar overlapping mark formed by the first overlap mark 17 and the second overlap mark 19 is formed by forming a second overlap mark 19 used as an inner box of the bar in box overlap mark. Form.
도 2 는 상기 도 1 의 중첩마크 영역에 형성된 바아 인 박스 중첩마크를 도시한 평면 셈사진 및 신호 흐름도를 도시한 것이다. FIG. 2 is a planar swatch and signal flow diagram illustrating a bar in box overlap mark formed in the overlap mark region of FIG. 1.
이상에서 설명한 바와 같이 종래기술에 따른 반도체소자의 중첩마크 형성방법은, 도 2 와 같은 중첩마크를 형성하지만 신호 흐름도의 분석시 바아 인 박스 중첩마크의 바깥 바아의 신호가 작게 나타나 중첩마크의 선명도가 떨어지고 그에 따른 중첩도를 저하시키는 문제점이 있다. As described above, in the method of forming a superimposed mark of a semiconductor device according to the prior art, the superimposed mark as shown in FIG. There is a problem of falling and thereby reducing the degree of overlap.
본 발명의 상기한 종래기술의 문제점을 해결하기 위하여, 중첩마크 영역에 소자분리막 없이 게이트전극 물질층의 패터닝시 상기 중첩마크 영역을 오픈하여 후속 공정으로 중첩마크를 형성함으로써 선명도를 향상시키고 그에 따른 반도체소자의 중첩도를 향상시킬 수 있도록 하는 반도체소자의 중첩마크 형성방법을 제공하는데 그 목적이 있다. In order to solve the above problems of the prior art of the present invention, when the gate electrode material layer is patterned without an isolation layer in the overlap mark region, the overlap mark region is opened to form a superimposition mark in a subsequent process to improve the sharpness and thereby the semiconductor. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming an overlap mark of a semiconductor device to improve the degree of overlap of devices.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 중첩마크 형성방법은, In order to achieve the above object, the method of forming an overlap mark of a semiconductor device according to the present invention,
중첩마크 영역에 중첩마크를 형성하는 방법에 있어서,In the method of forming an overlap mark in the overlap mark area,
소자분리막이 없는 중첩마크 영역 상에 게이트전극 물질층을 오픈하여 단차를 형성하는 공정과,Forming a step by opening the gate electrode material layer on the overlap mark region without the device isolation film;
상기 단차를 포함한 전체표면상부에 저장전극 콘택홀 층간절연막을 형성하는 공정과,Forming a storage electrode contact hole interlayer insulating film over the entire surface including the step;
저장전극 콘택마스크를 이용한 사진식각공정으로 상기 층간절연막을 식각하여 바아 인 박스 중첩마크의 바깥바아와 같은 평면구조의 저장전극 콘택홀을 형성하는 공정과,Forming a storage electrode contact hole having a planar structure such as an outer bar of the overlapped bar in box by etching the interlayer insulating layer by a photolithography process using a storage electrode contact mask;
전체표면상부에 상기 게이트전극 물질층의 단차 및 저장전극 콘택홀의 단차가 형성된 저장전극용 산화막을 형성하여 상기 바깥바아를 형성하는 공정을 포함하는 것을 제1특징으로 한다. The first feature includes forming an outer bar by forming an oxide film for a storage electrode having a step difference between the gate electrode material layer and a storage electrode contact hole formed on an entire surface thereof.
또한, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 중첩마크 형성방법은, In addition, in order to achieve the above object, the method of forming an overlap mark of a semiconductor device according to the present invention,
중첩마크 영역에 중첩마크를 형성하는 방법에 있어서,In the method of forming an overlap mark in the overlap mark area,
소자분리막이 없는 중첩마크 영역 상에 게이트전극 물질층을 오픈하여 단차를 형성하는 공정과,Forming a step by opening the gate electrode material layer on the overlap mark region without the device isolation film;
상기 단차를 포함한 전체표면상부에 저장전극 콘택홀 층간절연막을 형성하는 공정과,Forming a storage electrode contact hole interlayer insulating film over the entire surface including the step;
저장전극 콘택마스크를 이용한 사진식각공정으로 상기 층간절연막을 식각하여 박스 인 박스 중첩마크의 바깥박스와 같은 평면구조의 저장전극 콘택홀을 형성하는 공정과,Forming a storage electrode contact hole having a planar structure such as an outer box of a box-in-box overlap mark by etching the interlayer insulating layer by a photolithography process using a storage electrode contact mask;
전체표면상부에 상기 게이트전극 물질층의 단차 및 저장전극 콘택홀의 단차가 형성된 저장전극용 산화막을 형성하여 상기 바깥바아를 형성하는 공정을 포함하는 것을 제2특징으로 한다. And a step of forming the outer bar by forming an oxide film for the storage electrode having the step of the gate electrode material layer and the step of the storage electrode contact hole formed on an entire surface thereof.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3 및 도 4 는 본 발명의 실시예에 따른 반도체소자의 중첩마크 형성방법을 도시한 평면도 및 신호 흐름도이다.3 and 4 are a plan view and a signal flow diagram illustrating a method of forming an overlap mark of a semiconductor device according to an embodiment of the present invention.
상기 도 3 은 저장전극용 바아 인 박스 ( bar in box ) 형태의 중첩마크 형성공정시 사용되는 중첩마크 영역만을 도시한 평면도이다. 3 is a plan view illustrating only an overlap mark area used in a process of forming an overlap mark in the form of a bar in box for a storage electrode.
도 3 을 참조하면, 활성영역을 정의하는 소자분리막의 형성공정시 중첩마크 영역에 소자분리막을 형성하지 않고 반도체기판(21) 그대로 유지한다. Referring to FIG. 3, the semiconductor substrate 21 is maintained without forming an isolation layer in an overlap mark region during the formation of the isolation layer defining an active region.
상기 반도체기판(21) 상의 다른 부분에 중첩키를 형성하며 상기 중첩마크 영역을 매립하는 절연막(23)을 형성한다. An insulating key 23 is formed in another portion of the semiconductor substrate 21 to fill the overlap mark region.
그 다음, 상기 절연막(23)을 포함하는 전체표면상부에 게이트전극용 물질층(도시안됨)을 형성한다. Next, a gate electrode material layer (not shown) is formed on the entire surface including the insulating film 23.
게이트전극 마스크(도시안됨)를 이용한 사진식각공정시 상기 중첩마크 영역의 게이트전극용 물질층을 식각하여 상기 절연막(23)을 오픈시켜 게이트전극 물질층의 오픈영역(25)을 형성하여 인접한 게이트전극 물질층과 단차를 갖게 된다. In the photolithography process using a gate electrode mask (not shown), the gate electrode material layer of the overlap mark region is etched to open the insulating layer 23 to form an open region 25 of the gate electrode material layer to form an adjacent gate electrode. It has a step with the material layer.
그 다음, 전체표면상부에 바아 인 박스 ( bar in box ) 형태의 바깥 바아인 제1중첩마크(27)를 형성한다. Then, the first overlap mark 27, which is an outer bar in the form of a bar in box, is formed on the entire surface.
이때, 상기 제1중첩마크(27)의 형성공정은 다음과 같이 실시한다. At this time, the process of forming the first overlap mark 27 is performed as follows.
먼저, 상기 게이트전극용 물질층의 식각공정으로 단차가 형성된 중첩마크 영역을 포함한 전체표면상부에 저장전극 콘택용 층간절연막을 증착한다. First, an interlayer insulating layer for a storage electrode contact is deposited on the entire surface including an overlap mark region in which a step is formed by etching the gate electrode material layer.
저장전극 콘택마스크를 이용한 사진식각공정으로 상기 저장전극용 콘택용 층간절연막을 식각하여 저장전극 콘택홀을 형성하되, 상기 저장전극 콘택홀은 상기 제1중첩마크(27)와 같은 평면구조로 형성한다. A storage electrode contact hole is formed by etching the interlayer insulating layer for the storage electrode contact by a photolithography process using a storage electrode contact mask, wherein the storage electrode contact hole is formed in the same planar structure as the first overlap mark 27. .
이때, 제1중첩마크(27)는 상하좌우에 각각 형성되는 바아가 2×20 ㎛ 의 크기로 형성된 것이다. At this time, the first overlap marks 27 are formed in the size of 2 × 20 ㎛ bars respectively formed on the top, bottom, left and right.
그 다음, 상기 바아 인 박스 중첩마크의 안박스로 사용되는 제2중첩마크(29)를 형성함으로써 상기 제1중첩마크(27)와 제2중첩마크(29)로 형성되는 바아 인 박스 중첩마크를 형성한다. Next, by forming a second overlap mark 29 used as an inner box of the bar in box overlap mark, a bar in box overlap mark formed of the first overlap mark 27 and the second overlap mark 29 is formed. Form.
이때, 상기 제2중첩마크(29)는 다음과 같은 공정으로 형성한다. In this case, the second overlap mark 29 is formed by the following process.
먼저, 상기 저장전극 콘택홀로 형성된 제1중첩마크(27)의 단차가 그대로 구비되는 저장전극용 산화막을 전체표면상부에 증착한다. First, an oxide film for a storage electrode having a level difference between the first overlap marks 27 formed as the storage electrode contact hole is deposited on the entire surface.
후속 공정으로, 상기 저장전극용 산화막 상에 10×10 ㎛ 크기로 상기 안박스 형성된 감광막패턴을 형성함으로써 제2중첩마크(29)를 형성한다. In a subsequent step, the second overlap mark 29 is formed by forming the unboxed photosensitive film pattern having a size of 10 × 10 μm on the storage electrode oxide film.
도 4 는 상기 도 3 의 공정으로 형성된 바아 인 박스의 중첩마크를 도시한 평면 셈사진과 신호 흐름도를 도시한 것으로서, 바깥바아의 신호가 ⓑ 와 같이 크게 나타나 상기 바깥바아를 보다 선명하게 도시하며 후속 공정에서 중첩도를 정확하게 측정할 수 있도록 형성한다. 4 is a planar swatch and signal flow diagram showing overlapping marks of a bar in box formed by the process of FIG. 3, wherein the signal of the outer bar is large as shown in ⓑ to more clearly show the outer bar, and Form so that the degree of overlap can be measured accurately in the process.
상기 바깥바아의 신호 ⓑ 가 종래기술인 도 2 의 바깥바아 신호 ⓐ 보다 크게 나타나므로, 그에 따른 선명도 차이가 나타나게 된다. Since the signal ⓑ of the outer bar is larger than the outer bar signal ⓐ of FIG. 2, the sharpness difference is shown.
본 발명의 다른 실시예는 박스 인 박스 형태로 중첩마크를 형성하는 것이다. Another embodiment of the present invention is to form an overlap mark in the form of a box in a box.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 중첩마크 형성방법은, 소자분리막 형성공정시 중첩마크 영역의 식각공정없이 게이트전극 물질층 형성공정시 중첩마크 영역을 오픈한 다음 후속 공정으로 저장전극 형성공정시 바아 인 박스 형태의 중첩마크를 형성함으로써 중첩마크의 선명도를 향상시킬 수 있고 그에 따른 반도체소자의 중첩도를 정확하게 측정할 수 있도록 하여 반도체소자의 후속 공정을 용이하게 하는 효과를 제공한다. As described above, in the method of forming an overlap mark of a semiconductor device according to the present invention, the overlap mark region is opened during the gate electrode material layer forming process without etching the overlap mark region during the device isolation film forming process, and then the storage electrode is formed in a subsequent process. By forming a superimposed mark in the form of a bar-in box during the process, the sharpness of the superimposed mark can be improved and the superimposition of the semiconductor device can be accurately measured, thereby facilitating subsequent processing of the semiconductor device.
도 1 은 종래기술에 따른 저장전극용 중첩마크의 형성공정시 각층에서의 중첩마크 영역을 도시한 평면도.1 is a plan view showing the overlapping mark area in each layer during the forming process of the overlapping mark for the storage electrode according to the prior art.
도 2 는 상기 도 1 중첩마크 영역의 각층 형성공정으로 형성된 중첩마크를 도시한 것으로, 상측은 평면 셈사진을 도시하고 하측은 그에 따른 신호의 강도를 도시한 신호의 흐름도.FIG. 2 is a diagram illustrating overlapping marks formed by the process of forming each layer of the overlapping mark region of FIG. 1, in which an upper side shows a planar image and a lower side shows a signal intensity accordingly; FIG.
도 3 은 본 발명에 따른 저장전극용 중첩마크의 형성공정시 각층에서의 중첩마크 영역을 도시한 평면도.Figure 3 is a plan view showing the overlapping mark area in each layer during the formation process of the overlapping mark for the storage electrode according to the present invention.
도 4 는 상기 도 3 중첩마크 영역의 각층 형성공정으로 형성된 중첩마크를 도시한 것으로, 상측은 평면 셈사진을 도시하고 하측은 그에 따른 신호의 강도를 도시한 신호의 흐름도.FIG. 4 is a flowchart illustrating overlapping marks formed by forming layers in the overlapping mark region of FIG. 3, in which an upper side shows a planar image and a lower side shows a signal intensity accordingly; FIG.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 소자분리막 13,23 : 절연막11 element isolation film 13,23 insulation film
15 : 게이트전극 물질층 17,27 : 제1중첩마크15: gate electrode material layer 17, 27: first overlap mark
19,29 : 제2중첩마크 21 : 반도체기판19,29: second overlap mark 21: semiconductor substrate
25 : 게이트전극 물질층의 오픈 영역25: open area of the gate electrode material layer
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