JPS627692B2 - - Google Patents
Info
- Publication number
- JPS627692B2 JPS627692B2 JP57156254A JP15625482A JPS627692B2 JP S627692 B2 JPS627692 B2 JP S627692B2 JP 57156254 A JP57156254 A JP 57156254A JP 15625482 A JP15625482 A JP 15625482A JP S627692 B2 JPS627692 B2 JP S627692B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- mask
- monitor pattern
- alignment
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Weting (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法に係り、主と
して高周波高出力トランジスタを対象として、マ
スク合せを容易にし、マスク合せ時間の短縮とそ
の後の最適のエツチングを見出し得るようにした
半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, mainly for high-frequency, high-output transistors, to facilitate mask alignment, shorten mask alignment time, and find optimal etching thereafter. The present invention relates to a method for manufacturing a semiconductor device.
従来、高周波トランジスタの高周波特性を向上
させるためには、ベース幅、ベース抵抗、コレク
タ容量等を小さくする必要がある。したがつて、
高周波トランジスタを製造する際には、高精度の
加工技術を必要とする。この加工技術として、従
来、ホトマスクを使用するホトエツチング技術が
知られており、数μ程度の微小パターンの加工が
可能である。 Conventionally, in order to improve the high frequency characteristics of a high frequency transistor, it is necessary to reduce the base width, base resistance, collector capacitance, etc. Therefore,
Manufacturing high-frequency transistors requires high-precision processing technology. As a technique for this processing, a photoetching technique using a photomask is conventionally known, and it is possible to process a minute pattern of several micrometers.
しかし、高周波トランジスタの高周波特性をあ
げるためには、1μ程度の微小パターンが必要で
あるが、マスクアライメント精度、オーバエツチ
ング等の制約があり、ホトマスクの精度が向上
し、たとえ1μ程度の素子パターンを有するホト
マスクが出来たとしても、それをウエハに写真製
版する際に上記のアライメントマークの精度、オ
ーバエツチング等により、ホトマスクの精度その
ままを、ウエハに転写することは困難である。 However, in order to improve the high-frequency characteristics of high-frequency transistors, a micropattern of about 1μ is required, but there are constraints such as mask alignment accuracy and overetching. Even if a photomask with the same characteristics is made, it is difficult to transfer the same accuracy of the photomask onto the wafer due to the accuracy of the alignment marks, overetching, etc. when photoengraving the photolithography onto the wafer.
この発明は以上のような点に鑑みてなされたも
ので、ホトエツチング工程における最適エツチン
グを見出し得るためのモニタパターンとそのモニ
タパターン部にアライメントマーク群を設けたマ
スクを用いることによつてマスク合わせの容易
で、最適エツチングが可能な半導体装置の製造方
法を提供することを目的としている。 This invention was made in view of the above points, and it is possible to perform mask alignment by using a monitor pattern for finding the optimum etching in the photoetching process and a mask having a group of alignment marks on the monitor pattern. The object of the present invention is to provide a method for manufacturing a semiconductor device that is easy and allows optimal etching.
第1図はこの発明に用いるホトマスクの一例を
示す平面図で、このホトマスク1はパターン部2
に本来製造しようとするトランジスタのパターン
を配置し、その中に所要幅のバー状のモニタパタ
ーン3を配置し、そのモニタパターン部3の一部
にアライメントマーク群4を配置している。 FIG. 1 is a plan view showing an example of a photomask used in the present invention.
A pattern of a transistor to be manufactured is placed therein, a bar-shaped monitor pattern 3 of a required width is placed therein, and an alignment mark group 4 is placed in a part of the monitor pattern portion 3.
第2図は第1図に示したホトマスク1を用いて
写真製版した半導体ウエハを示す平面図で、ウエ
ハ5上のモニタパターン6およびアライメントマ
ーク群7はそれぞれ第1図のモニタパターン3お
よびアライメントマーク群4を写真製版で転写し
たものである。このときのモニタパターン6は後
述のエツチングが最適の段階に達したことを目視
で観測できる十分な寸法を有するように設計され
る。アライメントマーク群7には大略のマスク合
わせ用、高精度マスク合わせ用、及びマスク自体
のピツチずれ検出用などのアライメントマークが
含まれる。 FIG. 2 is a plan view showing a semiconductor wafer photoengraved using the photomask 1 shown in FIG. This is a photolithography transfer of Group 4. The monitor pattern 6 at this time is designed to have sufficient dimensions to enable visual observation of when etching, which will be described later, has reached an optimal stage. The alignment mark group 7 includes alignment marks for general mask alignment, high precision mask alignment, and pitch shift detection of the mask itself.
第3図は第2図の−線での拡大部分断面図
で、半導体ウエハ8上の酸化膜9の表面上に塗着
されたホトレジスト膜10に第1図に示したよう
なマスクを用いて露光現像した状態を示す。 FIG. 3 is an enlarged partial cross-sectional view taken along the - line in FIG. 2, in which a mask as shown in FIG. Shows the state after exposure and development.
第4図は第3図のホトレジスト膜10をマスク
として酸化膜9を理想的にエツチングされた状態
を示す。 FIG. 4 shows a state in which the oxide film 9 has been ideally etched using the photoresist film 10 of FIG. 3 as a mask.
第5図は従来のエツチング過程でオーバエツチ
ングに陥つた状態を示す。このようなオーバエツ
チングが生じるのを防止するために、この発明で
はモニタパターン6を用い、エツチング液である
フツ酸が酸化膜9をエツチングしている間はフツ
酸が酸化膜9によくなじんでいるが、第4図に示
すようにウエハ8表面が露出すると、フツ酸がウ
エハ8になじまずはじくのを目視することによつ
て最適エツチング状態でエツチング停止させるこ
とができる。このような目視観察はトランジスタ
等の実用の半導体素子のパターン部分では、パタ
ーンが微細であり目視観察は困難で、所要寸法の
モニタパターンが必要である。 FIG. 5 shows a state where over-etching occurs during the conventional etching process. In order to prevent such overetching from occurring, the present invention uses a monitor pattern 6 to ensure that while the hydrofluoric acid, which is an etching solution, is etching the oxide film 9, the hydrofluoric acid is well adapted to the oxide film 9. However, when the surface of the wafer 8 is exposed as shown in FIG. 4, the etching can be stopped in the optimum etching state by visually observing that the hydrofluoric acid does not blend into the wafer 8 and is repelled. Such visual observation is difficult in the pattern portion of a practical semiconductor element such as a transistor because the pattern is minute, and a monitor pattern of a required size is required.
以上説明したように、この発明では所要寸法の
モニタパターンを設けたのでジヤストエツチング
を目視観察することができ、更にモニタパターン
部にアライメントマーク群を設けたのでマスク合
わせ時にアライメントマークの位置を捜すのが容
易であり、マスク合わせ時間の短縮と高精度のエ
ツチング加工が可能である。 As explained above, in this invention, since a monitor pattern with the required dimensions is provided, it is possible to visually observe the just etching.Furthermore, since a group of alignment marks are provided in the monitor pattern section, the position of the alignment mark can be searched for when aligning the mask. This makes it possible to shorten mask alignment time and perform highly accurate etching.
第1図はこの発明に用いるホトマスクの一例を
示す平面図、第2図は第1図に示したホトマスク
を用いて写真製版した半導体ウエハを示す平面
図、第3図は第2図の−線での拡大部分断面
図、第4図は第3図のホトレジスト膜をマスクと
してウエハ上の酸化膜を理想的にエツチングした
状態を示す断面図、第5図は従来のエツチング過
程でオーバエツチングに陥つた状態を示す断面図
である。
図において、1はマスク、3,6はモニタパタ
ーン、4,7はアライメントマーク群、5,8は
半導体ウエハ、9は絶縁膜、10はホトレジスト
膜である。なお、図中同一符号は同一または相当
部分を示す。
FIG. 1 is a plan view showing an example of a photomask used in the present invention, FIG. 2 is a plan view showing a semiconductor wafer photoengraved using the photomask shown in FIG. 1, and FIG. 3 is a plan view showing the - line in FIG. 4 is a cross-sectional view showing the oxide film on the wafer ideally etched using the photoresist film of FIG. 3 as a mask, and FIG. FIG. 3 is a sectional view showing the ivy state. In the figure, 1 is a mask, 3 and 6 are monitor patterns, 4 and 7 are alignment mark groups, 5 and 8 are semiconductor wafers, 9 is an insulating film, and 10 is a photoresist film. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
版技術で所要パターンに形成されたホトレジスト
膜を介して弗酸でエツチングする工程を含む半導
体装置の製造方法において、上記ホトレジスト膜
に所要寸法の開口のモニタパターンとこのモニタ
パターン形成部の一部にアライメントマーク群と
を形成するマスクを用い、上記モニタパターン部
の上記絶縁膜のエツチングが完了したことを上記
弗酸が上記半導体ウエハによつてはじかれるのを
目視観察して認識できるようにするとともに、マ
スクアライメントを容易ならしめたことを特徴と
する半導体装置の製造方法。1. In a method for manufacturing a semiconductor device that includes a step of etching with hydrofluoric acid through a photoresist film formed in a desired pattern by photolithography on an insulating film formed on a semiconductor wafer, an opening of a desired size is formed in the photoresist film. Using a mask that forms a monitor pattern and a group of alignment marks on a part of the monitor pattern forming area, the hydrofluoric acid is repelled by the semiconductor wafer to confirm that the etching of the insulating film in the monitor pattern area is completed. 1. A method for manufacturing a semiconductor device, characterized by making it possible to visually observe and recognize the mask alignment, and facilitating mask alignment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57156254A JPS5944827A (en) | 1982-09-06 | 1982-09-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57156254A JPS5944827A (en) | 1982-09-06 | 1982-09-06 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5944827A JPS5944827A (en) | 1984-03-13 |
JPS627692B2 true JPS627692B2 (en) | 1987-02-18 |
Family
ID=15623764
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57156254A Granted JPS5944827A (en) | 1982-09-06 | 1982-09-06 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5944827A (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6153891A (en) * | 1994-11-23 | 2000-11-28 | Intel Corporation | Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die |
US5976980A (en) * | 1994-11-23 | 1999-11-02 | Intel Corporation | Method and apparatus providing a mechanical probe structure in an integrated circuit die |
US6020746A (en) * | 1994-11-23 | 2000-02-01 | Intel Corporation | Method and apparatus for probing an integrated circuit through the back side of an integrated circuit die |
US5952247A (en) * | 1994-11-23 | 1999-09-14 | Intel Corporation | Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate |
US5904486A (en) * | 1997-09-30 | 1999-05-18 | Intel Corporation | Method for performing a circuit edit through the back side of an integrated circuit die |
US6309897B1 (en) | 1997-09-30 | 2001-10-30 | Intel Corporation | Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die |
US6159754A (en) * | 1998-05-07 | 2000-12-12 | Intel Corporation | Method of making a circuit edit interconnect structure through the backside of an integrated circuit die |
US6692995B2 (en) | 2002-04-05 | 2004-02-17 | Intel Corporation | Physically deposited layer to electrically connect circuit edit connection targets |
-
1982
- 1982-09-06 JP JP57156254A patent/JPS5944827A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5944827A (en) | 1984-03-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2803734B2 (en) | Integrated circuit forming method | |
US6559063B2 (en) | Method for manufacturing semiconductor wafer having resist mask with measurement marks for measuring the accuracy of overlay of a photomask | |
JPH07231022A (en) | Production of pattern overlap accuracy measurement mark | |
JPS627692B2 (en) | ||
JPS5846054B2 (en) | photo mask | |
US6399259B1 (en) | Method of forming alignment marks for photolithographic processing | |
US5928820A (en) | Method for measuring pattern line width during manufacture of a semiconductor device | |
JP2002507840A (en) | Formation of Stepper Alignment Mark in Double Field Oxidation Process | |
KR960010726B1 (en) | Method of forming pattern of semiconductor device | |
JPS6154247B2 (en) | ||
JPS6324617A (en) | Method for double sided exposure of wafer | |
JPS6215854B2 (en) | ||
KR0149221B1 (en) | Photo mask for fabricating semiconductor | |
JP4023983B2 (en) | Pattern dimension inspection method and image recognition auxiliary pattern | |
JP4013727B2 (en) | Vernier pattern, mask alignment method using the same, and pattern length measurement method | |
JP2839469B2 (en) | Pattern for measuring mask misalignment and method for measuring the same | |
JPS6232783B2 (en) | ||
KR0156104B1 (en) | Reference wafer fabricating method for measuring step coverage of semiconductor metal thin film | |
KR100618689B1 (en) | Method for forming overlay vernier in semiconductor device | |
KR0172826B1 (en) | Forming method of active region | |
JPS6235101B2 (en) | ||
KR100685597B1 (en) | Measurement marks of semiconductor devices and method for forming the same | |
JPH04216647A (en) | Misresistration measuring method | |
JPH02273914A (en) | Mask alignment in photolithography | |
JPH01161715A (en) | Manufacture of semiconductor device |