JPH04216647A - Misresistration measuring method - Google Patents

Abstract

PURPOSE:To accurately measure the misregistration of a wafer by a simple method which occurs in a wafer process in semiconductor device manufacturing processes. CONSTITUTION:After a layer 30 is formed on a semiconductor substrate in the first pattern and resistance layers 321-323 are formed at the overlapping sections of the layer 30 with the second patterns 311-313 by positioning the patterns 311-313 to the layer 30, the misregistration between the first and second patterns is found by measuring the resistance of each resistance layer 321-323. At the time of finding the positional deviation, each measured resistance value is fitted to a logical function (33) about the positions of the resistance layers 321-323 and the positional deviation is found from the misregistration of the layers 321-323 from the central axis 34 of the function 33.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring positional deviation in a wafer process in the manufacturing process of semiconductor devices.

0002

[Background Art] In recent years, patterns for semiconductor devices have been required to become increasingly finer, and along with this, considerably high accuracy has been required for resist pattern positioning, such as the alignment accuracy of exposure equipment. ing. In this case, in order to perform alignment with high accuracy, it is necessary to accurately understand the amount of positional deviation of the resist pattern, and this calculated amount of positional deviation is fed back to the exposure equipment as a calibration standard to achieve high accuracy. It is necessary to perform exposure.

Conventionally, for example, in measuring the amount of positional deviation in the manufacturing process of semiconductor wafers, the degree of overlap between a main pattern and a vernier pattern has been judged by the human eye using an electron microscope or light. That is, for example, the extent to which the position of the main pattern with respect to the vernier pattern deviates from the original overlapping position is visually observed, and this deviation amount is determined as the positional deviation amount of the resist pattern.

[0004] Once the amount of positional deviation is determined in this manner, it is fed back to the exposure device using it as a calibration reference to perform exposure.

[0005]

[Problems to be Solved by the Invention] Conventional methods rely on the human eye to determine the amount of positional deviation using an electron microscope, making it impossible to accurately determine the amount of positional deviation. There is a problem that the design rules (criteria) become inaccurate, resulting in a small margin and high defective rate during mass production of devices.Furthermore, conventional methods cannot achieve a certain level of accuracy unless a large number of measurement points are taken. Since this is difficult to obtain, there is a problem in that the work of determining the amount of positional deviation becomes frequent.

SUMMARY OF THE INVENTION An object of the present invention is to provide a positional deviation measuring method that can accurately measure the amount of positional deviation using a simple method.

[0007]

[Means for Solving the Problems] FIG. 1 shows a diagram illustrating the principle of the present invention. 3A is a plan view when patterns used in the present invention are aligned, and FIG. 1B is a diagram illustrating a method for determining the amount of positional deviation of each pattern.

In the same figure (A), the present invention provides a layer (30, or 311 to 313) on a semiconductor substrate in a first pattern.
) and align the second pattern (311 to 313, or 30) to the layer (30, or 311 to 313) to form a layer (30, or 311 to 313) and the second pattern.
forming resistive layers (321 to 323) in the overlapping portions with the patterns (311 to 313 or 30), respectively;
By measuring each resistance value of the resistance layers (321 to 323), the amount of positional deviation between the first pattern and the second pattern is determined.

In this case, the first pattern is a longitudinal pattern, and the second pattern (311 to 313)
are sequentially shifted by a predetermined pitch so that they overlap at least partially with the first pattern in a direction perpendicular to the longitudinal direction of the first pattern when aligned with the layer (30), and are lined up in at least three rows at a predetermined pitch in the longitudinal direction. The layer (30) has a second pattern (311 to 31
3) to align at least three resistive layers (321
~323) and three resistance layers (321 ~3
23), and as shown in the same figure (B), each resistance value is fitted with a logical function (for example, a quadratic curve) (33) to the position of the resistive layer (321 to 323) to obtain a logical result. The amount of positional deviation is determined from the central axis (34) of the function (33).

0010

[Operation] For example, the first pattern is the main layer pattern, the second pattern is
When the pattern is used as a vernier layer pattern, the vernier layer pattern is aligned with the main layer pattern, exposed and developed to pattern a vernier layer resist, and the main layer pattern and the vernier layer pattern are formed. A resistive layer (
321 to 323). The alignment accuracy at this time is the alignment accuracy of the exposure apparatus, and each resistance value of the resistance layers (321 to 323) corresponds to the amount of positional deviation of the vernier layer pattern with respect to the main layer pattern.

Therefore, at least three resistance layers (321
- 323) are measured, and the values are fitted with a logical function as shown in FIG. The amount of positional deviation determined in this manner is fed back to the exposure apparatus as a calibration reference to correct alignment accuracy. Note that if there is no positional shift at all, the resistance value of the central resistance layer 322 coincides with the central axis (34) of the logic function.

In this way, since the amount of positional deviation is determined by resistance measurement, the amount of positional deviation can be determined more easily and accurately than in the conventional method. Since the amount of positional deviation is determined from the tendency of value change (relative measurement), it is possible to determine the amount of positional deviation with less variation than with absolute measurement determined from only one resistance value.

[0013]

[Example] FIG. 2 is a plan view of each layer pattern used in the method of the present invention, FIG. 3 is a manufacturing process diagram of a semiconductor wafer manufactured by aligning the patterns shown in FIG. 2, and FIG.
2A and 2B show plan views of semiconductor wafers manufactured by aligning the patterns shown in FIG. 2, respectively.

In FIG. 2, 1 is the main layer pattern, 21 to 2
5 is a vernier layer pattern, and 31 to 38 are contact hole layer patterns, each having the shape shown in FIGS. 4(A) to 4(C). In particular, the vernier layer patterns 21 to 25 are arranged in parallel at a predetermined pitch in the longitudinal direction of the main layer pattern 1, with pattern 23 as the center.
They are sequentially shifted by the same pitch in a direction perpendicular to the longitudinal direction. When manufacturing semiconductor wafers, the alignment accuracy in the LOCOS process becomes the reference for the alignment accuracy of the entire process, so knowing the amount of deviation here is important for the exposure process. Hereinafter, the alignment in the LOCOS process will be explained in this embodiment as well.

In FIG. 3(A), a silicon wafer 10
A silicon nitride film 11 is formed on the surface of the silicon nitride film 11, and a major layer resist 1 is formed on the surface using a major layer pattern 1 (FIG. 2(A)).
2 is patterned, the silicon nitride film 11 is etched as shown in FIG. 3(B) using the major layer resist 12, and the major layer resist 12 is peeled off. Next, the same figure (C
), the surface of the silicon wafer 10 is oxidized by thermal oxidation to form a silicon oxide layer 13, and the silicon nitride film 11 is removed, as shown in FIG. The surface of the silicon wafer 10 from which the silicon nitride film 11 has been removed is used as a main scale layer (LOCOS layer) 14.

Next, vernier layer patterns 21 to 25 (
2(B)) with respect to the main length layer 14, exposure and development are performed to form the vernier layer resists 151 to 155 (
A pitch of 0.1 μm) is formed by patterning. The alignment accuracy at this time is the alignment accuracy of the exposure apparatus, and for example, when there is no positional shift at all, the resists 151 to 155 are positioned at the positions indicated by the dashed lines in FIG.
In this case, the center resist 153 completely matches the main scale layer 14), and if there is even a slight positional deviation, it is set to the position shown by the broken line in FIG. Next, ions are implanted into the main length layer 14 (shaded area) to form resistance layers 191 to 195 as shown in FIG. 3(F), and the vernier layer resist 151 is
~155 Peel off.

Next, in FIG. 3(G), a silicon oxide film 16 is formed on the surface by the CVD method, and then the contact hole layer patterns 31 to 38 (FIG. 2(C)) are used to form the silicon oxide film 16 in FIG. 3(H). Contact hole layer resists 171 to 178 are patterned as shown in FIG.
61 to 168 are formed, and resists 171 to 178 are formed.
Peel off. Next, if contact compensation is required, ions are implanted into the main layer 14 (shaded area) as shown in FIG. Aluminum layers 181 to 188 shown in FIG.

By the way, in the process shown in FIG. 3(E), the vernier layer patterns 21 to 25 (
2(B)), and perform exposure and development to form the vernier layer resists 151 to 155, the relative positions of the vernier layer resists 151 to 155 with respect to the main layer 14 are determined by the position of this exposure device. This is the amount of deviation. As described above, the resists 151 to 155 are located at the positions shown by the dashed lines in FIG. 4 when there is no positional deviation, and at the positions shown by the broken lines in FIG. 4 when there is any positional deviation. The ion-implanted portions of the resistance layers 191 to 195 formed using such resists 151 to 155 (FIG. 3(
The size of the shaded area shown in F) is resist 151 to 1.
55 with respect to the main scale layer 14, and the resistance values of the resistance layers 191 to 195 correspond to the size of the ion-implanted portion.
Each resistance value of 195 to 195 corresponds to the amount of positional deviation of the resists 151 to 155 with respect to the main layer 14.

Therefore, the aluminum layers 181 and 188
A current is passed between the aluminum layers 182 and 18.
3, between aluminum layers 183 and 184, between aluminum layers 184 and 185, between aluminum layers 185 and 186, between aluminum layer 18
By measuring each voltage between 6 and 187,
Each resistance value of the resistance layers 191 to 195 can be determined. Resistance layers 191 to 19 obtained in this way
The vertical axis represents each resistance value of resistor layers 191 to 195 and the horizontal axis represents the positional deviation of resists 151 to 155 with respect to the main scale layer 14, and FIG. 5 shows a result of fitting these relationships using a logical function. Shown below.

In FIG. 5, the curve shown by the dashed line is
As shown by the dashed line, the resists 151 to 155 are in an ideal state with no misalignment with respect to the main layer 14,
The center axis of the curve coincides with the coordinate axis, that is, the resistance value of the resistive layer 193 formed of the resist 153 in the center is the lowest. On the other hand, in FIG. 5, the logic function 20 indicated by a solid line is one in which the resists 151 to 155 are slightly misaligned with respect to the main layer 14, as indicated by the broken line in FIG.
The central axis 21 of the next curve 20 is slightly deviated from the coordinate axis, and the value indicated by a is the alignment accuracy, that is, the amount of positional deviation of this exposure apparatus.

In this case, the amount of positional deviation can be determined by measuring only the resistance value of the central resistance layer 193 (absolute measurement), but such an absolute measurement method generally has large variations. However, in the present invention, by using a plurality of resistive layers 191 to 195 whose pitches are intentionally shifted relative to each other, the central axis 2 is determined from the tendency of change in resistance value (relative measurement).
Since the amount of positional deviation is determined by calculating 1, the amount of positional deviation can be determined with less variation compared to absolute measurement. In addition, the amount of positional deviation between the main scale pattern and the vernier pattern can be determined more accurately than in the conventional example, in which the amount of positional deviation between the main scale pattern and the vernier pattern is judged by the human eye using a microscope. Since there is no need to take a large number of measurement points, the amount of positional deviation can be determined easily and in a short time.

The positional deviation amount a obtained in this manner is fed back to the exposure device as a calibration reference to correct the alignment accuracy, and an actual product is manufactured using the corrected exposure device.

In the above embodiment, pattern 1 is the main layer pattern and patterns 21 to 25 are the vernier layer patterns, but this is reversed so that patterns 21 to 25 are the main layer patterns and pattern 1 is the vernier layer pattern. It may also be a layer pattern.

[0024] Also, in this embodiment, 181 and 188
As current terminals, terminal 182 - terminal 183 , 183
-184 ,184 -185 ,185 -186
, 186 - 187 , each resistance is measured by a four-terminal method, but the present invention is not limited to this.
,184 -185 ,185 -186 ,186
A two-terminal method that directly measures the resistance of -187 may also be used.

Furthermore, in the present invention, the main length layer is not limited to a continuous pattern, but as shown in FIG.
82 - terminals 183, 183' - 184, 184
'-185, 185'-186, 186'-
A two-terminal method that measures the resistance of 187 mm may also be used. Furthermore, as shown in FIG. 7, the pitch of the vernier layers 151 to 155 is 0.
The pitch of the main scale layers 141 to 145 may be changed. Furthermore, the position of each resistor pattern does not need to be at a constant pitch (0.1 μm) as in this embodiment, for example, 0,
It may be ±0.1, ±0.3, ±0.7.

Furthermore, the fitting function is not only a quadratic curve, but as shown in FIG. Strictly speaking, if the amount of positional shift is x, then the following logical function is obtained.

[0027]

[Math 1]

[0028] Therefore, W>X, ρs * > ρs
In a case like

[0029]

[Math 2]

##EQU1## may be taken as a fitting function. However, A, B, and W are constants. Furthermore, if the main layers 141 to 145 are metal resistors as shown in FIG. 9(A), if the vernier layers 151 to 155 are etched from the main layer as shown in FIG. 9(B),

[0031]

[Math 3]

is the fitting function. here,
X is the sum of the initial deviation amount P of each resistor pattern and the positioning accuracy x due to alignment of the exposure device, X=P+x.

[0033]

As explained above, according to the present invention, the amount of pattern alignment deviation is determined by forming a resistance layer in the overlapping portion of the main layer pattern and the vernier layer pattern and measuring this. Because of this, the amount of positional deviation can be determined more accurately than the conventional method, which relies on the human eye using a microscope to determine the amount of positional deviation, and it also does not take many measurement points like the conventional method. Since it is not necessary, the work is easy and can be done in a short time.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a plan view of each layer pattern used in the present invention.

3 is a manufacturing process diagram of a semiconductor wafer manufactured by aligning the patterns shown in FIG. 2; FIG.

FIG. 4 is a plan view of a semiconductor wafer manufactured by aligning the patterns shown in FIG. 2;

FIG. 5 is a diagram illustrating a method of determining a positional deviation amount from a measured resistance value.

FIG. 6 is a diagram illustrating an example of a two-terminal method.

FIG. 7 is a diagram illustrating another example of the two-terminal method.

FIG. 8 is a diagram illustrating how to obtain a fitting function.

FIG. 9 is a diagram illustrating how to obtain a fitting function when the vernier layer is formed by etching from the main layer.

[Explanation of symbols]

1 Main layer patterns 21 to 25 Vernier layer patterns 31 to 38 Contact hole layer pattern 10
Silicon wafer 11 Silicon nitride film 12 Main layer resist 13, 16 Silicon oxide layer 14, 141 to 145 Main layer (LOCOS layer)
151 - 155 Vernier layer resist 161 - 16
8 Contact holes 171 to 178 Contact hole layer resists 181 to 188, 183
'~186' Aluminum layer 191~195
, 321 - 323 Resistance layer 20, 33 Quadratic curve 21, 34 Central axis 30 Layer formed in the first pattern (or second pattern) 311 - 313 Second pattern (or layer formed in the first pattern) layer)

Claims (2)

[Claims] Claim 1: A layer (3 layers) is formed on a semiconductor substrate in a first pattern.
0, or 311 to 313), and the layer (30,
or 311 to 313) with the second pattern (311
313, or 30) and align the layers (30, or 311 to 313) and the second pattern (311 to 313).
A resistive layer (313 or 30) is provided in the overlapped portion with
21 to 323) are formed, and the resistance layers (321 to 3
23) A positional deviation measuring method characterized in that the amount of positional deviation between the first pattern and the second pattern is determined by measuring each resistance value. 2. The first pattern is a longitudinal pattern, and the second pattern (311 to 313
) is the first layer when aligned to the layer (30).
At least three patterns are arranged in parallel at a predetermined pitch in the longitudinal direction and are sequentially shifted by a predetermined pitch so as to overlap at least partially with the first pattern in a direction perpendicular to the longitudinal direction of the pattern, and aligning the second patterns (311 to 313) to form the at least three resistance layers (321 to 323);
The resistance values of the three resistance layers (321 to 323) are measured, and the resistance values of the three resistance layers (321 to 323) are measured.
2. The positional deviation measuring method according to claim 1, wherein the positional deviation amount is determined from a central axis (34) of the logical function (33) by fitting with a logical function (33) for the position.