CN115390374B - Overlay error measurement method and method for controlling semiconductor manufacturing process - Google Patents
Overlay error measurement method and method for controlling semiconductor manufacturing process Download PDFInfo
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- CN115390374B CN115390374B CN202211352795.3A CN202211352795A CN115390374B CN 115390374 B CN115390374 B CN 115390374B CN 202211352795 A CN202211352795 A CN 202211352795A CN 115390374 B CN115390374 B CN 115390374B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
Abstract
The present disclosure provides a method for measuring overlay error and a method for controlling a semiconductor manufacturing process, which relate to the technical field of semiconductors, and the method for measuring overlay error comprises the following steps: providing a substrate, wherein a front layer is formed on the substrate and is provided with a front layer pattern; forming a current process layer on the previous layer, sequentially forming at least two mask layers on the current process layer, wherein each mask layer is provided with a mask pattern, and the mask patterns are subsequently used for forming current layer patterns in the current process layer; measuring the offset of each layer of mask pattern relative to the previous layer of pattern; and determining first overlay error information of the current layer pattern and the previous layer pattern according to the at least two offsets. In the method, the alignment precision of the current layer pattern and the previous layer pattern is represented by the first alignment error information, the first alignment error information is related to the offset of each layer of mask pattern relative to the previous layer pattern, and the measurement precision of the first alignment error information is high.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for measuring overlay error and a method for controlling a semiconductor manufacturing process.
Background
The semiconductor chip comprises a plurality of layers of overlapped circuits, each layer of circuit is formed through a photoetching process, and the photoetching process is a process of developing a pattern on a mask plate onto the mask layer and then transferring the mask layer onto a wafer. In order to ensure the performance of the semiconductor chip, it is necessary to ensure the alignment of each front layer and rear layer stack pair (Overlay), but the semiconductor chip cannot be aligned one hundred percent layer by layer due to the effects of marking, measuring, etching, etc.
In order to ensure high overlay accuracy of each of the front and rear layers of the semiconductor chip, after the development of the photolithography process is completed, after-development Inspection (ADI) is performed, and After etching is completed, after-etching Inspection (AEI) is performed.
Disclosure of Invention
The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.
The present disclosure provides a method for measuring overlay error and a method for controlling a semiconductor manufacturing process.
A first aspect of the present disclosure provides a method for measuring an overlay error, where the method for measuring an overlay error includes:
providing a substrate, wherein a front layer is formed on the substrate and is provided with a front layer pattern;
forming a current process layer on the front layer, sequentially forming at least two mask layers on the current process layer, wherein each mask layer is provided with a mask pattern, and the mask patterns are subsequently used for forming current layer patterns in the current process layer;
measuring the offset of each layer of the mask pattern relative to the previous layer pattern; and determining first registration error information of the current layer pattern and the previous layer pattern according to at least two offsets.
Measuring the offset of each layer of the mask pattern relative to the previous layer of the pattern, wherein the measuring comprises:
establishing a rectangular coordinate system based on the front layer pattern, wherein the rectangular coordinate system comprises an X axis and a Y axis;
measuring the X-direction offset of each layer of the mask layer relative to the front layer pattern in the X-axis direction;
measuring the Y-direction offset of each mask layer relative to the front layer pattern in the Y-axis direction;
and determining the first overlay error information based on the X-direction offset of at least two mask layers and the Y-direction offset of at least two mask layers.
Determining first overlay error information of the current layer pattern and the previous layer pattern according to at least two offset values, including:
determining a first offset of the subsequently formed current layer pattern in the X-axis direction according to the X-direction offset and the Y-direction offset of the at least two layers of mask patterns;
determining a second offset of the subsequently formed current layer pattern in the Y-axis direction according to the X-direction offset of the at least two layers of mask patterns and the Y-direction offset of the at least two layers of mask patterns;
determining the first overlay error information based on the first offset and the second offset.
The mask layers are two in number, and the two mask layers comprise a first mask layer and a second mask layer;
the X-direction offset of the first layer of mask layer relative to the front layer pattern in the X-axis direction is a first sub-offset, and the Y-direction offset of the first layer of mask layer relative to the front layer pattern in the Y-axis direction is a second sub-offset;
the X-direction offset of the second layer of mask layer relative to the front layer pattern in the X-axis direction is a third sub-offset, and the Y-direction offset of the second layer of mask layer relative to the front layer pattern in the Y-axis direction is a fourth sub-offset;
and determining the first offset and the second offset according to the first sub-offset, the second sub-offset, the third sub-offset and the fourth sub-offset.
Wherein the first offset and the second offset are calculated according to the following formula:
Xc＝k×Xa+k×Xb+tan(β/2)×Ya-tan(β/2)×Yb；
Yc=tan(α/2)×Xa-tan(α/2)×Xb+k×Ya+k×Yb；
wherein Xc is the first offset; yc is the second offset; xa is the first sub-offset; ya is the second sub-offset; xb is the third sub-offset; yb is a fourth sub-offset; beta is an included angle between the extending direction of the first layer of mask layer and the extending direction of the second layer of mask layer; α is the complement angle of β, the sum of α and β equals 180 °; k is a constant associated with Xa, ya, xb, yb.
The current process layer comprises a first area and a second area which are independently arranged, part of the mask pattern of each mask layer is arranged on the first area of the current process layer, the other part of the mask pattern of each mask layer is arranged on the second area of the current process layer, and at least two layers of projections formed by the mask patterns in the second area of the current process layer are independently arranged.
Wherein the mask pattern on the first region of the current process layer is used for forming a current layer target pattern in the current process layer, and the mask pattern on the second region of the current process layer is used for forming a current layer mark pattern in the current process layer; the first overlay error information is overlay error information between the current layer target pattern and the previous layer pattern.
Wherein, form at least two layers of mask layers sequentially on the said layer of said present process, each said mask layer has step of the mask pattern to include:
forming a first mask layer on the current process layer, patterning the first mask layer, forming a first mask pattern on a first area of the current process layer, and simultaneously forming the first mask pattern on a second area of the current process layer;
and forming a second mask layer on the first mask layer, patterning the second mask layer, forming a second mask pattern on the first area of the current process layer, and simultaneously forming the second mask pattern on the second area of the current process layer, wherein projections of the first mask pattern and the second mask pattern formed in the second area of the current process layer are independently arranged.
Wherein, the measuring method further comprises:
and transferring the first layer mask pattern and the second layer mask pattern into the current process layer, forming the current layer target pattern in a first area of the current process layer, and simultaneously forming a first current layer mark pattern and a second current layer mark pattern which are independently arranged in a second area of the current process layer.
Measuring the offset of each layer of the mask pattern relative to the previous layer of the pattern, including:
measuring the offset of the first current layer mark pattern and the second current layer mark pattern relative to the previous layer pattern, and taking the measured offsets as the offsets of the first layer mask pattern and the second layer mask pattern relative to the previous layer pattern respectively.
The mask pattern is a hard mask pattern obtained by an etching process.
A second aspect of the present disclosure provides a method of controlling a semiconductor manufacturing process, the method of controlling a semiconductor manufacturing process including:
obtaining first overlay error information based on the overlay error measuring method of the first aspect of the disclosure;
acquiring first measurement data different from the first overlay error information based on a process of sequentially forming at least two mask layers on a current process layer, wherein each mask layer is provided with a mask pattern;
determining a correction amount of a manufacturing parameter of at least two of the mask layers in a manufacturing process of forming the mask pattern based on the first metrology data and the first overlay error information.
The step of obtaining first measurement data different from the first overlay error information based on a process of sequentially forming at least two mask layers on the current process layer, wherein each mask layer is provided with a mask pattern comprises:
after a first mask layer of at least two mask layers is formed, performing a first photoetching process on the first mask layer to obtain a first photoresist pattern, wherein the first photoresist pattern is subsequently used for forming a first mask pattern in the first mask layer, and measuring the offset of the first photoresist pattern and a front layer pattern;
after a second mask layer of the at least two mask layers is formed, performing a second photoetching process on the second mask layer to obtain a second photoresist pattern, wherein the second photoresist pattern is subsequently used for forming a second mask pattern in the second mask layer and measuring the offset of the second photoresist pattern and the front layer pattern;
obtaining a third offset and a fourth offset according to the offset of the first photoresist pattern and the front layer pattern and the offset of the second photoresist pattern and the front layer pattern;
and obtaining the first measurement data according to the third offset and the fourth offset.
Wherein the method of controlling a semiconductor manufacturing process further comprises:
after measuring the offset of the first photoresist pattern and the front layer pattern, judging whether the first photoresist pattern needs to be corrected according to the offset of the first photoresist pattern and the front layer pattern, if so, executing a first photoetching process on the first layer mask layer again to obtain a corrected first photoresist pattern;
after measuring the offset between the second photoresist pattern and the front layer pattern, judging whether the second photoresist pattern needs to be corrected according to the offset between the second photoresist pattern and the front layer pattern, and if the second photoresist pattern needs to be corrected, executing a second photoetching process on the second layer mask layer again to obtain a corrected second photoresist pattern;
obtaining a corrected third offset and a corrected fourth offset based on the corrected first photoresist pattern and the corrected second photoresist pattern;
and obtaining the first measurement data based on the corrected third offset and the corrected fourth offset.
Wherein the method of controlling a semiconductor manufacturing process further comprises:
measuring the X-direction offset of the first photoresist pattern relative to the front layer pattern in the X-axis direction to obtain a fifth sub-offset, and measuring the Y-direction offset of the first photoresist pattern relative to the front layer pattern in the Y-axis direction to obtain a sixth sub-offset;
measuring the X-direction offset of the second photoresist pattern relative to the front layer pattern in the X-axis direction to obtain a seventh sub-offset, and measuring the Y-direction offset of the second photoresist pattern relative to the front layer pattern in the Y-axis direction to obtain an eighth sub-offset;
the third offset and the fourth offset are calculated according to the following formula:
Xg＝k×Xe+k×Xf+tan(β/2)×Ye-tan(β/2)×Yf
Yg=tan(α/2)×Xe-tan(α/2)×Xf+k×Ye+k×Yf
xg is the third offset; yg is the fourth offset; xe is the fifth sub offset; ye is the sixth sub offset; xf is the seventh sub-offset; yf is the eighth sub-offset; beta is an included angle between the extending direction of the first photoresist pattern and the extending direction of the second photoresist pattern; α is the complement angle of β, the sum of α and β equals 180 °; k is a constant associated with Xe, ye, xf, yf.
In the overlay error measuring method and the method for controlling the semiconductor manufacturing process, first overlay error information is determined according to the offset of at least two layers of mask patterns relative to a previous layer pattern, the overlay accuracy of a current layer pattern and the previous layer pattern is represented by the first overlay error information, the first overlay error information is related to the offset of each layer of mask pattern relative to the previous layer pattern, and the measuring accuracy of the first overlay error information is high.
Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. For a person skilled in the art, other figures can be derived from these figures without inventive effort.
Fig. 1 is a flow chart illustrating a method for measuring overlay error according to an exemplary embodiment.
FIG. 2 is a flow chart illustrating control of a semiconductor manufacturing process according to an exemplary embodiment.
Fig. 3 is a schematic diagram illustrating the formation of a current process layer on a previous layer, according to an example embodiment.
Fig. 4 is a perspective view of a front layer pattern formed on a substrate according to an exemplary embodiment.
Fig. 5 is a schematic diagram illustrating the formation of a first photoresist pattern on a first masking layer, according to an example embodiment.
Fig. 6 is a schematic diagram illustrating the formation of a first-level mask pattern in a first-level mask layer, according to an example embodiment.
Fig. 7 is a schematic diagram illustrating the formation of a first photoresist pattern on a second masking layer, according to an example embodiment.
Fig. 8 is a schematic diagram illustrating the formation of a second layer mask pattern in a second layer mask layer according to an example embodiment.
Fig. 9 is a perspective view of a first layer mask pattern and a second layer mask pattern on a current process layer, according to an example embodiment.
Fig. 10 is a schematic diagram illustrating the transfer of a second layer mask pattern into a first layer mask layer according to an example embodiment.
FIG. 11 is a schematic diagram illustrating the formation of a current layer pattern in a current process layer in accordance with one illustrative embodiment.
Fig. 12 is a perspective view illustrating when a layer pattern is formed on a front layer according to an exemplary embodiment.
Fig. 13 is a schematic diagram of a first layer of mask patterns and a second layer of mask patterns on a cartesian coordinate system, according to an example embodiment.
Reference numerals are as follows:
100. a substrate; 110. an active region; 120. a front layer; 120a, a front layer pattern; 130. a bit line; 200. a current process layer; 200a, current layer pattern; 201. a first region; 202. a second region; 210a, current layer target pattern; 220a, marking a pattern on the current layer; 2201a, a first current layer mark pattern; 2202a, a second current layer mark pattern; 300. a mask layer; 300a, a mask pattern; 310. a first mask layer; 310a, a first layer mask pattern; 311a, an initial mark pattern; 3111a, a first initial mark pattern; 3112a, a second initial mark pattern; 320. a second mask layer; 320a, a second layer mask pattern; 410. a first photoresist pattern; 420. a second photoresist pattern;
XOY, rectangular coordinate system.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and the features of the embodiments may be arbitrarily combined with each other without conflict.
Currently, the offset of the mask in the X-axis direction and the Y-axis direction is generally measured as the overlay error of the current layer pattern relative to the previous layer pattern, but for the structure of the dual-layer mask or the multi-layer mask, when the post-etching inspection (AEI) is performed, the multi-layer mask pattern is mixed in the structure formed by etching, the overlay error of each layer of mask pattern relative to the previous layer pattern cannot be accurately measured, and the measurement result has low precision.
The utility model provides a measuring method of overlay error, which comprises determining a first overlay error information according to the offset of at least two layers of mask patterns relative to the previous layer pattern, representing the overlay accuracy of the current layer pattern and the previous layer pattern by the first overlay error information, wherein the first overlay error information is related to the offset of each layer of mask pattern relative to the previous layer pattern, and the measuring accuracy of the first overlay error information is high.
Fig. 1 shows a flowchart of a method for measuring overlay error according to an exemplary embodiment of the present disclosure, fig. 1 is a flowchart of a method for measuring overlay error provided according to an exemplary embodiment of the present disclosure, and fig. 3 to 13 are schematic diagrams of various stages of the method for measuring overlay error, which are described below with reference to fig. 3 to 13.
The method for measuring the overlay error of the embodiment may be applied to post-development inspection (ADI) and post-etching inspection (AEI), and includes the following steps:
step S110: providing a substrate, wherein a front layer is formed on the substrate and is provided with a front layer pattern.
As shown in fig. 3 and 4, the substrate 100 may be a wafer made of a semiconductor material, which may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials with semiconducting properties such as group iii-v compounds like gallium arsenide.
The substrate 100 includes one or more stacked semiconductor device layers in a direction perpendicular to a top surface of the substrate 100, wherein each semiconductor device layer may have various semiconductor devices and various metal interconnection structures formed therein. Wherein, the semiconductor device can comprise at least one of a metal oxide semiconductor field effect transistor, a bipolar junction transistor, a resistor, an inductor, a diode and an optical device. As shown in fig. 3 and 4, the front layer 120 is positioned on the substrate 100, and the front layer 120 is provided with a front layer pattern 120a.
Step S120: and forming a current process layer on the previous layer, sequentially forming at least two mask layers on the current process layer, wherein each mask layer is provided with a mask pattern, and the mask patterns are subsequently used for forming current layer patterns in the current process layer.
As shown in fig. 3, the current process layer 200 is disposed on the previous layer 120, and the current process layer 200 is a material layer to be patterned to form a current layer pattern 200a (refer to fig. 11). In some examples, the current process layer 200 may be a layer of semiconductor material, for example, the material of the current process layer 200 may include silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); the current process layer 200 may also include silicon-on-insulator (SOI), germanium-on-insulator (GOI); alternatively, the current process layer 200 may include other materials with semiconductor properties, such as group III-V compounds such as gallium arsenide. In other examples, the current process layer 200 may be other material layers used to form semiconductor devices, such as dielectric layers or metal layers. For example, the current process layer 200 may be an amorphous carbon layer, an oxide layer, a nitride layer, a copper layer, a tungsten layer, an aluminum layer, etc., but is not limited thereto.
Then, as shown in fig. 8 and 9, referring to fig. 3 and 4, at least two mask layers 300 are formed on the current process layer 200, and each mask layer 300 is provided with a mask pattern 300a. For example, two mask layers 300, three mask layers 300, four mask layers 300, or more mask layers 300 may be sequentially stacked on the current process layer 200 in a direction perpendicular to the top surface of the substrate 100, wherein the mask patterns 300a of each mask layer 300 are not completely the same.
Each of the mask patterns 300a may be a hard mask pattern obtained by an etching process, and each of the mask patterns 300a may also be a photoresist pattern obtained by a photolithography process.
Step S130: measuring the offset of each layer of mask pattern relative to the previous layer of pattern; and determining first overlay error information of the current layer pattern and the previous layer pattern according to the at least two offsets.
Referring to fig. 8 and 9, the shift amount of each mask pattern 300a with respect to the previous layer pattern 120a may be measured using an optical measurement method. For example, the offset amount of each mask pattern 300a with respect to the previous layer pattern 120a may be measured using a concentric alignment type mark measurement method, an advanced imaging measurement type mark measurement method, and a diffraction-based overlay mark. Then, first overlay error information of the current layer pattern 200a (refer to fig. 11) and the previous layer pattern 120a is determined according to at least two offset amounts.
In the present embodiment, the offset amount of each mask pattern 300a with respect to the previous layer pattern 120a may be measured after each mask pattern 300a is formed; or measuring the current layer pattern 200a formed in the current process layer 200 to obtain the offset of each layer mask pattern 300a relative to the previous layer pattern 120 a; the offset of each mask pattern 300a relative to the previous layer pattern 120a may also be obtained by measuring the intermediate structure formed by transferring the at least two mask patterns 300a to the current process layer 200 during the process of forming the current layer pattern 200a in the current process layer 200 according to the at least two mask patterns 300a.
In the method for measuring overlay errors of this embodiment, the offset of each layer of mask pattern relative to the previous layer pattern is measured, and the first overlay error information of the current layer pattern and the previous layer pattern is determined, where the first overlay error information is related to the offset of each layer of mask pattern relative to the previous layer pattern, and the overlay accuracy of the current layer pattern and the previous layer pattern obtained by measurement is more accurate.
According to an exemplary embodiment, the present embodiment is a description of the above embodiments, as shown in fig. 8, the current process layer 200 includes a first region 201 and a second region 202 that are independently disposed, a portion of the mask pattern 300a of each mask layer 300 is formed above the first region 201 of the current process layer 200, another portion of the mask pattern 300a of each mask layer 300 is formed above the second region 202 of the current process layer 200, and projections of at least two mask patterns 300a formed in the second region 202 of the current process layer 200 are independently disposed.
Referring to fig. 8 and 11, the mask pattern 300a on the first region 201 of the current process layer 200 is transferred to the current process layer 200 to form the current-layer target pattern 210a, and the mask pattern 300a on the second region 202 of the current process layer 200 is transferred to the current process layer 200 to form the current-layer mark pattern 220a, wherein the current-layer mark pattern 220a retains the pattern features of each layer of the mask pattern 300a.
The current layer pattern 200a formed by transferring the at least two mask patterns 300a to the current process layer 200 includes a current layer target pattern 210a and a current layer mark pattern 220a, and the first overlay error information determined according to the at least two offsets is overlay error information between the current layer target pattern 210a and the previous layer pattern 120a (refer to fig. 12).
Next, the present embodiment is described with the number of mask layers being two, where the two mask layers include a first mask layer and a second mask layer sequentially disposed on the current process layer. In this embodiment, in step S120, a current process layer is formed on a previous layer, at least two mask layers are sequentially formed on the current process layer, and each mask layer is provided with a mask pattern, including the following steps:
step S121: forming a first mask layer on the current process layer, patterning the first mask layer, forming a first mask pattern on a first area of the current process layer, and simultaneously forming a first mask pattern on a second area of the current process layer.
Step S122: and forming a second mask layer on the first mask layer, patterning the second mask layer, forming a second mask pattern on the first area of the current process layer, and simultaneously forming a second mask pattern on the second area of the current process layer, wherein projections formed by the first mask pattern and the second mask pattern on the second area of the current process layer are independently arranged.
Referring to fig. 11, as shown in fig. 8 and 9, the first-layer mask pattern 310a and the second-layer mask pattern 320a on the first region 201 of the current process layer 200 are used to form a current-layer target pattern 210a in the current process layer 200, and the first-layer mask pattern 310a and the second-layer mask pattern 320a on the second region 202 of the current process layer 200 are used to form a first current-layer mark pattern 2201a and a second current-layer mark pattern 2202a in the current process layer 200.
As shown in fig. 8 and 9, there may be an overlapping portion of the first-layer mask pattern 310a and the second-layer mask pattern 320a above the first region 201 of the current process layer 200, that is, there may be an overlapping region in the projection of at least the first-layer mask pattern 310a and the second-layer mask pattern 320a formed on the first region 201 of the current process layer 200.
The projections of the first-layer mask pattern 310a and the second-layer mask pattern 320a formed on the second region 202 of the current process layer 200 are independently arranged, and the projections of the first-layer mask pattern 310a and the second-layer mask pattern 320a formed on the second region 202 of the current process layer 200 are two independently arranged patterns, that is, the projections of the first-layer mask pattern 310a and the second-layer mask pattern 320a formed on the second region 202 of the current process layer 200 are not overlapped.
In some embodiments, referring to fig. 8 and 9, the second region 202 of the current process layer 200 includes two independently disposed sub-regions, the projection of the first layer mask pattern 310a formed on the second region 202 of the current process layer 200 falls on one of the two sub-regions, and the projection of the second mask pattern 320a formed on the second region 202 of the current process layer 200 falls on the other of the two sub-regions. It is understood that, in other embodiments, when the number of mask layers 300 on the current process layer 200 is greater than two, the number of sub-regions in the second region 202 of the current process layer 200 is also greater than two, that is, the second region 202 includes the same number of sub-regions as the number of mask layers 300, and the projections of the at least two mask patterns 300a formed on the second region 202 of the current process layer 200 respectively fall into different sub-regions.
In the overlay error measuring method of this embodiment, when the layer mark pattern retains the pattern features of each layer of mask pattern, the problem that the pattern features of the multi-layer mask pattern are mixed to cause difficulty in measurement after the multi-layer mask pattern is transferred to the current process layer does not occur. Therefore, the overlay error measurement method of the present embodiment can obtain the offset of each mask pattern relative to the previous layer pattern by energy measurement whether applied to post-development inspection (ADI) or post-etching inspection (AEI), so that the first overlay error information determined according to at least two offsets and the offset of each mask pattern relative to the previous layer pattern are both related, and the first overlay error information indicates that the accuracy of the overlay error of the current layer pattern and the previous layer pattern is higher.
In this embodiment, the process of transferring at least two mask patterns into the current process layer to form the current layer mark pattern includes:
as shown in fig. 10, referring to fig. 8, first, a next mask layer 300 is etched sequentially with each mask layer 300 as a mask from a top surface of the at least two mask layers 300 to a top surface of the current process layer 200, so as to transfer the at least two mask patterns 300a layer by layer to the current process layer 200 until the at least two mask patterns 300a are transferred into the first mask layer 310, at least two initial mark patterns 311a are formed in the first mask layer 310, the at least two initial mark patterns 311a are in one-to-one correspondence with the at least two mask patterns 300a, and each initial mark pattern 311a retains a pattern feature of the corresponding mask pattern 300a.
Referring to fig. 10, as shown in fig. 11, then, at least two initial mark patterns 311a are transferred into the current process layer 200 to form at least two current-layer mark patterns 220a, at least two current-layer mark patterns 220a and at least two-layer mask patterns 300a in a one-to-one correspondence, wherein each current-layer mark pattern 220a retains the pattern features of the corresponding mask pattern 300a.
In this embodiment, the offset of the mask pattern 300a relative to the previous layer pattern 120a may be obtained by measuring the initial mark pattern 311a or measuring the current layer mark pattern 220 a.
Next, this embodiment will be described with the number of mask layers being two.
In some examples, measuring the offset of each layer of mask pattern relative to the previous layer of pattern may employ the following embodiments:
referring to fig. 8, as shown in fig. 10, the first-layer mask pattern 310a and the second-layer mask pattern 320a are transferred into the first-layer mask layer 310, and a first initial mark pattern 3111a and a second initial mark pattern 3112a are formed in the first-layer mask layer 310. The shift amounts of the first and second preliminary mark patterns 3111a and 3112a with respect to the previous layer pattern 120a are measured as the shift amount of the first layer mask pattern 310a with respect to the previous layer pattern 120a and the shift amount of the second layer mask pattern 320a with respect to the previous layer pattern 120a, respectively.
In this example, the first-layer mask pattern 310a on the second region 202 is used as a first initial mark pattern 3111a, the first-layer mask layer 310 is etched using the second-layer mask layer 320 as a mask, the second-layer mask pattern 320a is transferred to the first-layer mask layer 310, a second initial mark pattern 3112a is formed in the first-layer mask layer 310 on the second region 202, and the second initial mark pattern 3112a retains pattern features of the second-layer mask pattern 320 a.
The present example takes a shift amount of the first initial mark pattern 3111a with respect to the previous layer pattern 120a as a shift amount of the first-layer mask pattern 310a with respect to the previous layer pattern 120 a; the shift amount of the second initial mark pattern 3112a with respect to the previous layer pattern 120a is used as the shift amount of the second layer mask pattern 320a with respect to the previous layer pattern 120a.
In other examples, measuring the offset of each mask pattern relative to the previous layer pattern may employ the following embodiments:
referring to fig. 10, as shown in fig. 11 and 12, the first layer mask pattern 310a and the second layer mask pattern 320a are transferred into the current process layer 200, and the current-layer target pattern 210a is formed in the first region 201 of the current process layer 200, and at the same time, the first current-layer mark pattern 2201a and the second current-layer mark pattern 2202a are formed in the second region 202 of the current process layer 200. The shift amounts of the first current-layer mark pattern 2201a and the second current-layer mark pattern 2202a with respect to the previous-layer pattern 120a are measured as the shift amount of the first-layer mask pattern 310a with respect to the previous-layer pattern 120a and the shift amount of the second-layer mask pattern 320a with respect to the previous-layer pattern 120a, respectively.
In this example, after the first layer mask pattern 310a and the second layer mask pattern 320a are transferred to the first layer mask layer 310, the current process layer 200 is etched using the first layer mask layer 310 as a mask, the current layer target pattern 210a is formed in the first region 201 of the current process layer 200, the first initial mark pattern 3111a is transferred to the second region 202 of the current process layer 200, the first current layer mark pattern 2201a is formed in the second region 202 of the current process layer 200, and the second initial mark pattern 3112a is transferred to the second region 202 of the current process layer 200 to form the second current layer mark pattern 2202a.
Then, the offset of the first current-layer mark pattern 2201a relative to the previous-layer pattern 120a is measured as the offset of the first-layer mask pattern 310a relative to the previous-layer pattern 120 a; the offset of the second current-layer mark pattern 2202a with respect to the previous-layer pattern 120a is measured as the offset of the second-layer mask pattern 320a with respect to the previous-layer pattern 120a.
In this embodiment, the initial mark pattern or the current layer mark pattern retains the pattern feature of the mask pattern, and the offset of the initial mark pattern or the current layer mark pattern relative to the previous layer pattern is measured and used as the offset of the mask pattern relative to the previous layer pattern, so as to ensure the accuracy of the measurement result, and the measurement method is simple, and the first overlay error information determined according to at least two offsets is more accurate.
In other embodiments, the first-layer mask pattern 310a of the first-layer mask layer 310 may be disposed only above the first region 201 of the current process layer 200 in a direction away from the substrate 100, and after the first-layer mask pattern 310a is formed, an offset of the first-layer mask pattern 310a with respect to the previous-layer pattern 120a may be directly measured and obtained.
According to an exemplary embodiment, this embodiment is a description of the above embodiment, in which the offset amount of each layer mask pattern with respect to the previous layer pattern is measured, the following embodiment is adopted:
first, a rectangular coordinate system is established based on the previous layer pattern, the rectangular coordinate system including an X-axis and a Y-axis.
Referring to fig. 13, a rectangular coordinate system XOY may be established with the pattern center of the previous layer pattern 120a as the origin, and the rectangular coordinate system XOY includes an X axis and a Y axis that are vertically arranged. It is understood that in other embodiments, a rectangular coordinate system XOY may be established for the X-axis or the Y-axis with the edge lines of the front layer pattern 120a.
Then, the X-direction offset of each mask layer relative to the previous layer pattern in the X-axis direction is measured. And measuring the Y-direction offset of each mask layer relative to the front layer pattern in the Y-axis direction.
Referring to fig. 8, 9, and 13, the X-directional offset amount and the Y-directional offset amount of each mask layer 300 with respect to the front layer pattern 120a are measured to obtain the X-directional offset amount and the Y-directional offset amount of at least two mask patterns 300a with respect to the front layer pattern 120a.
Then, the first overlay error information is determined based on the X-direction offsets of the at least two mask layers 300 and the Y-direction offsets of the at least two mask layers 300.
Referring to fig. 13, in this embodiment, determining the first overlay error information of the current layer pattern 200a and the previous layer pattern 120a according to at least two offsets includes the following steps:
first, a first offset of the subsequently formed current layer pattern 200a in the X-axis direction is determined according to the X-direction offset of the at least two mask patterns 300a and the Y-direction offset of the at least two mask patterns 300a.
Then, a second offset amount of the subsequently formed current layer pattern 200a in the Y-axis direction is determined according to the X-direction offset amount of the at least two-layered mask pattern 300a and the Y-direction offset amount of the at least two-layered mask pattern 300a.
Then, based on the first offset and the second offset, first overlay error information is determined.
According to an exemplary embodiment, the method for measuring overlay error of the present disclosure is described in the present exemplary embodiment with the number of mask layers being two. The method for measuring overlay error of the embodiment comprises the following steps:
as shown in fig. 3, first, a substrate 100 is provided, a front layer 120 is formed on the substrate 100, and the front layer 120 is provided with a front layer pattern 120a.
The substrate 100 provided in this embodiment is the same as the substrate 100 provided in step S110 in the above-described embodiment. As shown in fig. 3 and 4, the substrate 100 includes active regions 110 and isolation structures (not shown in the drawings), the isolation structures are disposed between adjacent active regions 110 to isolate the active regions 110, word lines (not shown in the drawings) are disposed in the active regions 110, bit lines 130 are disposed on the active regions 110, and the bit lines 130 are in contact connection with middle regions of the active regions 110. The front layer 120 is disposed on the substrate 100, and a front layer pattern 120a is disposed on the substrate 100, the front layer pattern 120a including a plurality of contact plugs disposed at one end of the active region 110 to be in contact with the active region 110.
As shown in fig. 8 and 9, referring to fig. 3, a current process layer 200 is formed on a front layer 120, a first mask layer 310 and a second mask layer 320 are sequentially formed on the current process layer 200, the first mask layer 310 is provided with a first mask pattern 310a, the second mask layer 320 is provided with a second mask pattern 320a, and the first mask pattern 310a and the second mask pattern 320a are subsequently used for forming a current layer pattern 200a in the current process layer 200.
Referring to fig. 8, as shown in fig. 11 and 12, the current process layer 200 is etched according to the first layer mask pattern 310a and the second layer mask pattern 320a, and a current layer target pattern 210a is formed in the first region 201 of the current process layer 200. Meanwhile, a first current-layer mark pattern 2201a and a second current-layer mark pattern 2202a are formed in the second region 202 of the current process layer 200.
As shown in fig. 11 and 12, then, the offset amount of the first layer mask pattern 310a with respect to the previous layer pattern 120a and the offset amount of the second layer mask pattern 320a with respect to the previous layer pattern 120a are measured; first overlay error information of the current layer pattern 200a and the previous layer pattern 120a is determined according to an offset amount of the first layer mask pattern 310a with respect to the previous layer pattern 120a and an offset amount of the second layer mask pattern 320a with respect to the previous layer pattern 120a.
In this embodiment, the offset of the first layer mask pattern 310a relative to the previous layer pattern 120a and the offset of the second layer mask pattern 320a relative to the previous layer pattern 120a are measured, and the following embodiments may be adopted:
first, a rectangular coordinate system including an X axis and a Y axis is established based on the front layer pattern 120a. As shown in fig. 11, 12, and 13, in the present embodiment, a Y axis is established with the extending direction of the bit line 130 with the center of the front layer pattern 120a as an origin, the Y axis is parallel to the extending direction of the bit line 130, and then an X axis is established according to the Y axis, and the X axis is perpendicular to the Y axis.
Referring to fig. 11, 12, and 13, the offset amount of the first current layer mark pattern 2201a with respect to the front layer pattern 120a is measured as the offset amount of the first layer mask layer 310 with respect to the front layer pattern 120a, the X-direction offset amount of the first layer mask layer 310 with respect to the front layer pattern 120a in the X-axis direction is a first sub-offset amount Xa, and the Y-direction offset amount of the first layer mask layer 310 with respect to the front layer pattern 120a in the Y-axis direction is a second sub-offset amount Ya.
Similarly, the shift amount of the second current layer mask layer 2202a from the previous layer pattern 120a is measured as the shift amount of the second layer mask layer 320 from the previous layer pattern 120a, the X-direction shift amount of the second layer mask layer 320 from the previous layer pattern 120a in the X-axis direction is a third sub-shift amount Xb, and the Y-direction shift amount of the second layer mask layer 320 from the previous layer pattern 120a in the Y-axis direction is a fourth sub-shift amount Yb.
Then, the first offset Xc and the second offset Yc are determined according to the first sub-offset Xa, the second sub-offset Ya, the third sub-offset Xb, and the fourth sub-offset Yb.
In this embodiment, the first offset amount Xc and the second offset amount Yc are calculated according to the following formulas:
Xc＝k×Xa+k×Xb+tan(β/2)×Ya-tan(β/2)×Yb；
Yc=tan(α/2)×Xa-tan(α/2)×Xb+k×Ya+k×Yb；
wherein Xc is a first offset; yc is a second offset; xa is a first sub-offset; ya is the second sub-offset; xb is a third sub-offset; yb is a fourth sub-offset; beta is an included angle between the extending direction of the first layer of mask layer and the extending direction of the second layer of mask layer; α is the complement of β, the sum of α and β being equal to 180 °; k is a constant associated with Xa, ya, xb, yb.
In the present embodiment, k may be a constant of 0 to 1.
As an example, β is 60 °, k is 0.5.
The formula for calculating the first offset Xc is:
Xc＝0.5×Xa+0.5×Xb+0.289×Ya-0.289×Yb；
the formula for calculating the second offset Yc is:
Yc=0.866×Xa-0.866×Xb+0.5×Ya+0.5×Yb。
in the overlay error measuring method of this embodiment, a first offset and a second offset are obtained by calculating according to an offset of a first layer mask pattern relative to a previous layer pattern and an offset of a second layer mask pattern relative to the previous layer pattern, where the first offset and the second offset are both related to an offset of each layer mask pattern relative to the previous layer pattern, and accuracy of first overlay error information defined by the first offset and the second offset is higher.
According to an exemplary general embodiment, the present embodiment provides a method of controlling a semiconductor manufacturing process, and fig. 2 illustrates a flowchart of a method of controlling a semiconductor manufacturing process provided according to an exemplary embodiment of the present disclosure, and as shown in fig. 2, the method of controlling a semiconductor manufacturing process includes the steps of:
step S210: the first overlay error information is obtained based on the overlay error measuring method of the embodiment.
Step S220: based on the above embodiment, at least two mask layers are sequentially formed on the current process layer, and a process of setting a mask pattern on each mask layer obtains first measurement data different from the first overlay error information.
Step S230: based on the first metrology data and the first overlay error information, a correction amount for a fabrication parameter of the at least two mask layers during a fabrication process for forming the mask pattern is determined.
Referring to fig. 3 to 12, in the present embodiment, error information obtained by an inspection After Development (ADI) of the at least two mask layers 300 is first metrology data, error information obtained by an inspection After Etching (AEI) of the at least two mask layers 300 is first set of etching error information, and a correction amount of a manufacturing parameter of the at least two mask layers 300 in a manufacturing process for forming the mask pattern 300a is a difference between the first set of etching error information and the first metrology data in a semiconductor manufacturing process, and process conditions for forming the current layer pattern 200a on the substrate 100 of a next lot may be adjusted according to the correction amount of the manufacturing parameter of the at least two mask layers 300 in the manufacturing process for forming the mask pattern 300a.
In this embodiment, the step of obtaining first measurement data different from the first overlay error information based on a process of sequentially forming at least two mask layers on a current process layer, each mask layer being provided with a mask pattern, includes:
referring to fig. 3 and 8, as shown in fig. 5 and 6, first, after a first mask layer 310 of at least two mask layers 300 is formed, a first photolithography process is performed on the first mask layer 310 to obtain a first photoresist pattern 410, and the first photoresist pattern 410 is subsequently used to form a first mask pattern 310a in the first mask layer 310, and a deviation between the first photoresist pattern 410 and a previous layer pattern 120a is measured.
As shown in fig. 7 and 8, referring to fig. 6, after forming the second mask layer 320 of the at least two mask layers 300, a second photolithography process is performed on the second mask layer 320 to obtain a second photoresist pattern 420, and the second photoresist pattern 420 is subsequently used to form a second mask pattern 320a in the second mask layer 320, and the offset between the second photoresist pattern 420 and the previous layer pattern 120a is measured.
Next, a third offset and a fourth offset are obtained according to the offset of the first photoresist pattern 410 and the previous layer pattern 120a and the offset of the second photoresist pattern 420 and the previous layer pattern 120a. In the present embodiment, the offset amount of the first photoresist pattern 410 and the previous layer pattern 120a is a third offset amount, and the offset amount of the second photoresist pattern 420 and the previous layer pattern 120a is a fourth offset amount.
Then, the first measurement data is obtained according to the third offset and the fourth offset.
Referring to fig. 5 and 7, in the present embodiment, an X-direction offset amount of the first photoresist pattern 410 with respect to the front layer pattern 120a in the X-axis direction is measured to obtain a fifth sub-offset amount Xe; the Y-direction offset of the first photoresist pattern 410 with respect to the front layer pattern 120a in the Y-axis direction is measured to obtain a sixth sub-offset Ye. Measuring the X-direction offset of the second photoresist pattern 420 relative to the front layer pattern 120a in the X-axis direction to obtain a seventh sub-offset Xf; the Y-direction shift amount of the second photoresist pattern 420 with respect to the front layer pattern 120a in the Y-axis direction is measured to obtain an eighth sub-shift amount Yf.
The third offset amount and the fourth offset amount are calculated according to the following formulas.
Xg＝k×Xe+k×Xf+tan(β/2)×Ye-tan(β/2)×Yf
Yg=tan(α/2)×Xe-tan(α/2)×Xf+k×Ye+k×Yf
Xg is a third offset; yg is the fourth offset; xe is a fifth sub-offset; ye is the sixth sub-offset; xf is the seventh sub-offset; yf is the eighth sub-offset; beta is an included angle between the extending direction of the first photoresist pattern and the extending direction of the second photoresist pattern; α is the complement angle of β, the sum of α and β equals 180 °; k is a constant associated with Xe, ye, xf, yf.
In this embodiment, the method of controlling a semiconductor manufacturing process further includes the steps of:
referring to fig. 3, after measuring the offset between the first photoresist pattern 410 and the front layer pattern 120a, it is determined whether the first photoresist pattern 410 needs to be corrected according to the offset between the first photoresist pattern 410 and the front layer pattern 120a, and if the first photoresist pattern needs to be corrected, the first photolithography process is performed on the first layer mask layer 310 again to obtain the corrected first photoresist pattern 410, as shown in fig. 5 and 6.
After the first photoresist pattern 410 is formed each time, measuring the offset between the first photoresist pattern 410 and the front layer pattern 120a, then determining whether the measured offset between the first photoresist pattern 410 and the front layer pattern 120a exceeds the range of the preset threshold, and if the determination result is that the offset exceeds the range of the preset threshold, determining that the first photoresist pattern 410 formed this time is unqualified. The first photoresist pattern 410 is removed from the first mask layer 310, and the first photolithography process is performed again to form a corrected first photoresist pattern 410 on the first mask layer 310. Until the determination result indicates that the offset between the first photoresist pattern 410 and the front layer pattern 120a does not exceed the predetermined threshold, the next process flow may be entered.
Referring to fig. 7 and 8, referring to fig. 6, after measuring the offset between the second photoresist pattern 420 and the previous layer pattern 120a, it is determined whether the second photoresist pattern 420 needs to be corrected according to the offset between the second photoresist pattern 420 and the previous layer pattern 120a, and if the second photoresist pattern needs to be corrected, the second photoresist process is performed on the second layer mask layer 320 again to obtain the second photoresist pattern 420, so as to obtain the corrected second photoresist pattern 420.
After each second photolithography process is performed, measuring the offset between the second photoresist pattern 420 and the previous layer pattern 120a, determining whether the measured offset between the second photoresist pattern 420 and the previous layer pattern 120a exceeds the predetermined threshold, removing the second photoresist pattern 420 from the second mask layer 320 when the determination result is that the offset 120a between the second photoresist pattern 420 and the previous layer pattern 120a exceeds the predetermined threshold, and performing the second photolithography process again to form the corrected second photoresist pattern 420 on the second mask layer 320. The next process flow may be entered until the determination result indicates that the offset between the second mask layer 320 and the front layer pattern 120a does not exceed the predetermined threshold.
Then, based on the corrected first photoresist pattern 410 and the corrected second photoresist pattern 420, a corrected third offset amount and a corrected fourth offset amount are obtained.
Then, the first measurement data is obtained based on the corrected third offset amount and the corrected fourth offset amount.
Referring to fig. 5, 7, 8, and 9, in the present embodiment, based on the corrected first photoresist pattern 410 and the corrected second photoresist pattern 420, the corrected third offset and the corrected fourth offset are obtained, so as to ensure that the first photoresist pattern 410 and the second photoresist pattern 420 used for forming the at least two mask patterns 300 meet the requirement of the process precision, which is beneficial to improving the alignment precision of the formed at least two mask patterns 300a and the front layer pattern 120a. The first measurement data obtained according to the corrected first photoresist pattern 410 and the corrected second photoresist pattern 420 can more accurately represent the influence of the process of forming the mask pattern 300a on the mask pattern 300a, and the correction value of the manufacturing parameter in the manufacturing process of forming the mask pattern 300a, which is determined according to the first measurement data and the first overlay error information, has higher precision, which is beneficial to improving the manufacturing process of a semiconductor and improving the quality of a semiconductor structure.
The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
In the description herein, references to the description of the terms "embodiment," "exemplary embodiment," "some embodiments," "exemplary embodiment," "example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure.
In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing and simplifying the present disclosure, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present disclosure.
It will be understood that, as used in this disclosure, the terms "first," "second," etc. may be used in this disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.
Like elements in one or more of the drawings are represented by like reference numerals. For purposes of clarity, the various features in the drawings are not drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Numerous specific details of the present disclosure, such as structure, materials, dimensions, processing techniques and techniques of the devices, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications or substitutions do not depart from the scope of the embodiments of the present disclosure by the essence of the corresponding technical solutions.
Claims (14)
1. A method for measuring overlay error is characterized in that the method for measuring overlay error comprises the following steps:
providing a substrate, wherein a front layer is formed on the substrate and is provided with a front layer pattern;
forming a current process layer on the front layer, sequentially forming at least two mask layers on the current process layer, wherein each mask layer is provided with a mask pattern, and the mask patterns are subsequently used for forming current layer patterns in the current process layer;
the current process layer comprises a first area and a second area which are independently arranged, part of the mask pattern of each mask layer is arranged on the first area of the current process layer, the other part of the mask pattern of each mask layer is arranged on the second area of the current process layer, and the projections formed by at least two layers of the mask patterns in the second area of the current process layer are independently arranged;
measuring the offset of each layer of the mask pattern relative to the previous layer pattern; and determining first registration error information of the current layer pattern and the previous layer pattern according to at least two offsets.
2. The overlay error measurement method of claim 1, wherein measuring an offset of each mask pattern with respect to the previous layer pattern comprises:
establishing a rectangular coordinate system based on the front layer patterns, wherein the rectangular coordinate system comprises an X axis and a Y axis;
measuring the X-direction offset of each mask layer relative to the front layer pattern in the X-axis direction;
measuring the Y-direction offset of each mask layer relative to the front layer pattern in the Y-axis direction;
and determining the first overlay error information based on the X-direction offset of at least two mask layers and the Y-direction offset of at least two mask layers.
3. The overlay error measurement method of claim 2, wherein determining the first overlay error information of the current layer pattern and the previous layer pattern according to at least two of the offsets comprises:
determining a first offset of the subsequently formed current layer pattern in the X-axis direction according to the X-direction offset of at least two layers of mask patterns and the Y-direction offset of at least two layers of mask patterns;
determining a second offset of the subsequently formed current layer pattern in the Y-axis direction according to the X-direction offset and the Y-direction offset of the at least two layers of mask patterns;
determining the first overlay error information based on the first offset and the second offset.
4. The overlay error measuring method of claim 3, wherein the number of the mask layers is two, and the two mask layers comprise a first mask layer and a second mask layer;
the X-direction offset of the first layer mask layer relative to the front layer pattern in the X-axis direction is a first sub-offset, and the Y-direction offset of the first layer mask layer relative to the front layer pattern in the Y-axis direction is a second sub-offset;
the X-direction offset of the second layer of mask layer relative to the front layer pattern in the X-axis direction is a third sub-offset, and the Y-direction offset of the second layer of mask layer relative to the front layer pattern in the Y-axis direction is a fourth sub-offset;
and determining the first offset and the second offset according to the first sub-offset, the second sub-offset, the third sub-offset and the fourth sub-offset.
5. The overlay error measurement method of claim 4, wherein the first offset and the second offset are calculated according to the following formulas:
Xc＝k×Xa+k×Xb+tan(β/2)×Ya-tan(β/2)×Yb；
Yc=tan(α/2)×Xa-tan(α/2)×Xb+k×Ya+k×Yb；
wherein Xc is the first offset; yc is the second offset; xa is the first sub-offset; ya is the second sub-offset; xb is the third sub-offset; yb is a fourth sub offset; beta is an included angle between the extending direction of the first layer of mask layer and the extending direction of the second layer of mask layer; α is the complement of β, the sum of α and β being equal to 180 °; k is a constant associated with Xa, ya, xb, yb.
6. The overlay error measurement method of claim 1, wherein the mask pattern located on a first region of the current process layer is used to form a current layer target pattern in the current process layer, and the mask pattern located on a second region of the current process layer is used to form a current layer mark pattern in the current process layer; the first overlay error information is overlay error information between the current layer target pattern and the previous layer pattern.
7. The overlay error measurement method of claim 6, wherein at least two mask layers are sequentially formed on the current process layer, and each mask layer is provided with a mask pattern, comprising:
forming a first mask layer on the current process layer, patterning the first mask layer, forming a first mask pattern on a first area of the current process layer, and simultaneously forming the first mask pattern on a second area of the current process layer;
and forming a second mask layer on the first mask layer, patterning the second mask layer, forming a second mask pattern on the first area of the current process layer, and simultaneously forming the second mask pattern on the second area of the current process layer, wherein projections of the first mask pattern and the second mask pattern formed in the second area of the current process layer are independently arranged.
8. The overlay error measurement method of claim 7, further comprising:
and transferring the first layer mask pattern and the second layer mask pattern into the current process layer, forming the current layer target pattern in a first area of the current process layer, and simultaneously forming a first current layer mark pattern and a second current layer mark pattern which are independently arranged in a second area of the current process layer.
9. The overlay error measurement method of claim 8, wherein measuring an offset of each mask pattern with respect to the previous layer pattern comprises:
measuring the offset of the first current layer mark pattern and the second current layer mark pattern relative to the previous layer pattern, and taking the measured offset as the offset of the first layer mask pattern and the second layer mask pattern relative to the previous layer pattern respectively.
10. The overlay error measurement method of claim 1, wherein the mask pattern is a hard mask pattern obtained by an etching process.
11. A method of controlling a semiconductor manufacturing process, the method comprising:
obtaining first overlay error information based on the overlay error measurement method of any one of claims 1-10;
acquiring first measurement data different from the first overlay error information based on a process of sequentially forming at least two mask layers on a current process layer, wherein each mask layer is provided with a mask pattern;
determining correction amounts of manufacturing parameters of at least two mask layers in a manufacturing process for forming the mask pattern based on the first metrology data and the first overlay error information.
12. The method of claim 11, wherein the step of obtaining first metrology data different from the first overlay error information based on a process of sequentially forming at least two mask layers on the current process layer, each mask layer having a mask pattern, comprises:
after a first mask layer of at least two mask layers is formed, performing a first photoetching process on the first mask layer to obtain a first photoresist pattern, wherein the first photoresist pattern is subsequently used for forming a first mask pattern in the first mask layer, and measuring the offset of the first photoresist pattern and a front layer pattern;
after a second mask layer of the at least two mask layers is formed, performing a second photoetching process on the second mask layer to obtain a second photoresist pattern, wherein the second photoresist pattern is subsequently used for forming a second mask pattern in the second mask layer and measuring the offset of the second photoresist pattern and the front layer pattern;
obtaining a third offset and a fourth offset according to the offset of the first photoresist pattern and the front layer pattern and the offset of the second photoresist pattern and the front layer pattern;
and obtaining the first measurement data according to the third offset and the fourth offset.
13. The method of claim 12, further comprising:
after measuring the offset of the first photoresist pattern and the front layer pattern, judging whether the first photoresist pattern needs to be corrected according to the offset of the first photoresist pattern and the front layer pattern, if so, executing a first photoetching process on the first layer mask layer again to obtain a corrected first photoresist pattern;
after measuring the offset between the second photoresist pattern and the front layer pattern, judging whether the second photoresist pattern needs to be corrected according to the offset between the second photoresist pattern and the front layer pattern, and if the second photoresist pattern needs to be corrected, executing a second photoetching process on the second layer mask layer again to obtain a corrected second photoresist pattern;
obtaining a corrected third offset and a corrected fourth offset based on the corrected first photoresist pattern and the corrected second photoresist pattern;
and obtaining the first measurement data based on the corrected third offset and the corrected fourth offset.
14. The method of controlling a semiconductor manufacturing process according to claim 12, further comprising:
measuring the X-direction offset of the first photoresist pattern relative to the front layer pattern in the X-axis direction to obtain a fifth sub-offset, and measuring the Y-direction offset of the first photoresist pattern relative to the front layer pattern in the Y-axis direction to obtain a sixth sub-offset;
measuring the X-direction offset of the second photoresist pattern relative to the front layer pattern in the X-axis direction to obtain a seventh sub-offset, and measuring the Y-direction offset of the second photoresist pattern relative to the front layer pattern in the Y-axis direction to obtain an eighth sub-offset;
the third offset and the fourth offset are calculated according to the following formula:
Xg＝k×Xe+k×Xf+tan(β/2)×Ye-tan(β/2)×Yf
Yg=tan(α/2)×Xe-tan(α/2)×Xf+k×Ye+k×Yf
xg is the third offset; yg is the fourth offset; xe is the fifth sub-offset; ye is the sixth sub-offset; xf is the seventh sub-offset; yf is the eighth sub-offset; beta is an included angle between the extending direction of the first photoresist pattern and the extending direction of the second photoresist pattern; α is the complement angle of β, the sum of α and β equals 180 °; k is a constant associated with Xe, ye, xf, yf.
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| US7218399B2 (en) * | 2004-01-21 | 2007-05-15 | Nikon Corporation | Method and apparatus for measuring optical overlay deviation |
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