JP2006332177A - Semiconductor wafer, manufacturing method thereof and mask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a TEG (test element group) for improving verification accuracy in verifying the pattern dimension of a semiconductor element and verifying it without deteriorating its production yield. <P>SOLUTION: In manufacturing a semiconductor wafer, two element forming regions 12 and a scribing line region 13 for segmenting the regions 12 from each other are formed with one reticle shot 11. The TEGs 14 each having not more than 1/2 of the width of the scribing line region 13 are formed on the scribing line region 13 of four corners of each of the reticle shots 11 and on the center scribing line region 13 thereof. A pattern of the same shape as that of the semiconductor element in the regions 12 and the same shape as each other is formed in each of the TEGs 14. The two TEGs 14 adjacent with each other on each scribing line region 13 are arranged spaced in a longitudinal directions of the scribing line region 13. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer, a manufacturing method thereof, and a mask, and more particularly, a semiconductor wafer having a TEG (Test Element Group) used for verifying a manufacturing process of the semiconductor wafer, a manufacturing method thereof, and the manufacturing method. It relates to the mask used.

  The miniaturization and high density of semiconductor elements are still vigorously advanced, and at present, ultra-highly integrated semiconductors such as DRAM (Dynamic Random Access Memory) manufactured based on 90 nm rule design standards or lower design standards. A device is being developed and prototyped.

  When a semiconductor device is manufactured, generally, a reduction projection exposure apparatus (hereinafter referred to as a stepper and a scanner) is used to perform patterning of a photoresist film, whereby a large number of semiconductors are formed in an element formation region on a semiconductor wafer. An LSI including elements is formed. In recent years, with the high integration of LSI, the occupied area of each semiconductor element in a semiconductor device has been reduced year by year, and as microfabrication for this purpose proceeds, the demand for element dimensional accuracy is increasing. . For this reason, it is indispensable to measure the dimensions of the element pattern formed in the element formation region in the manufacturing process of the semiconductor device. Conventionally, in this dimension measurement, an automatic measurement method for a semiconductor element formed in an element formation region by using a scanning electron microscope (SEM) has become mainstream.

  By the way, when dimension measurement by a scanning electron microscope (SEM) is performed in the element formation region following the photoresist lithography process, there is a problem that the resist pattern contracts with electron beam irradiation. This pattern reduction may cause, for example, a device characteristic defect due to a short circuit between adjacent contacts due to a decrease in separation width accompanying an increase in contact diameter, a disconnection due to a thin wiring pattern, or the like. Such a defect leads to a decrease in the yield of the semiconductor device, and becomes a serious problem as the miniaturization further proceeds. This problem is considered to be particularly remarkable when the ArF technique is applied, in which resist shrinkage due to electron beam irradiation is large compared to other resists (I-line, KrF).

  The problem of shrinkage on the resist pattern can be suppressed to some extent by lowering the voltage (acceleration voltage) applied between the grid and anode of the scanning electron microscope. However, in this case, there is a problem that, in principle, the dimensional measurement accuracy itself decreases due to a decrease in the amount of secondary electrons generated from the surface of the measurement pattern.

  The problem of shrinkage on the resist pattern can also be avoided by substituting TEGs for evaluating various device characteristics previously arranged in the scribe line region. Techniques for forming a TEG in the scribe line region are described in, for example, Patent Document 1, Patent Document 2, and Patent Document 3.

FIG. 7 shows an example of a TEG pattern for measuring the characteristics of the MOSFET formed on the scribe line region. A MOSFET 51 having the same size and shape as the MOSFET formed in the element formation region 12 is formed in the scribe line region 13 that separates the element formation regions 12 from each other. A wiring 52 that connects the MOSFET 51 is used for characteristic measurement. A pad 53 is formed.
JP 2004-158515 A (paragraph 0153) JP-A-6-295054 (paragraph 0005) Japanese Patent Laid-Open No. 11-186353 (paragraph 0027)

  By the way, in order to increase the measurement accuracy when measuring the pattern dimensions in the TEG, it is required to arrange the TEG patterns at a plurality of locations in the reticle shot and accurately detect the dimensional variations in the shot during the photolithography process. The However, the conventional TEG pattern MOSFET 51 shown in FIG. 7 for the purpose of device characteristic evaluation is considerably connected to a plurality of characteristic measurement pads 53 through a metal wiring 52 made of aluminum or the like. Requires a large area. For this reason, when placing a TEG pattern on the scribe line region 13, there are restrictions on the placement of the TEG pattern, such as being unable to place it on a ½ width scribe line region placed around the reticle shot. growing.

  In view of the above, the present invention is an improved semiconductor that can improve the verification accuracy by TEG used for the purpose of verifying the dimensions of the semiconductor element pattern formed by the patterning following the patterning using the stepper and the scanner. An object of the present invention is to provide a wafer manufacturing method, a mask used in the manufacturing method, and a semiconductor wafer formed by the manufacturing method.

In order to achieve the above object, a semiconductor wafer of the present invention includes a plurality of element formation regions each having an integrated circuit including semiconductor elements formed therein, and a scribe line region that partitions the plurality of element formation regions from each other. In a semiconductor wafer formed by patterning using photolithography,
A plurality of TEGs are arranged on the scribe line region in each rectangular exposure region formed by one reticle shot in the photolithography, and the plurality of TEGs are formed in the element formation region. The semiconductor device pattern includes at least one pattern having the same shape and the same size as each other and having the same shape.

In addition, a manufacturing method of a semiconductor device according to the present invention includes a rectangular including a plurality of element formation regions in which integrated circuits including semiconductor elements are respectively formed, and a scribe line region that partitions the plurality of element formation regions from each other. In a method for manufacturing a semiconductor device, in which a shaped exposure region is repeatedly formed on a semiconductor wafer,
Each of the rectangular exposure regions includes a plurality of TEGs disposed on the scribe line region, and the plurality of TEGs have the same shape and the same size as the semiconductor element pattern formed in the element formation region. And at least one pattern having the same shape as each other.

Furthermore, the mask of the present invention is a rectangular exposure region including a plurality of element formation regions in which integrated circuits including semiconductor elements are respectively formed and a scribe line region that partitions the plurality of element formation regions. A mask for forming a semiconductor wafer on a semiconductor wafer,
The rectangular exposure region includes a plurality of TEGs disposed on the scribe line region, and the plurality of TEGs have the same shape and the same size as the semiconductor element pattern formed in the element formation region. And at least one pattern having the same shape as each other.

  According to the semiconductor wafer, the method for manufacturing a semiconductor wafer, and the mask of the present invention, the plurality of TEGs arranged on the scribe line include a pattern having the same shape and size as the semiconductor element pattern formed in the element formation region. Thus, there is an effect that the verification accuracy in the verification of the pattern dimension is improved without increasing the area of the chip formed in the semiconductor wafer.

  In a preferred aspect of the semiconductor wafer and the manufacturing method thereof according to the present invention, the plurality of TEGs include TEGs formed on scribe line regions at four corners of the exposure region. At the four corners of the exposure region, the dimensional accuracy tends to be lowered particularly during exposure by a stepper and a scanner. Therefore, the verification accuracy is particularly improved by arranging the TEG on the scribe line region at the four corners.

  The two TEGs that are respectively formed in two adjacent exposure regions and are adjacent to each other are separated on both sides of the center line of the scribe line region on the same scribe line region and the center line It is also a preferred aspect of the present invention that the position is shifted in the extending direction. In this case, the problem of performing measurement with an incorrect TEG during automatic dimension measurement can be solved.

  The plurality of TEGs are further formed on a scribe line region at a central portion of each exposure region, and are separated on both sides across the center line of the scribe line region and arranged in a shifted direction in the direction in which the center line extends. It is also a preferred embodiment of the present invention that two TEGs are included. By placing a TEG in the center of the exposure area and comparing and verifying the measurement dimensions at the four corners of the TEG and the measurement dimensions of the TEG at the center, it is easier to identify the location and cause when a problem occurs. In addition, the accuracy of verification for dimensional variations in reticle shots (mask manufacturing variations) produced by EB (Electron Beam) drawing, etc., and dimensional variations in reticle shots due to lens characteristics of steppers and scanners is further improved. To do.

  Hereinafter, the present invention will be further described based on embodiments of the present invention with reference to the accompanying drawings. FIG. 1 is a plan view showing a part of a semiconductor wafer according to an embodiment of the present invention. In the figure, four exposure regions (reticle shots) 11 formed on the semiconductor wafer 10 using the same mask pattern are shown. Each exposure region 11 includes two element formation regions 12, a scribe line region 13 that partitions these element formation regions, and TEGs 14 formed at the four corners and the central portion of the exposure region 11, respectively. Each TEG 14 has the same pattern shape and size, and each of these patterns includes a semiconductor element or a capacitor element included in an integrated circuit formed in the element formation region 12 (in this specification, these elements are all semiconductors). Are formed in the same shape and size as the respective patterns.

  The two TEGs 14 at the center of each reticle shot 11 are formed on the same scribe line region 13 and are arranged on both sides of the center line of the scribe line region 13 and shifted in the longitudinal direction of the scribe line region 13. Is done. Further, two TEGs 14 included in two exposure regions 11 arranged in the vertical direction in the drawing and formed on and adjacent to the same scribe line region 13 are on both sides of the center line of the scribe line region 13. In addition, they are arranged shifted in the longitudinal direction of the scribe line region 13.

  FIG. 2 shows arrangement details of two TEGs 14 formed in two adjacent exposure regions 11 and arranged adjacent to each other on the same scribe line region 13 in the semiconductor wafer 10 of FIG. The two TEGs 14 are arranged separately on both sides of the center line 15 of the scribe line region 13 that constitutes the boundary portion of the exposure region 11, separated by a distance of W12 in the direction along the center line 15, and on the center line 15. They are arranged symmetrically with respect to the point X. Each TEG 14 is formed with an element dimension measuring pattern formed in the same pattern shape as the semiconductor element. Each pattern formed in the TEG 14 follows the resist pattern patterning process or follows the patterning process of the semiconductor element using the resist pattern as an etching mask. A pattern dimension is measured.

  For example, the width W10 of the scribe line region 13 is 100 μm, the length of one side of the TEG 14 is 20 to 40 μm, and the width from the boundary line 16 between the scribe line region 13 and the element formation region 12 to the TEG 14 constituting the element dimension measurement pattern. W11 is 5 to 15 μm, and the separation distance W12 along the longitudinal direction of the scribe line region 13 of the TEG 14 is 10 to 30 μm. The arrangement of the two TEGs 14 formed in the central portion of the exposure region 11 is the same as the arrangement shown in FIG.

  As described above, the TEG 14 is separated along the longitudinal direction of the scribe line region 13 for the following reason. That is, in the semiconductor device manufacturing process, automatic dimension measurement using a scanning electron microscope is the mainstream in the process of performing dimension measurement subsequent to the photolithography process. In automatic dimension measurement, pattern recognition is performed by comparing a pattern image of a specific location stored in advance with an image on the same coordinates on an actual measurement wafer. After wafer alignment (origin correction), when moving to a desired coordinate position and performing automatic measurement, the contrast decreases due to changes in the shape of the measurement target pattern caused by the focus change (defocus) of the exposure tool. However, accurate image recognition (matching processing) becomes difficult. In this case, the measuring machine itself moves to the peripheral coordinates, and a process of automatically searching for a location that matches the pattern image stored in advance is performed. For example, as shown in the comparative example of FIG. 3, when both adjacent TEGs 14 are arranged symmetrically with respect to the center line 15, the automatic recognition apparatus mistakenly causes the other reticle shot due to the proximity of the patterns in both TEGs 14. This is because a problem of designating the TEG may occur.

  FIG. 4 shows an example of a reticle mask used when patterning the semiconductor wafer 10 of the above embodiment. The reticle mask 20 has an exposure region 21 that exposes two semiconductor chips (element formation regions) 22 at a time. The TEG pattern 24 is disposed adjacent to the four corners of the exposure region 21, and the TEG pattern 24 is also disposed on the scribe line region pattern 23 in the center. Each TEG pattern 24 is a dimension measuring pattern having the same size and the same shape, and is formed in a substantially square region. Among the TEG patterns 24 at the four corners, the TEG pattern 24 adjacent to the two corners arranged in the vertical direction on the drawing has the edge of one TEG pattern 24 aligned with the edge of the element formation region pattern 22; The edge of the other TEG pattern 24 is arranged farther from the edge of the element formation region pattern 22 than the other edge of the one TEG pattern 24. As for the two TEG patterns 24 arranged in the horizontal direction in the drawing, the edge of one TEG pattern 24 is aligned with the edge of the element formation region pattern 22, and the edge of the other TEG pattern 24 is further away from this. Be placed.

  Hereinafter, a method for manufacturing the semiconductor wafer according to the embodiment will be described with reference to FIGS. FIG. 5A is a plan view showing the vicinity of the TEG formed in the scribe line region when the silicon nitride film is formed. FIG. 5B is a cross-sectional view taken along the line A-A ′ showing a part “C” of the TEG shown in FIG. First, as shown in FIGS. 5A and 5B, a silicon oxide film (PAD oxide film) 31 having a thickness of about 10 nm by a thermal oxidation method is formed on a silicon substrate 30 which is a P-type semiconductor substrate, for example. Then, a silicon nitride film (field nitride film) 32 having a thickness of about 150 nm is formed in the element formation region 12 and the scribe line region 13 where the TEG 14 and the alignment mark are formed. As shown in these drawings, the same insulating films 31 and 32 as the element formation region 12 are formed on the TEG 14 in the scribe line region 13.

  Next, a photoresist film is deposited on the entire surface of the wafer including the element formation region and the scribe area, and is patterned using a photolithography technique to form a resist pattern 33. FIG. 6A shows a photoresist pattern of a part “C” of the TEG 14 shown in FIG. 5A, and this pattern has the same shape and size as the pattern formed in the element formation region 12. Is. FIG. 6B is a cross-sectional view of the portion “C” taken along the line A-A ′. As described above, the pattern formed on the TEG 14 in the present embodiment is a pattern specialized for dimension measurement, and the pattern is exactly the same in size and shape as the pattern formed in the element formation region 12. As described above, the pattern specialized for dimension measurement does not require a plurality of characteristic measurement pads via a metal wiring layer made of aluminum or the like, and thus is smaller than a TEG used for conventional characteristic measurement. Area is enough.

  The silicon nitride film 32 is patterned using the resist pattern 33 shown in FIG. 6 as an etching mask. As a result, a region for forming the MOSFET diffusion layer is defined in the element formation region 12 and the same pattern is also formed in the TEG 14 in the scribe line region 13.

  The TEG 14 is formed by one reticle shot, one at each of the four corners of the reticle shot 11 and two at the center. A similar pattern is formed on each TEG 14 for each process step. For example, a pattern having the same shape and arrangement as the semiconductor element pattern formed in the element formation region 12 and a minimum width are formed for all of the insulating film and the wiring layer, and the dimensions of each pattern are measured each time. It is determined whether or not the patterning has been performed with high accuracy.

  For example, when manufacturing a DRAM device, a memory cell pattern of several k to several tens of k bits is formed in the TEG 14 on the scribe line region 13. At this time, the size of one side of the TEG is, for example, 20 to 40 μm. The formed TEG includes patterns such as a word line and a bit line made of polycrystalline silicon as well as a diffusion layer. In this way, memory cells of several k to several tens of k bits are formed in the TEG 14 in a pseudo manner, and the dimensions of each pattern are measured. However, since a pattern having a small size (area) is sufficient as compared with a conventional pattern for measuring characteristics of a semiconductor element, a plurality of patterns that fit within half the width of the scribe line region 13 are formed in each exposure region 11. it can.

  By measuring the dimensions of the same pattern with a plurality of formed TEGs 14 and comparing them with each other, it is possible to make a detailed determination as to which part of each reticle shot has insufficient dimensional accuracy. If the dimensional accuracy is insufficient in a certain part, it is possible to investigate the cause such as whether it is caused by the lens of the stepper and the scanner or if it is caused in the drawing apparatus when it is produced on the reticle substrate. As a result, verification accuracy can be increased without adding a process to the conventional photolithography process. In particular, since the TEG is formed on the scribe line region, there is no risk of occurrence of defects due to the reduction of the resist pattern or the like in the element dimension measurement by the scanning electron microscope.

  By forming a TEG having a size of ½ or less of the width of the scribe line region, the TEG can be arranged on the scribe line region at the four corners particularly in the reticle shot, and the dimensional accuracy that is particularly likely to occur at the peripheral portion of the reticle shot. A decrease is detectable. In addition, by comparing these with the measurement pattern results placed in the center, it is easy to determine which of the peripheral patterns is causing dimensional defects. The cause can be easily determined, and the dimensional monitor accuracy can be improved.

  In the above embodiment, the element dimension measurement pattern is used to form the element in the element formation region 12 when the element dimension is measured by the scanning electron microscope in the photolithography process without adding the number of conventional processes in the semiconductor process. It is possible to avoid irradiating the device pattern directly with an electron beam. For this reason, it is possible to prevent a short circuit failure due to a decrease in separation width accompanying an increase in contact diameter due to a shrinkage of a resist pattern, a disconnection due to a thinning of a wiring pattern, a device characteristic failure, and the like, thereby reducing the yield of semiconductor devices. It becomes possible to prevent. In addition, since it is not necessary to reduce the voltage (acceleration voltage) applied between the grid and the anode of the scanning electron microscope, the pattern dimension formed in the element formation region can be controlled without reducing the dimension measurement accuracy.

  In the present embodiment, a plurality of element dimension measurement patterns formed from element patterns having the same minimum design dimensions as the element formation area 12 are simultaneously arranged on the scribe line area within the mask circuit pattern drawing range. Therefore, it is possible to easily monitor the mask manufacturing variation and the dimensional variation in the shot due to the lens characteristics of the stepper and the scanner, increase the chip area, and greatly increase the product cost. Can be easily avoided.

  Further, in a photolithography process, a constant distance of, for example, about 10 to 30 μm is provided between adjacent TEGs so as to be point-symmetric with respect to a point on the center line of the scribe line region 13 at the reticle shot boundary. It is possible to obtain an effect of easily avoiding erroneous measurement during automatic measurement.

  As mentioned above, although this invention was demonstrated based on the suitable embodiment, the semiconductor wafer of this invention, its manufacturing method, and a mask are not limited only to the structure of the said embodiment, From the structure of the said embodiment. Various modifications and changes are also included in the scope of the present invention. In addition, each configuration described as a preferred aspect of the present invention or each configuration described in the embodiment is preferably used together with the essential configuration of the present invention, but about a configuration that exhibits a beneficial effect even when used alone. However, it is not always necessary to use all the configurations described as the essential configurations of the present invention.

  The present invention can be applied to a semiconductor wafer manufactured when manufacturing a semiconductor device such as a DRAM or a system LSI, a manufacturing method thereof, and a reticle used for manufacturing the same.

1 is a partial plan view of a semiconductor wafer according to an embodiment of the present invention. The top view which shows the detailed arrangement | positioning of TEG of the scribe line area | region of FIG. The top view which shows arrangement | positioning of TEG of the comparative example for comparing with arrangement | positioning of FIG. FIG. 2 is a pattern plan view of a reticle mask used when exposing the semiconductor wafer of FIG. 1. (A) is a top view which shows the TEG vicinity of the scribe line area | region in the manufacturing stage of a semiconductor wafer, (b) is sectional drawing which shows a part of TEG of the figure (a). (A) is a top view of a part of photoresist pattern of TEG, (b) is a sectional view taken along the line A-A 'in (a). The top view which shows TEG for element characteristic measurement formed on the conventional scribe line area | region.

Explanation of symbols

10: Semiconductor wafer 11: Reticle shot (exposure area)
12: Element formation region 13: Scribe line region 14: TEG (Dimension measurement pattern formation region)
15: Center line of scribe line area 16: Boundary line 20 between element formation area and scribe line area 20: Reticle mask 21: Exposure area 22: Element formation area pattern 23: Scribe line area pattern 24: TEG pattern (dimension measurement) Pattern formation area)
30: Silicon substrate 31: Silicon oxide film 32: Silicon nitride film 33: Resist pattern 51: MOSFET (device characteristic evaluation TEG)
52: Wiring 53: Pad for characteristic measurement

Claims (9)

A semiconductor wafer in which a plurality of element formation regions each having an integrated circuit including semiconductor elements formed therein and a scribe line region that partitions the plurality of element formation regions from each other are formed by patterning using photolithography In
A plurality of TEGs are arranged on the scribe line region in each rectangular exposure region formed by one reticle shot in the photolithography, and the plurality of TEGs are formed in the element formation region. A semiconductor wafer comprising at least one pattern having the same shape and the same size as the semiconductor element pattern formed and having the same shape as each other.   The semiconductor wafer according to claim 1, wherein the plurality of TEGs include TEGs formed on scribe line regions at four corners of the exposure region.   Two TEGs that are respectively formed in two adjacent exposure areas and are adjacent to each other are separated on both sides of the center line of the scribe line area on the same scribe line area, and the center line extends. The semiconductor wafer according to claim 2, wherein the semiconductor wafer is arranged with a position shifted in a direction.   The plurality of TEGs are further formed on a scribe line region at a central portion of each exposure region, and are separated on both sides across the center line of the scribe line region and arranged in a shifted direction in the direction in which the center line extends. The semiconductor wafer according to claim 2, comprising two TEGs. A rectangular exposure region is repeatedly formed on a semiconductor wafer, which includes a plurality of element formation regions in which integrated circuits including semiconductor elements are formed, and a scribe line region that divides the plurality of element formation regions. In a method for manufacturing a semiconductor device,
Each of the rectangular exposure regions includes a plurality of TEGs disposed on the scribe line region, and the plurality of TEGs have the same shape and the same size as the semiconductor element pattern formed in the element formation region. A method for manufacturing a semiconductor device, comprising at least one pattern having the same shape.   The semiconductor device manufacturing method according to claim 5, wherein the plurality of TEGs are formed in scribe line regions at four corners of the exposure region.   Two TEGs that are respectively formed in two adjacent exposure regions and that are adjacent to each other are separated on both sides of the center line of the scribe line region on the same scribe line region and the center line extends. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is disposed at a shifted position.   The plurality of TEGs are further formed on a scribe line region in the central portion of each exposure region, separated on both sides across the center line of the scribe line region, and shifted in a direction in which the center line extends 2 The manufacturing method of the semiconductor device of Claim 6 or 7 containing two TEGs. Forming a rectangular exposure region on a semiconductor wafer including a plurality of element forming regions each having an integrated circuit including a semiconductor element formed therein and a scribe line region that partitions the plurality of element forming regions. Mask,
The rectangular exposure region includes a plurality of TEGs arranged on the scribe line region, and the plurality of TEGs have the same shape and the same size as the semiconductor element pattern formed in the element formation region. And at least one pattern having the same shape as each other.

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