JP7251014B2 - Semiconductor integrated circuit pattern layout method, semiconductor chip manufacturing method, semiconductor chip evaluation method, and semiconductor chip - Google Patents

Description

The present invention relates to a pattern layout of a semiconductor integrated circuit, and more particularly to a TEG (Test Element Group) pattern layout.

In a semiconductor integrated circuit incorporated in an LSI package, etc., a TEG equipped with an evaluation element for examining design constraints and manufacturing processes is installed on the periphery (scribe area) of a semiconductor element circuit in which a large number of wiring patterns are hierarchically formed. is provided. Performance evaluation and failure analysis of the semiconductor integrated circuit can be performed by evaluating and analyzing the evaluation element of the TEG.

In recent years, with the increase in the number of elements mounted on semiconductor integrated circuits, the number of items to be evaluated by the TEG has increased, and many evaluation elements must be arranged in the TEG. However, due to the limited area of the scribe region, it is difficult to arrange all the evaluation elements on the TEG. In order to solve this problem, it has been proposed to form a module evaluation pattern as a dummy pattern around a module (memory, logic, sensor, etc.) in a semiconductor device circuit (see Patent Document 1).

Japanese Patent No. 4435069

As the chip size shrinks, it becomes more difficult to secure space around the module. For example, a cross-sectional evaluation pattern (also called SEMBAR) needs to secure a sufficient occupied area for preparing various sample patterns, so it is difficult to form the evaluation pattern around the module of the semiconductor element circuit. .

Therefore, there is a demand for a TEG pattern layout that can cope with the reduction in chip size.

The pattern layout method of the present invention is a pattern layout method for arranging a semiconductor element circuit pattern in a semiconductor element circuit area and arranging a TEG (Test Element Group) pattern in a scribe area. , a layout pattern composed of the shape evaluation pattern is arranged in the portion where the dummy pattern can be arranged. Here, the "shape evaluation pattern" represents a pattern for evaluating the shape of a circuit pattern, an element, or the like, and includes, for example, a pattern for evaluating a cross-sectional shape and a pattern for evaluating a surface shape. The layout pattern can be configured as a pattern in which the shape evaluation patterns are regularly arranged, and the layout pattern is arranged by either the cross-sectional shape evaluation pattern or the surface shape evaluation pattern, or a layout pattern including both is arranged. It is also possible to

Here, the term "semiconductor device circuit" refers to an integrated circuit surrounded by a scribe area and comprising a circuit made up of devices such as transistors. "TEG pattern layout area" indicates the layout area of the entire TEG. The “portion where dummy pattern can be arranged” indicates a region in which no TEG evaluation element, electrode terminal, wiring, or the like is arranged.

The shape evaluation pattern can be a pattern corresponding to the pattern of contact plugs or vias formed in the semiconductor element circuit. It is possible to arrange a plurality of layout patterns composed of shape evaluation patterns having different sizes, or a layout pattern composed of shape evaluation patterns having different pitches, or a plurality of cells having different surface shapes. A layout pattern can be arranged as a shape evaluation pattern.

In the layout process, it is possible to define a plurality of regions for arranging a plurality of cell layout patterns prepared as patterns for shape evaluation and to assign addresses to each region in the pattern arrangement area of the TEG.

According to another aspect of the present invention, there is provided a semiconductor chip manufacturing method in which a semiconductor element circuit pattern is formed in a semiconductor element circuit area on a wafer, and a TEG (Test Element Group) pattern is formed in a scribe area on the wafer. A semiconductor chip manufacturing method including a photolithography process for forming a shape evaluation pattern in a dummy pattern formable portion of a pattern formation area of a TEG in the photolithography process. The pattern for shape evaluation can be evaluated by SEM (Scanning Electron Microscope) for the semiconductor chip manufactured by this. In addition, the shape evaluation pattern corresponding to the shape evaluation pattern can be formed in the same process as the formation of the contact plug or the like arranged in the semiconductor element circuit.

A semiconductor chip, which is another aspect of the present invention, comprises a semiconductor element circuit and a TEG provided in a scribe region, and the TEG comprises an evaluation element and a shape evaluation pattern different from the evaluation element.

In the present invention, a data pattern used in a pattern layout method using a computer or the like, a pattern for evaluation that is exposed on a wafer in a wafer process including a photoresist, and a semiconductor chip that is a product have dimensions and shapes. Both patterns are expressed as "evaluation patterns".

According to the present invention, it is possible to provide a TEG pattern layout and a semiconductor chip based thereon that can cope with a reduction in chip size.

It is a figure showing a part of the semiconductor wafer which is this embodiment. FIG. 4 is a diagram schematically showing a pattern of a partial area within the TEG; Fig. 3 shows three partial areas within the TEG; FIG. 10 is a diagram showing layout patterns with different pattern sizes; FIG. 4 is a cross-sectional view illustrating a pattern for shape evaluation; 1 is a cross-sectional view showing part of a semiconductor chip; FIG. FIG. 5 is a diagram showing a flow of pattern layout processing; It is the figure which showed the flow of wafer processing.

The present embodiment will be described below with reference to the drawings. In each figure, the same components are denoted by the same reference numerals, and overlapping descriptions are omitted.

FIG. 1 is a diagram showing part of a semiconductor wafer according to this embodiment.

A large number (only four are shown in FIG. 1) of semiconductor element circuits 10 are formed in a grid pattern on a semiconductor wafer 100, and a TEG 20 is provided in a scribe area (also referred to as a scribe line area) 15 around it. . The semiconductor element circuit 10 is an integrated circuit including many modules such as transistors, and the TEG 20 includes elements, circuits, and the like for evaluating and analyzing the characteristics, performance, and the like of the semiconductor element circuit 10 . The semiconductor chip 10 ′ finally obtained through the dicing process and the like is a reduced size chip here, and the scribe area 15 corresponding to the periphery of the semiconductor element circuit 10 includes the TEG 20 .

FIG. 2 is a diagram schematically showing a pattern of a partial area within the TEG 20. As shown in FIG.

A plurality of evaluation elements 22 and electrode terminals (PADs) 23 are formed in a partial area 20 ′ inside the TEG 20 , and are electrically connected by wires 24 that connect the evaluation elements 22 and the electrode terminals 23 . As the evaluation element 22, for example, an element for evaluating a transistor or a buffer circuit formed in the semiconductor element circuit 10 can be formed. . An output signal from the evaluation element 22 is sent to an electrically connected inspection circuit (not shown) via the electrode terminal 23 .

In a partial area 20' of the TEG 20, there is a gap area where the evaluation element 22, the electrode terminal 23, and the wiring 24 are not formed. These regions 30 (310 to 390) are regions where dummy patterns can be formed (hereinafter referred to as dummy pattern formable portions 30). In the partial area 20 ′, the area occupied by the dummy pattern formable portion 30 is equal to or larger than the area occupied by the evaluation element 22 , the electrode terminal 23 and the wiring 24 .

The formation of the dummy pattern itself is arbitrary and does not affect the operation of the semiconductor element circuit 10, but suppresses dishing, which is excessive polishing of the wiring during the CMP process (planarization process) of wafer processing, In addition, the microloading effect caused by pattern sparseness is suppressed in a dry etching process such as RIE.

In the present embodiment, a pattern 40 (hereinafter referred to as a layout pattern 40) composed of patterns (hereinafter referred to as a shape evaluation pattern 40P) arranged regularly in a cell shape is formed in the dummy pattern formable portion 30. there is The shape evaluation patterns 40P are formed here as patterns corresponding to contact plugs formed in the semiconductor element circuit 10, and are arranged at a constant pitch. At the same time, the array is regularly shifted along one direction for cross-sectional shape evaluation by SEM (Scanning Electronic Microscope), that is, electron scanning microscope. The shape evaluation pattern 40</b>P is not connected to the electrode terminal 23 and the wiring 24 .

Although FIG. 2 shows the TEG pattern in the area 310 of the partial area 20', the layout pattern 40 can be arranged in other areas 320 to 390 as well. Furthermore, in areas other than the partial area 20', various types of evaluation elements are similarly provided, electrode terminals and wiring are formed accordingly, and a layout pattern is formed in the dummy pattern formable area 30 around them. 40 can be formed. Therefore, by preparing a plurality of layout patterns of different types and forming each of them in the dummy pattern formable portion 30, the contact plugs in the semiconductor element circuit 10 can be evaluated from various aspects.

FIG. 3 is a diagram showing three partial areas within the TEG 20. As shown in FIG. FIG. 4 is a diagram showing layout patterns having different shape evaluation pattern sizes.

FIG. 3 shows TEG patterns formed in three regions 20A, 20B, and 20C of the TEG 20. FIG. 20A, 20B, 20C are the same size and the TEG pattern is also identical here. In the areas 20A, 20B, 20C, layout patterns 40A, 40B, 40C having different shape evaluation pattern sizes are formed with respect to the dummy pattern formable portions 30A, 30B, 30C, respectively (however, in FIG. not shown).

In FIG. 4, the symbols of the shape evaluation patterns are represented by 40PA, 40PB and 40PC in accordance with the layout patterns 40A, 40B and 40C, respectively. As shown in FIG. 4, the size (length) r1 of the shape evaluation pattern 40PA constituting the layout pattern 40A is the smallest, the size r2 of the shape evaluation pattern 40PB of the layout pattern 40B, and the shape evaluation pattern of the layout pattern 40C. The size r3 of 40PC is larger in order. As for pitch, everything is equal here.

The shape evaluation patterns 40PA, 40PB, and 40PC have different cross-sectional shapes, depths, etc. due to differences in size. Therefore, when the semiconductor wafer 100 is manufactured by wafer processing, it is possible to evaluate the shape of the contact plugs of different sizes formed in the semiconductor element circuit 10 using the shape evaluation patterns 40PA, 40PB, and 40PC by observation with a cross-sectional SEM. can.

FIG. 5 is a cross-sectional view illustrating a shape evaluation pattern formed on the TEG 20 of the semiconductor wafer 100. As shown in FIG. For example, it corresponds to a part of a cross-sectional view obtained by scanning along line A-A' shown in FIG. The pattern for shape evaluation (denoted by reference numeral 40CH here) formed between the wiring layers PA and PB usually tapers as the depth increases.

FIG. 6 is a cross-sectional view partially showing a region of the semiconductor element circuit 10 of the semiconductor wafer 100 and a partial region of the TEG 20 different from that of FIG. The semiconductor device circuit 10 and TEG 20 regions are formed in the same wafer processing. However, an insulating layer is formed around the shape evaluation pattern 40CH. By using the cross-sectional SEM, the cross-sectional shape of the shape evaluation pattern 40CH can be observed, evaluated, and analyzed. Also, the size of the diameter R1 on the side of the wiring layer PA and the size of the diameter R2 on the side of the wiring layer PB can be measured. Therefore, by producing the semiconductor chip 100 as a prototype chip, it is possible to evaluate and analyze the contact plugs provided in the semiconductor element circuit 10 in response to the occurrence of defects during chip inspection. In addition, regardless of the occurrence of defects, it is possible to evaluate whether the cross-sectional shape of the formed layout pattern is a desired shape, and it is also possible to indirectly evaluate and analyze contact holes. A semiconductor chip as a final product may be used instead of the prototype chip.

In a cross-sectional SEM, it is necessary to scan along a line, so the area for forming a layout pattern for evaluating the cross-sectional shape is inevitably large, and many layout patterns composed of patterns for shape evaluation of different sizes are prepared. the larger the area occupied. Since the sizes of the semiconductor wafer 100 and the semiconductor chip 10' are reduced, it is difficult to arrange such a layout pattern in the TEG 20 as the pattern of the evaluation element. doesn't work.

In this embodiment, since the layout pattern composed of the shape evaluation pattern 40CH corresponding to the contact plug is formed in the dummy pattern formable portion 30, the overall pattern formation area is limited as the scribe area is reduced. It is possible to secure a sufficient occupied area even in the TEG 20 that is configured. In addition, it is also possible to perform analysis using evaluation elements in the TEG 20, and there is no need to secure an area within the TEG 20 for the cross-sectional shape evaluation pattern. Furthermore, the pattern for shape evaluation can be formed by the same wafer processing, and no special process is required.

In FIGS. 3 and 4, the shape evaluation patterns having the same shape but different sizes are formed. However, it is also possible to form a layout pattern composed of shape evaluation patterns having the same size but different pitches. . Also, layout patterns that are different in both size and pitch may be formed. In this embodiment, a contact plug, that is, a pattern in which a conductor is provided in a contact hole, is evaluated. However, a shape evaluation pattern corresponding to the contact hole may be formed. may be formed as a shape evaluation pattern for a different pattern, and evaluated and analyzed, and any layout pattern composed of patterns related to shape may be used.

On the other hand, in consideration of evaluation by surface SEM as well as cross-sectional SEM, layout patterns composed of evaluation patterns for various rectangular shapes such as squares and rectangles were prepared, and layout patterns with different surface shapes were formed. good too. This makes it possible to evaluate characteristics such as resistance.

The semiconductor wafer 100 described above is manufactured through pattern layout processing (design process), wafer processing (pre-process), and assembly/inspection (post-process). Pattern layout processing and wafer processing will be described below.

FIG. 7 is a diagram showing a flow of pattern layout processing. FIG. 8 is a diagram showing the flow of wafer processing.

A pattern layout of a semiconductor integrated circuit can be created by a CAD system. There, the pattern of the semiconductor element circuit is created, and the data of the mask pattern of the TEG 20 including the evaluation element pattern, the electrode terminal pattern, and the wiring pattern are created (S1). However, the pattern here is a mask pattern. After creation, the pattern of the semiconductor element circuit and the pattern of the TEG 20 are arranged as data in a predetermined area on the wafer (S2).

Furthermore, the pattern arrangement area of the TEG 20, that is, the pattern formation area of the entire TEG shown in FIG. FIG. 3 shows addresses A, B, and C corresponding to the areas 20A, 20B, and 20C. At the same time, a portion in each region where the pattern for shape evaluation can be arranged is determined (S3).

Then, a plurality of layout patterns having different shape evaluation pattern sizes, which are prepared in advance and stored in the memory, are arranged as dummy patterns in a predetermined address area (S4). However, dummy patterns other than the cross-sectional shape and surface shape evaluation patterns may be placed in the dummy pattern placeable portion. When the pattern layout is completed, the pattern layout data is stored in the memory (S5). After that, drawing data is created based on the pattern layout data, and a mask having a mask pattern formed thereon is manufactured.

In the wafer processing shown in FIG. 7, patterning processing (photolithography processing) using a mask is performed through processing such as film formation and photoresist coating (S11, S12). Here, the semiconductor element circuit mask and the TEG20 mask are used for exposure with an exposure apparatus.

After exposure, processing such as development, etching, photoresist removal, device isolation formation, transistor formation, and wiring formation is performed (S13, S14). Post-processes including dicing are performed on the preprocessed semiconductor wafer (S15) to obtain semiconductor chips. The obtained semiconductor chip is operated, and when a problem occurs, the cross-sectional shape evaluation pattern is evaluated and analyzed (S16).

When performing evaluation by SEM, it is possible to determine the position of the layout pattern to be evaluated by referring to the address assigned to the arrangement location of the layout pattern, set the scanning line, and observe the cross-sectional shape using the SEM. can.

The pattern layout and wafer processing described above are examples, and other steps may be added or changed. In addition, the semiconductor chip, semiconductor wafer, and pattern layout described above are also aspects of the present invention, and any embodiment derived from the configuration in which the shape evaluation pattern is formed in the dummy pattern formable portion 30 of the TEG 20 is also applicable to the present invention. Included in the description.

While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

10... Semiconductor element circuit. 10′ semiconductor chip 20 TEG 22 evaluation element 30 dummy pattern formable portion 40 layout pattern 40P shape evaluation pattern 100・Semiconductor wafer

Claims (10)

Arranging a pattern of a semiconductor element circuit in a semiconductor element circuit region,
A pattern layout method for arranging TEG patterns in a scribe area,
A pattern layout method for a semiconductor integrated circuit, wherein a layout pattern composed of a pattern for shape evaluation is arranged in a portion where a dummy pattern can be arranged in the pattern arrangement area of the TEG. 2. The pattern layout method for a semiconductor integrated circuit according to claim 1, wherein said shape evaluation pattern is a pattern corresponding to a pattern of contact plugs or vias formed in said semiconductor element circuit. 3. A pattern layout method for a semiconductor integrated circuit according to claim 1, wherein a plurality of layout patterns each comprising shape evaluation patterns of different sizes are arranged. 4. The pattern layout method for a semiconductor integrated circuit according to claim 1, wherein a plurality of layout patterns each comprising shape evaluation patterns having different pitches are arranged. 5. A pattern layout method for a semiconductor integrated circuit according to claim 1, wherein a plurality of layout patterns each composed of shape evaluation patterns having different surface shapes are arranged. 6. A pattern layout method for a semiconductor integrated circuit according to claim 1, wherein a plurality of areas in which layout patterns are to be laid out are defined for said pattern layout area of said TEG, and an address is assigned to each of the areas. A semiconductor chip manufacturing method including a photolithography process for forming a semiconductor element circuit pattern in a semiconductor element circuit area on a wafer and forming a TEG pattern in a scribe area on the wafer,
1. A method of manufacturing a semiconductor chip, wherein in a photolithography process, a layout pattern composed of a shape evaluation pattern is formed in a dummy pattern formable portion of the pattern forming area of the TEG. 8. A method for evaluating a semiconductor chip, wherein the pattern for shape evaluation is evaluated by an SEM for a semiconductor chip manufactured by the method for manufacturing a semiconductor chip according to claim 7. a semiconductor element circuit;
and a TEG provided in the scribe area,
A semiconductor chip, wherein the TEG comprises an evaluation element and a layout pattern in which a shape evaluation pattern different from the evaluation element is regularly arranged. 10. The semiconductor chip according to claim 9, wherein the shape evaluation pattern is a pattern corresponding to contact plugs or vias formed in the semiconductor element circuit.

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