JP2011216554A - Semiconductor device, layout method of semiconductor device, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an accurate and a fuss-free method for improving the visibility of a boundary of characteristic evaluation elements which are aligned at equal intervals, preventing work operation mistakes, determining positions of elements in measurement by manual probing, and probing by automatic probing using a layout coordinate.SOLUTION: If one scribe TEG is an MOSFET, it includes: an evaluation element 3; four electrode terminals 4a, 4b, 4c, and 4d; and wiring 5 electrically connecting the evaluation element and the electrode terminals, and if it is a resistor, it includes an evaluation element, two electrode terminals, and the wiring 5 electrically connecting the evaluation element 3 and the electrode terminal. The variously sized electrode terminals are aligned at different magnitudes at equal pitches. A wiring dummy is disposed at each wiring layer at a scribe region 2 so as to avoid a region wherein the evaluation element, the electrode terminals, and the wiring electrically connecting the evaluation element and the electrode terminal of the scribe TEG exist.

Description

  The present invention relates to a semiconductor device, and more particularly to the shape of an electrode terminal provided in a TEG (Test Element Group) which is a circuit for evaluating element characteristics.

  A semiconductor device is formed by forming a large number of circuit elements such as transistors, resistors, and capacitors on a semiconductor substrate, and connecting the circuit elements so as to perform required circuit operations and functions. In order to perform the required circuit operation and function, it is necessary to inspect and evaluate whether the transistors, resistors, capacitors, and the like have the required characteristics at the manufacturing stage. The number of evaluation elements necessary for inspection is increasing as semiconductor devices are miniaturized, multilayered, and highly functional.

  Therefore, a large number of evaluation elements are packed and arranged in a minute semiconductor device. As a result, there is a problem that it takes time and effort to generate an operation error, to determine the position of the evaluation element in the measurement by manual probing, and to check whether the probing by the automatic probing using the arrangement coordinates is correctly performed. Therefore, a method for easily determining the position of the evaluation element is desired.

  FIG. 1 is a plan view schematically showing an enlarged part of a scribe region related to the configuration of the prior art. FIG. 2 is a plan view schematically showing an enlarged part of a scribe region where a scribe TEG (Test Element Group) shown in FIG. 1 is arranged. The same parts in FIGS. 1 and 2 are denoted by the same reference numerals, and the description thereof is omitted. The TEG is an evaluation element for finding a design or manufacturing problem that occurs in an LSI (Large Scale Integration).

  The LSI chip 1 is formed in a lattice shape on a wafer surface, and a scribe region 2 for cutting the chip is formed around the LSI chip 1. A scribing TEG evaluation element 3 and a scribing TEG electrode terminal 4 are formed in the scribe region 2.

  If one scribe TEG is a MOSFET (Metal Oxide Field Effect Effect Transistor), the evaluation element 3, the four electrode terminals 4a, 4b, 4c, 4d, the evaluation element 3, and the electrode terminals 4a, 4b, 4c, A wiring 5 for electrically connecting 4d is provided. Moreover, if it is a resistor, the evaluation element 3, the two electrode terminals 4a and 4b, and the wiring 5 that electrically connects the evaluation element 3 and the electrode terminals 4a and 4b are provided.

  The electrode terminals 4a, 4b, 4c, and 4d have the same size / shape (uniform size / shape) and are arranged at an equal pitch. Although not shown in FIG. 1, as shown in FIG. 2, the scribe region 2 includes an evaluation element 3 for the scribe TEG, electrode terminals 4a, 4b, 4c, and 4d of the scribe TEG, and an evaluation of the scribe TEG. A wiring dummy 6 is arranged for each wiring layer so as to avoid a region where the wiring 5 connecting the element 3 and the electrode terminal of the scribe TEG exists.

  In the scribe TEG configured by the conventional method, it is difficult to determine the boundary of the scribe TEG, so that a measurement error is likely to occur. When a character for recognition is added in the vicinity of the electrode terminal so as to improve the visibility, the arrangement area of the scribe TEG is increased.

The reason why it is difficult to distinguish is as follows.
1. For repeated electrode terminals of the same size / shape.
2. Wiring dummy is arranged, and it is difficult to see the wiring that electrically connects the evaluation element and the electrode terminal.
3. The electrode terminal and the evaluation element are separated.

  As a related technique, Japanese Unexamined Patent Application Publication No. 2006-339548 (Patent Document 1) discloses a semiconductor device. This semiconductor device includes an LSI chip formed by integrating internal circuits made of semiconductor elements, and a scribe TEG formed on a scribe region around the LSI chip and formed with an evaluation element and electrode terminals. At least one of the evaluation elements of the scribe TEG and the electrode terminal of the scribe TEG are formed separately in different regions in the scribe region, and are electrically connected to each other.

JP 2006-339548 A

  An object of the present invention is to provide a semiconductor device in which the electrode terminals of the characteristic evaluation element are nonuniform in size / shape while maintaining an equal pitch.

  The semiconductor device of the present invention includes an evaluation element provided in a TEG (Test Element Group), a plurality of electrode terminals provided in the TEG, and a wiring that electrically connects each of the evaluation element and each of the plurality of electrode terminals. It comprises. The electrode terminals are arranged in a different shape and at equal pitches.

  The semiconductor device layout method of the present invention is implemented by a computer. In this semiconductor device layout method, an evaluation element is provided in the TEG. A plurality of electrode terminals are provided on the TEG. Further, a wiring for electrically connecting the evaluation element and each of the plurality of electrode terminals is provided. At this time, the electrode terminals are arranged at equal pitches in different shapes.

  The program of the present invention includes a step of providing an evaluation element in the TEG, a step of providing a plurality of electrode terminals in the TEG, a step of providing wiring for electrically connecting the evaluation element and each of the plurality of electrode terminals, This is a program for causing a computer to execute a step of arranging terminals at equal pitches in different shapes. The program can be stored in a storage device or a storage medium (media).

  The visibility of the boundaries of characteristic evaluation elements arranged at equal pitch has been improved, and it has been troublesome to determine the position of evaluation elements in manual probing and to check whether probing is performed correctly using automatic probing using the arrangement coordinates. And solve the problem of taking time.

It is a top view of a prior art. It is a top view of a prior art. It is a top view by a 1st embodiment of the present invention. It is a top view by a 1st embodiment of the present invention. It is a top view by a 2nd embodiment of the present invention. It is a top view by a 2nd embodiment of the present invention. It is a block diagram which shows the structural example of the computer which concerns on this invention. It is a flowchart of the program execution process which concerns on this invention.

<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.
FIG. 3 is a plan view schematically showing an enlarged part of the scribe area according to the present embodiment. FIG. 4 is a plan view schematically showing an enlarged part of a scribe region where the scribe TEG (Test Element Group) of FIG. 3 is arranged. Parts identical to those in FIGS. 1 and 2 showing the conventional example are given the same reference numerals, and the description thereof is omitted. 3 and 4 are given the same reference numerals, and description thereof is omitted.

  If one scribe TEG in the present embodiment is a MOSFET, the evaluation element 3, the four electrode terminals 7a, 7b, 7c, and 7d, and the evaluation element 3 and the electrode terminals 7a, 7b, 7c, and 7d are electrically connected. Wiring 5 connected to is provided. In the case of a resistor, the evaluation element 3, the two electrode terminals 7 a and 7 b, and the wiring 5 that electrically connects the evaluation element 3 and the electrode terminals 7 a and 7 b are provided.

  The electrode terminals 7a, 7b, 7c, and 7d have different sizes / shapes (non-uniform sizes / shapes) and are arranged at an equal pitch. In order to ensure the stability of probing, the length of one side of the electrode terminal needs to be 40 μm or more. In the figure, the electrode terminal is shown as a rectangle, but it may be a polygon such as a hexagon or a circle. Although not shown in FIG. 3, as shown in FIG. 4, the scribe region 2 includes an evaluation element 3 for the scribe TEG, electrode terminals 7a, 7b, 7c, and 7d for the scribe TEG, and an evaluation of the scribe TEG. A wiring dummy 6 is arranged for each wiring layer so as to avoid a region where the wiring 5 connecting the element 3 and the electrode terminal of the scribe TEG exists.

  In the determination of the position of the element in the measurement by manual probing and the check of whether the probing by the automatic probing using the arrangement coordinates is correctly performed, the position of the target evaluation element is recognized by comparing with the drawing showing the arrangement position. To do.

  In order to recognize the position of the target evaluation element, the boundary of the evaluation element is pattern-recognized by the size of the electrode terminals having different sizes / shapes, which is a feature of the first embodiment of the present invention, and the position is determined.

  Conventionally, the boundary between the scribe TEGs has been difficult to distinguish because the size of the electrode terminal is constant, the evaluation element or the connection wiring is hidden by the wiring dummy, or the electrode terminal is separated from the evaluation element. It was. As a result, it was easy to cause an operation error such as probing with the electrode terminal shifted by one terminal.

  It was difficult to check the state where one terminal was shifted in checking whether the probing in the automatic probing was performed correctly.

  Although the boundary can be determined by arranging the pattern of the recognition character and the recognition symbol in the vicinity of the scribe TEG, this method causes an increase in the area of the TEG pattern.

  In order to solve these problems, as shown in FIG. 3 and FIG. 4, electrode terminals 7 a, 7 b, 7 c, and 7 d having different sizes / shapes are used for MOSFETs, and electrode terminals 7 a and 7 b are used for resistors. By using it, the boundary can be easily distinguished. As a result, it is possible to prevent work mistakes and shorten the probing state check time.

Second Embodiment
Below, 2nd Embodiment of this invention is described with reference to an accompanying drawing.
FIG. 5 is a plan view schematically showing this embodiment. FIG. 6 is a plan view schematically showing an enlarged part of FIG. The same parts as those of the first embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  If one scribe TEG in the present embodiment is a MOSFET, the evaluation element 3, the four electrode terminals 7a, 7b, 7c, and 7d, and the evaluation element 3 and the electrode terminals 7a, 7b, 7c, and 7d are electrically connected. Wiring 5 connected to is provided. In the case of a resistor, the evaluation element 3, the two electrode terminals 7 a and 7 b, and the wiring 5 that electrically connects the evaluation element 3 and the electrode terminals 7 a and 7 b are provided.

  The electrode terminals 7a, 7b, 7c, and 7d have different sizes / shapes (non-uniform sizes / shapes) and are arranged at an equal pitch. In order to ensure the stability of probing, the length of one side of the electrode terminal needs to be 40 μm or more. In the figure, the electrode terminal is shown as a rectangle, but it may be a polygon such as a hexagon or a circle. Although not shown in FIG. 5, as shown in FIG. 6, the scribing region 2 includes the scribing TEG evaluation element 3, the scribing TEG electrode terminals 7 a, 7 b, 7 c and 7 d, and the scribing TEG evaluation. A wiring dummy 6 is arranged for each wiring layer so as to avoid a region where the wiring 5 connecting the element 3 and the electrode terminal of the scribe TEG exists.

  The reason why the operation and the problem are solved is the same as in the first embodiment of the present invention.

  In the first embodiment of the present invention, the TEGs are only arranged in a row and are improvements related to the determination of the upper and lower boundaries. In the second embodiment of the present invention, the TEGs are arranged in an array. An improvement for facilitating the determination of the upper, lower, left, and right TEG boundaries is shown.

  Note that the above embodiments can be implemented in combination.

<Layout design and manufacturing of semiconductor devices>
It is conceivable to design the layout of the semiconductor device in each embodiment of the present invention by a computer. As an example of such a computer, a PC (personal computer), a thin client server, a workstation, a mainframe, a supercomputer, and the like can be considered. However, actually, it is not limited to these examples.

  Here, the layout design by the computer is the layout method of the semiconductor device of the present invention. In addition, in order to cause a computer to execute the semiconductor device layout method of the present invention, a case of executing a semiconductor device layout program of the present invention may be considered. Actually, not only the layout method but also a semiconductor manufacturing method based on the layout may be used.

<Hardware configuration of computer>
FIG. 7 shows a configuration example of the computer as described above. The computer 100 as described above includes a processing device 101, a main storage device 102, a secondary storage device 103, a storage medium insertion port 104, and a network interface 105. If the computer 100 already holds the program 150 and does not need to be acquired from the outside, the storage medium insertion port 104 and the network interface 105 may be omitted. The program 150 is a computer-readable program for causing the computer 100 to perform the semiconductor device layout method (or the semiconductor manufacturing method based on the layout) of the present invention. Here, it is assumed that the processing device 101, the main storage device 102, the secondary storage device 103, the storage medium insertion port 104, and the network interface 105 are connected to each other via a data bus. Although not particularly illustrated, in practice, the computer 100 may further include an input device, a display device, and the like.

  The processing apparatus 101 reads the program 150 and actually executes the program 150. As an example of the processing apparatus 101, a CPU (Central Processing Unit), a microprocessor (microprocessor), a microcontroller, or a semiconductor integrated circuit (Integrated Circuit (IC)) having a similar function can be considered. However, actually, it is not limited to these examples.

  The main storage device 102 temporarily stores the program 150 and data being processed when the processing device 101 is actually executing the program 150. Examples of the main storage device 102 include a RAM (Random Access Memory), a ROM (Read Only Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory), a flash memory, or a combination thereof. However, actually, it is not limited to these examples.

  The secondary storage device 103 stores the program 150 and provides the processing device 101 with the program 150. Here, the secondary storage device 103 stores a program 150, data used for processing, and processing result data. When the processing device 101 loads the program 150 directly from the storage medium 200 and temporarily stores the program 150 in the main storage device 102, the secondary storage device 103 does not need to store the program 150. good. Examples of the secondary storage device 103 include an HDD (Hard Disk Drive) and an SSD (Solid State Drive). The secondary storage device 103 is not necessarily built in the computer 100. For example, the secondary storage device 103 may be a peripheral device (such as an external HDD). However, actually, it is not limited to these examples.

  When the computer acquires a program from the storage medium, the computer 100 reads the storage medium 200 via the storage medium insertion port 104. The storage medium 200 is a storage medium that stores the program 150. Examples of the storage medium 200 include a DVD (Digital Versatile Disk), a USB memory (Universal Serial Bus memory), an SD card (Secure Digital memory card), and other memory cards. The storage medium 200 may be an electronic device connected to a computer via a USB cable or the like. Because it is essentially the same. However, actually, it is not limited to these examples.

  The storage medium insertion port 104 is an insertion port for reading the storage medium 200 by arranging the storage medium 200. Here, the storage medium insertion port 104 reads the program 150 stored in the storage medium 200 when the storage medium 200 is arranged. Examples of the storage medium insertion port 104 include a DVD drive (DVD drive), a USB port, an SD card slot, and a connection port (connector) into which various cables compliant with standards other than USB are inserted. However, actually, it is not limited to these examples.

  When the computer acquires a program via a network, the computer 100 communicates with the external storage device 300 via the network interface 105. The external storage device 300 is an external storage device that stores the program 150. Examples of the external storage device 300 include an external server (Web server, file server, etc.), DAS (Direct Attached Storage), FC-SAN (Fibre Channel-Storage Area Network), NAS (Network Attached Storage), IP-Storage (IP-Storage). IP-Storage Area Network) is conceivable. However, actually, it is not limited to these examples.

  The network interface 105 communicates with the external storage device 300 via the network. When the computer 100 is a server that receives a request for layout design of a semiconductor device from another terminal, the network interface 105 receives necessary data from the other terminal via the network, and processes layout data and the like. Reply the result. Examples of the network interface 105 include a network adapter such as a NIC (Network Interface Card), a communication device such as an antenna, and a communication port such as a connection port (connector). Examples of the network include the Internet, a LAN (Local Area Network), a wireless LAN (Wireless LAN), a backbone (Backbone), a cable TV (CATV) line, a fixed telephone network, a mobile phone network, a leased line (lease line), IrDA (Infrared Data Association), Bluetooth (registered trademark), a serial communication line, and the like are conceivable. However, actually, it is not limited to these examples.

<Processing by program execution>
FIG. 8 shows an operation when the computer as described above executes a computer-readable program for causing the semiconductor device layout method (or the semiconductor manufacturing method based on the layout) of the present invention to be executed.

(1) Step S1
In the computer 100, the processing device 101 reads the program 150 and executes the program 150.

(2) Step S2
The processing apparatus 101 provides an evaluation element in a TEG (Test Element Group) according to the program 150.

(3) Step S3
The processing apparatus 101 provides a plurality of electrode terminals in the TEG according to the program 150. At this time, the processing apparatus 101 arranges the electrode terminals in different shapes and at equal pitches. Alternatively, the electrode terminals are arranged at equal pitches with different sizes. When the shape of each electrode terminal is unified into a rectangle and the electrode terminals are arranged at equal pitches with different sizes, the length of one side of the electrode terminal is set to 40 μm or more. This is because the length of one side of the electrode terminal needs to be 40 μm or more in order to ensure the stability of probing.

(4) Step S4
The processing apparatus 101 provides wiring for electrically connecting the evaluation element and each of the plurality of electrode terminals according to the program 150.

(5) Step S5
The processing apparatus 101 arranges the TEG designed as described above on the semiconductor device according to the program 150. Here, the processing apparatus 101 arranges TEGs in an array on a semiconductor device.

  When the computer 100 controls a semiconductor device manufacturing apparatus, the processing apparatus 101 actually designs the TEG as described above for the manufacturing apparatus and places the TEG on the semiconductor device. Send instructions / commands to that effect.

<Summary>
As described above, in the present invention, in the semiconductor device, the size / shape of the electrode terminals of the characteristic evaluation element are made non-uniform while maintaining the same pitch.

  According to the present invention, the visibility of the boundaries of the characteristic evaluation elements arranged at the same pitch is improved, work errors are prevented, the position of the element is determined in the measurement by manual probing, and the automatic probing using the arrangement coordinates is used. It can solve the problem that it takes time and labor to check whether probing is performed correctly.

  As mentioned above, although embodiment of this invention was explained in full detail, actually, it is not restricted to said embodiment, Even if there is a change of the range which does not deviate from the summary of this invention, it is included in this invention.

DESCRIPTION OF SYMBOLS 1 ... LSI chip 2 ... Scribe area 3 ... Evaluation element 4a, 4b, 4c, 4d ... Electrode terminal (size / shape is uniform)
5 ... Wiring 6 ... Wiring dummy 7a, 7b, 7c, 7d ... Electrode terminal (size / shape is not uniform)
DESCRIPTION OF SYMBOLS 100 ... Computer 101 ... Processing apparatus 102 ... Main storage device 103 ... Secondary storage device 104 ... Storage medium insertion port 105 ... Network interface 150 ... Program 200 ... Storage medium (media)
300 ... External storage device

Claims (12)

An evaluation element provided in a TEG (Test Element Group);
A plurality of electrode terminals provided in the TEG;
A wiring for electrically connecting the evaluation element and each of the plurality of electrode terminals;
The respective electrode terminals are arranged in a different shape and at equal pitches. Semiconductor device. The semiconductor device according to claim 1,
Each of the electrode terminals is arranged in an equal pitch with a different size. The semiconductor device according to claim 2,
The length of one side of the electrode terminal is 40 μm or more. A semiconductor device according to any one of claims 1 to 3,
The TEGs are arrayed in a semiconductor device. A layout method of a semiconductor device implemented by a computer,
Providing an evaluation element in a TEG (Test Element Group);
Providing the TEG with a plurality of electrode terminals;
Providing wiring for electrically connecting the evaluation element and each of the plurality of electrode terminals;
A method of laying out a semiconductor device, comprising arranging the electrode terminals in different shapes and at equal pitches. A semiconductor device layout method according to claim 5, comprising:
The semiconductor device layout method further includes arranging the electrode terminals at different pitches at equal pitches. A layout method of a semiconductor device according to claim 6,
A layout method of a semiconductor device, further comprising setting the length of one side of the electrode terminal to 40 μm or more. A semiconductor device layout method according to any one of claims 5 to 7,
A semiconductor device layout method further comprising arranging the TEGs in an array. Providing an evaluation element in a TEG (Test Element Group);
Providing a plurality of electrode terminals on the TEG;
Providing a wiring for electrically connecting the evaluation element and each of the plurality of electrode terminals;
A program for causing a computer to execute the step of arranging the electrode terminals in different shapes and at equal pitches. The program according to claim 9, wherein
A program for causing a computer to further execute a step of arranging the respective electrode terminals in different sizes at equal pitches. The program according to claim 10,
A program for causing a computer to further execute a step of setting the length of one side of the electrode terminal to 40 um or more. A program according to any one of claims 9 to 11,
A program for causing a computer to further execute the step of arranging the TEGs in an array.

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