JP2008071999A - Semiconductor device, inspection method therefor, and inspection method for inspecting apparatus of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can judge whether or not a probe is properly in contact with a pad of the semiconductor device without preventing the multi-pinning and pinch-pitching, and its inspection method as well as an inspection method for an inspecting device of the semiconductor device. <P>SOLUTION: The semiconductor device has alignment pads 4 and 6 composed of multiple rectangular pads lined up in series in directions longitudinal and lateral to an LSI chip 2 in respective lengthwise and crosswise directions of the LSI chip 2 and arranged in a semiconductor wafer 1's dicing-line region 8 near the LSI chip 2, and inspection pads 5 and 7 formed for alignment positions detection such that they pair with the alignment pads 4 and 6, wherein the alignment pads 4 and 6 and the detection pads 5 and 7 twin to them are electrically connected through metal wiring formed on the semiconductor wafer 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a contact position between a probe mounted on a tester and a pad serving as an input / output terminal or a power supply terminal of the integrated circuit in a test process of the integrated circuit formed on the wafer in a wafer state during the manufacture of the semiconductor device. The present invention relates to a semiconductor device that performs alignment, an inspection method thereof, and an inspection method of an inspection device for a semiconductor device.

  When conducting a confirmation test of electrical characteristics at the wafer stage during the manufacture of a semiconductor device such as an LSI chip, a test probe is brought into contact with a pad serving as an input / output terminal or a power supply terminal provided in the semiconductor device, In this state, signals corresponding to various tests are supplied from the tester to the semiconductor device via the probe. The semiconductor device operates in accordance with the supplied input signal and power supply. By taking the output signal of the semiconductor device back into the tester, the quality of the semiconductor device is determined.

  Therefore, when performing such a test, it is necessary to perform alignment in advance so that the probe is in good contact with the pad of the semiconductor device.

  In recent years, when the number of pins of a semiconductor device is increased and the pitch is increased, the amount of positional deviation between the pads of the semiconductor device and the probe is extracted by image processing, and the positional deviation amount is feedback-controlled. Thus, the alignment is automatically performed.

  However, the positioning of the probe and the pad is finally finely adjusted visually regardless of the presence or absence of the alignment function by the image processing of the prober device. As a result, as the number of pins increases and the pitch decreases, visual contact alignment and fine adjustment become difficult.

  Therefore, in order to accurately align the probe and each pad of the semiconductor device, it is possible to confirm by visual inspection or needle mark inspection of an image at the present stage, but it takes time and much labor for the determination. However, since it has already been tested when it can be confirmed by needle mark inspection, it can be discovered only at a stage where processing has progressed to some extent.

As a conventional technique for determining whether or not the probe is accurately in contact with the pad of the semiconductor device with a relatively simple configuration, “integrated circuit” disclosed in Patent Document 1 and “Patent Document 2” are disclosed. Semiconductor device and alignment method of the semiconductor device ”, and“ Semiconductor device and test method thereof ”disclosed in Patent Document 3.
JP-A-1-129432 JP-A-9-107011 JP-A-9-260443

The invention disclosed in Patent Document 1 can confirm the alignment of the contact, but there is a problem that when the position of the contact is deviated, the direction of deviation cannot be confirmed except by visual observation.
In addition, an alignment pad for detecting misalignment is provided in the substrate. However, it is necessary to provide an alignment pad individually under the situation where the number of pins of the semiconductor device is increased and the pitch is increased, making it difficult to secure the space. It becomes. Furthermore, there is a problem in that it is not possible to arrange individual alignment pads in the chip due to restrictions and hindrances when the number of pins is increased and the pitch is increased.

  The invention disclosed in Patent Document 2 is a method for easily determining whether or not a semiconductor device is accurately aligned with a test probe, by connecting a pad and an outer peripheral pad to a ground resistance, respectively. In addition, each grounding resistor is set to have a different resistance value, is made to correspond to the alignment pad, an alignment probe is provided, and energization is performed while the alignment probe is in contact with the semiconductor device. The position of the semiconductor device is determined based on the detected output of the voltage value, and the position of the semiconductor device is determined.

  However, pad debris usually adheres to the probe when the probe is connected to the pad for each measurement. As a result, contact resistance occurs in the probe and the detection output value is shifted, so the output value according to the position shift state is measured and compared based on the data of those output results. Different voltage values having no correlation are shown, and it is impossible to accurately determine the quality of the positional deviation and the degree (direction and distance) of the positional deviation.

  In the invention disclosed in Patent Document 3, the first pad pair, the second pad pair, the third pad pair, and the fourth pad pair are provided for each integrated circuit in the scribe line region of the semiconductor wafer, or A plurality of integrated circuits are formed for each predetermined region, and are based on voltage state detection outputs in the first pad pair, the second pad pair, the third pad pair, and the fourth pad pair. Check the direction of displacement of the probe relative to the pad in the corrector circuit to check whether the contact alignment is correct, and if contact displacement occurs, before the probe protrudes from the pad of each terminal It is easy to recognize how much and in which direction it is displaced.

However, when the positioning probe is in contact with the positioning pad due to misalignment, the probe is in contact with the positioning pad unless the integrated circuit probe comes off the integrated circuit pad. Even if a deviation occurs, the detected potential does not change, and the degree (distance) of the positional deviation cannot be accurately recognized.
Accordingly, the correction fine adjustment of the deviation cannot be easily performed.

  As described above, conventionally, it has not been possible to determine whether or not the probe is accurately in contact with the pad of the semiconductor device without hindering the increase in the number of pins of the terminal and the reduction in pitch.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a semiconductor device that can determine whether a probe is accurately in contact with a pad of a semiconductor device without interfering with an increase in the number of pins or a narrow pitch, and an inspection thereof It is an object of the present invention to provide a method and an inspection method for an inspection apparatus for a semiconductor device.

In order to achieve the above object, the present invention provides, as a first aspect, a semiconductor device including a semiconductor wafer on which a plurality of integrated circuits are formed, for each vertical and horizontal direction of each chip of the plurality of integrated circuits. An alignment pad that is arranged in a dicing line area of a semiconductor wafer in the vicinity of the chip and includes an alignment pad for detecting the alignment position. Each of the rectangular pads has an alignment detection pad formed as a pair, and the alignment pad and the alignment detection pad paired therewith are electrically connected via a metal wiring formed on the semiconductor wafer. The present invention provides a semiconductor device characterized in that the semiconductor device is connected.
According to the first aspect of the present invention, a dedicated alignment pad and a dedicated detection pad are formed on a dicing line in the vicinity of the chip without providing a conventional alignment pad for positioning in the chip. . In recent years, semiconductor products have a tendency to reduce the chip size even if the products have the same function due to miniaturization of process rules. On the other hand, the size of the pad has not been relatively reduced due to problems of wire bonding accuracy and probe card alignment accuracy during wafer testing. Providing a dedicated pad for misalignment alignment in addition to the normal pad in the chip leads to an increase in the chip area and, consequently, an increase in cost. According to this aspect, this problem can be solved or its influence can be reduced.

In order to achieve the above object, according to a second aspect of the present invention, there is provided a semiconductor device inspection method according to the first aspect of the present invention, wherein any one of the alignment pads is used. A method for inspecting a semiconductor device is provided, wherein a predetermined voltage determined by an inspection tester is applied via an alignment probe to inspect which of the alignment detection pads detects the voltage. Is.
According to the second aspect of the present invention, not only the alternative determination of only the quality of the positional deviation as in the prior art but also the positional deviation occurs even when the contact resistance is generated in the probe and the measured value changes. If so, it can be easily determined how much distance is shifted in which direction.

In the second aspect of the present invention, the position of the alignment probe in the alignment pad when the needle is aligned using the pad in the integrated circuit chip is stored as an initial position, and the probing process is performed with respect to the stored position. It is preferable to determine the amount and direction of deviation during the test. Thus, since the fine adjustment of the alignment can be performed while checking the contact position of the probe, the labor required for the alignment can be greatly reduced as compared with the conventional visual alignment operation. In addition, it is possible to determine the shift amount and the shift direction in real time.
In addition to this, it is preferable to perform a warning / warning display when the amount of deviation from the initial position exceeds a predetermined size. This allows early detection of misalignment during the test.

  In order to achieve the above object, according to a third aspect of the present invention, there is provided an inspection method for an inspection apparatus for a semiconductor device according to the first aspect of the present invention. On the other hand, a predetermined voltage determined by an inspection test machine is applied via an alignment probe, and the pad in the integrated circuit chip is inspected based on which of the alignment detection pads detects the voltage. Therefore, the present invention provides an inspection method for an inspection apparatus for a semiconductor device, characterized by measuring a wear amount of a contact for the purpose.

  In the third aspect of the present invention, it is preferable to accumulate contact wear amount data and predict the contact replacement time based on the accumulated data.

  According to the present invention, there is provided a semiconductor device that can determine whether or not a probe is accurately in contact with a pad of a semiconductor device, without interfering with an increase in the number of pins or a narrow pitch, and an inspection method for the semiconductor device. An inspection method can be provided.

  A preferred embodiment of the present invention will be described. FIG. 1 shows the configuration of an LSI chip according to this embodiment. In the LSI chip 2, dedicated alignment pads 4 and 6 and dedicated detection pads 5 and 7 are formed on a dicing line in the vicinity of the LSI chip 2, separately from the pads 3 serving as normal input / output terminals and power supply terminals. Has been.

FIG. 2 shows an LSI chip 2 (X portion in FIG. 1) cut out from the semiconductor wafer 1.
The alignment pads 4 and 6 and the detection pads 5 and 7 are provided on the dicing line region 8. The dicing line area 8 is an area provided for individually separating chips aligned in the wafer. In this area, an X-side alignment pad 4 is provided in the lower right corner direction of the substrate, and an X direction in the right direction. A side detection pad 5 is provided. Also, a Y-side alignment pad 6 is provided in the upper right corner direction of the base, and a Y-side detection pad 7 is provided in the upper direction.

FIG. 3 shows an enlarged shape of the alignment pad.
The alignment pads 4 and 6 have the same shape, but are rotated 90 degrees in the arrangement direction.
As the alignment pads, rectangular pads of size L2 × L3 are arranged until the length becomes L1 with an interval of a pitch L4, and each pad has a one-to-one correspondence with a detection pad for extracting output potential. To connect to.

  The pad total length L1 and the rectangular pad length L2 are appropriately set by adding a value in consideration of variations in probe production to the length of one side of the normal pad 3. The rectangular pad width L3 is set larger than the probe tip diameter, and the pitch size L4 is set smaller than the probe tip diameter.

FIG. 4 shows the connection relationship between the alignment pad and the detection pad.
AX to FX of the alignment pad 4 are electrically connected to aX to fX of the detection pad 5 in pairs and are detected when a voltage is applied to the alignment pad 4. An electrical characteristic test can be performed by measuring whether or not a voltage appears on the pad 5 for use.

  As shown in FIG. 5, AY to FY of the alignment pad 6 and aY to fY of the detection pad 7 are also electrically connected to each other by an aluminum wiring in the chip, and a voltage is supplied to the alignment pad 6. When the voltage is applied, an electrical characteristic test can be performed by measuring whether or not a voltage appears on the detection pad 7.

  In the electrical characteristic test, the alignment probe contacts one of the individual rectangular pads of the alignment pad, and a voltage is applied. Which individual pad of the detection pads among the detection pads through the rectangular pad is contacted with the detection probe to detect the voltage output and determine the degree of misalignment of the semiconductor device. Alignment is performed.

Next, a procedure for aligning each pad of the LSI chip 2 with the probe will be described.
FIG. 6 shows the actual contact state between the probes 9, 10, 11 and the LSI chip 2.
7 to 11, when the probe 9 is displaced with respect to the integrated circuit pad 3, the probe 10 is aligned with the alignment pads 4 and 6 and the probe 11 is detected with respect to the detection pads 5 and 7. The position where the contact is made will be described.
FIG. 7 shows a state where the probe is displaced upward with respect to the tip. FIG. 8 shows a state where the probe is displaced downward with respect to the tip. FIG. 9 shows a state in which the probe is shifted to the left with respect to the tip. FIG. 10 shows a state where the probe is displaced to the right with respect to the tip. FIG. 11 shows a state in which the probe is removed from the pads in the integrated circuit with respect to the chip.

  When testing various electrical characteristics of the LSI chip 2 with a tester, the probe card attached to the tester is separate from the integrated circuit pad probe 9 to be in contact with a pad serving as a normal input terminal or power supply terminal. A dedicated alignment pad probe 10 corresponding to the alignment pads 4 and 6 and a dedicated detection pad probe 11 corresponding to the detection pads 5 and 7 are newly provided.

  When the alignment pad probe 10 comes into contact with the alignment pad, a voltage is applied from the tester to the alignment pads 4 and 6 through the alignment pad probe 10, and at that time, the detection pad 5, The individual pad of 7 is detected with a tester by contacting the detection pad probe 11 to determine which individual pad has the voltage value.

  From each alignment pad probe 10, for example, a voltage of 3 V is applied to the alignment pads 4 and 6. This numerical value is merely an example, and the present invention is not limited to this.

  As shown in FIG. 6, when the positioning of the LSI chip 2 is accurately performed, the contact position of the probe 9 with respect to the pad 3 in the integrated circuit is set as the origin of the XY coordinates. At the origin, only the rectangular pads CX and CY of the alignment pads 4 and 6 are individually in contact with each other. Detection pads cX and cY that are pairs of rectangular pads CX and CY are provided, and these are electrically connected by an aluminum wiring or the like in the chip. Therefore, when a predetermined voltage is applied from the tester to the rectangular pad CX of the alignment pad 4 and the rectangular pad CY of the alignment pad 6 via the alignment pad probe 10, the detection pad probe 11. A predetermined voltage is detected by cx of the detection pad 5 and cy of the detection pad 7 by a tester via the circuit.

On the other hand, for example, as shown in FIG. 7, when the probes 9, 10, 11 are slightly shifted upward with respect to the LSI chip 2, the rectangular pad of the alignment pad 6 with which the alignment probe 10 contacts is , CY changes to BY. As a result, the rectangular pad from which the potential appearing on the detection pad 7 is detected also changes from the cy position to the by position.
At this time, the alignment pad 4 that is not displaced in the horizontal direction remains in contact with the rectangular pad CX. Therefore, a predetermined voltage is detected at the detection pad 5 by the rectangular pad cx.

As shown in FIG. 8, when the probes 9, 10, and 11 are slightly shifted downward with respect to the LSI chip, the rectangular pad of the alignment pad 6 that the alignment probe 10 contacts is changed from CY to DY. Changes to. As a result, the rectangular pad from which the potential appearing on the detection pad 7 is detected also changes from cy to dy.
At this time, the rectangular pad of the alignment pad 4 that is not displaced in the horizontal direction is still in contact with the rectangular pad CX. Therefore, a predetermined voltage is detected at the detection pad 5 by the rectangular pad cx.

As shown in FIG. 9, when the probes 9, 10, and 11 are slightly shifted to the left with respect to the LSI chip 2, the rectangular pad of the alignment pad 4 that the alignment probe 10 contacts is CX. Changes to DX. As a result, the rectangular pad from which the potential appearing on the detection pad 5 is detected also changes from cX to dX.
At this time, the alignment pad 6 that is not displaced in the vertical direction is still in contact with the rectangular pad CY. Therefore, in the detection pad 7, the voltage is detected by the rectangular pad cy.

  As shown in FIG. 10, when the probes 9, 10, and 11 are slightly shifted to the right with respect to the LSI chip 2, the rectangular pad of the alignment pad 4 with which the alignment probe 10 contacts is CX. Changes from BX to BX. As a result, the rectangular pad from which the potential appearing on the detection pad 5 is detected also changes from cx to bX.

  Further, as shown in FIG. 11, the probes 9, 10, and 11 are extremely displaced from side to side and up and down with respect to the LSI chip 2, so that the probe 9 to be in contact with the pad 3 serving as a normal input terminal or power supply terminal. Is removed from the pad 3, the alignment probe 10 is completely detached from the alignment pads 4, 6, and no voltage value appears on any of the detection pads 5, 7. Since the detection probe 11 is also detached from the detection pads 5 and 7, all the potentials measured by the tester via the detection pad probe 11 are open.

  As described above, when the alignment position is largely deviated, it is preferable to perform a warning or a warning display. Further, the probing process may be terminated with an error.

  In addition, the alignment position deviation is detected in the same manner as described above even when it is shifted in the diagonally upward right direction, diagonally upward left direction, diagonally downward right direction, diagonally downward left direction, clockwise rotation direction, or counterclockwise rotation direction. Table 1 shows from which detection pad the applied voltage appears with respect to the alignment position deviation.

  As described above, when the relative positions of the probes 9, 10, and 11 are shifted with respect to the LSI chip 2, the detection pads 5 and 7 have a rectangular pad that is measured in a good alignment state and The voltage values measured on the rectangular pads at different positions appear. Further, when the direction of displacement and the degree of displacement deviate from the normal pad 3, no voltage value appears on the detection pads 5 and 7. Accordingly, as shown in FIGS. 6 to 11, the voltage appears on the rectangular pads in the detection pads 5 and 7 at a position corresponding to the misalignment state. And distance).

Further, the wear of the probe 9 is lost over time, but when this wears, the position of the rectangular pad of the alignment pads 4 and 6 that the alignment probe 10 contacts when the probe 9 is correctly applied changes. Thereby, the degree of wear of the probe 9 can be detected.
Furthermore, by accumulating wear amount data, it is possible to predict when the probe 9 needs to be replaced.

In addition, the said embodiment is an example of suitable implementation of this invention, and this invention is not limited to this.
For example, the shape of the alignment pads 4 and 6 is not limited to the above example. The rectangular pad can be divided into an arbitrary number as well as being divided into six (A to F) as in the above example. If the number of divisions is increased and a corresponding detection pad is provided, the alignment accuracy can be increased.

  In the above example, the state where the needle is at the center is the initial state. However, even if the origin is not necessarily at the center, the position deviation is detected by detecting how much the data is output to the origin. Can be detected.

  As described above, the present invention can be variously modified.

It is a figure which shows the structure of the semiconductor wafer which concerns on suitable embodiment of this invention. It is a figure which shows the structure of the semiconductor chip cut out from a semiconductor wafer. It is a figure which shows the structure of the pad for alignment. It is a figure which shows the connection state of the pad for alignment, and the pad for a detection. It is a figure which shows the connection state of the pad for alignment, and the pad for a detection. It is a figure which shows the contact position of a probe when the position alignment of a LSI chip is performed correctly. It is a figure which shows the contact position of a probe when each probe has shifted | deviated slightly upwards with respect to an LSI chip. It is a figure which shows the contact position of a probe in case each probe has shifted | deviated slightly with respect to LSI chip. It is a figure which shows the contact position of a probe when each probe has shifted | deviated slightly to the left with respect to LSI chip. It is a figure which shows the contact position of a probe when each probe has shifted | deviated slightly rightward with respect to an LSI chip. It is a figure which shows the contact position of a probe when each probe has shifted | deviated to the lower left significantly with respect to an LSI chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor chip 3 Pad in integrated circuit 4, 6 Pad for alignment 5, 7 Detection pad 8 Dicing line area 9 Probe for pad in integrated circuit 10 Probe for alignment pad 11 Probe for detection pad

Claims (6)

A semiconductor device comprising a semiconductor wafer on which a plurality of integrated circuits are formed,
A dicing line region of the semiconductor wafer in the vicinity of the chip, comprising a plurality of rectangular pads arranged in series in the vertical / horizontal direction with respect to the chip for each vertical and horizontal direction of each chip of the plurality of integrated circuits. An alignment pad arranged in
An alignment detection pad formed as a pair with each of the rectangular pads of the alignment pad for alignment position detection;
The semiconductor device according to claim 1, wherein the alignment pad and the alignment detection pad paired therewith are electrically connected via a metal wiring formed on the semiconductor wafer. An inspection method for a semiconductor device according to claim 1,
A predetermined voltage determined by an inspection test machine is applied to any rectangular pad of the alignment pad via an alignment probe, and the alignment detection pad is inspected to detect the voltage. A method for inspecting a semiconductor device.   The position of the alignment probe in the alignment pad when the needle is aligned using the pad in the integrated circuit chip is stored as an initial position, and the amount and direction of deviation in the probing process with respect to the stored position The method of inspecting a semiconductor device according to claim 2, wherein determination is made during the test.   4. The method for inspecting a semiconductor device according to claim 3, wherein a warning / attention display is performed when a deviation amount with respect to the initial position exceeds a predetermined size. An inspection method for an inspection apparatus for a semiconductor device according to claim 1,
A predetermined voltage determined by an inspection and testing machine is applied to any rectangular pad of the alignment pad via an alignment probe, and based on which of the alignment detection pads the voltage is detected. A method for inspecting a semiconductor device inspection apparatus, comprising: measuring a wear amount of a contact for inspecting a pad in the integrated circuit chip.   6. The inspection method for an inspection apparatus for a semiconductor device according to claim 5, wherein data on the amount of wear of the contact is accumulated, and the replacement time of the contact is predicted based on the accumulated data.

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