JP6234797B2 - Wiring board via arrangement determination apparatus, method and program - Google Patents

Description

  The present invention relates to a wiring board via arrangement determining apparatus, method, and program, for example, a through via (through VIA) in a wiring board that is a component of a probe card for simultaneous energization testing of a plurality of electronic devices formed on a semiconductor wafer. This can be applied when determining the arrangement of through vias.

  Some probe cards test a semiconductor wafer which is a device under test on which a plurality of electronic circuits are formed (see Patent Document 1 and Patent Document 2). Such a probe card is provided with a probe holder that holds a large number of probes, one end of which is connected to each pad of the semiconductor wafer, a pad to which the other end of each probe is connected, and a tester at the peripheral edge of the upper surface. A disk-like wiring board (sometimes referred to as a card board) provided with an interface part (hereinafter referred to as a tester interface part) composed of a connector for connection.

  In this specification, the surface of the wiring board to which the other end of the probe is connected is referred to as the “lower surface” regardless of the posture of the probe card during actual use, and the surface having the interface unit for connecting to the tester. Is called the “upper surface”.

  Electronic components such as relays, capacitors, resistors, and coils are also provided on the upper surface of the wiring board. In addition, there are probe pads that need to be connected to the tester interface unit through a direct wiring path, and other probe pads that need to be connected to the tester interface unit through a wiring path via an electronic component.

  In order to realize a large number of wiring paths, conventionally, not only mere through vias but also relay through vias are employed at appropriate positions as shown in FIG. FIG. 8 is a schematic longitudinal sectional view showing a part of the longitudinal section of the wiring board.

  In FIG. 8, the wiring board 1 is obtained by bonding a top side laminated portion 2 having about 20 layers and a bottom side laminated portion 3 having about 20 layers through a bonding layer 4. The pad P5-2 of the pogo pin (which may be another type of electrical interconnection element; the electrical interconnection element including the pogo pin is called a probe in the claims) 5-2 is an electronic component. 6-2, it is necessary to connect to the pad P6-2, and when the through via is applied to the pad P5-2, the other end of the through via is located directly below the other electronic component 6-1, May adversely affect the operation of the electronic component 6-1. Therefore, a non-through via (hereinafter referred to as a bottom IVH) 7-2 that extends from the pad P5-2 of the pogo pin 5-2 to the coupling layer 4 by adopting IVH (Interstitial Via Hole) technology, In addition, a non-through via (hereinafter referred to as a top side IVH) 9-2 extending from the pad P6-2 of the electronic component 6-2 to the coupling layer 4 is provided, and an arbitrary gap is provided between the bottom side IVH 7-2 and the relay through via 8. The layer wiring 10-2 is connected, and the relay through via 8 and the top IVH 9-2 are connected by an arbitrary layer wiring 11-2.

  The pogo pins 5-1 and 5-3 to 5-5 in FIG. 8 do not need to be connected to electronic components, and the pogo pins 5-1, 5-3 and 5-5 are connected to through vias in any layer. Is connected to the tester interface unit 12 by a wiring path (not shown), and the pogo pin 5-4 is connected to the bottom side IVH and is connected to the tester interface unit 12 by a wiring path (not shown) of an arbitrary layer. .

  Conventionally, a designer has determined the layout of vias using a wiring board CAD (Computer Aided Design) so as to satisfy the following conditions and constraints (hereinafter collectively referred to as conditions).

(A) Arrangement of vias for pogo pins that need to be connected to electronic components arranged on the upper surface of the wiring board (a-1) Interference with electronic components (Hereinafter referred to as interference that may adversely affect electronic components) Only when the bottom side IVH is used.

(A-2) Through vias are used in places where through vias can be arranged, and the number of relay through vias is reduced.

(B) Arrangement of vias for pogo pins that only need to be connected to the tester interface unit (b-1) The number of pogo pins that only need to be connected to the tester interface unit is the same as the number of wires accommodated in the bottom-side stacked unit. The bottom side IVH is used.

(B-2) A through via is used for a pogo pin that exceeds the number of wires accommodated in the bottom-side laminated portion. At this time, pogo pin portions that do not interfere with the electronic components on the upper surface of the substrate are formed as through vias. In addition, this (b-2) restriction | limiting is for arrange | positioning, without increasing the number of layers of a bottom side laminated part.

JP-A-2005-17121 JP 2010-271160 A

  By the way, in a probe card, the pogo pin which forms an electrical connection between a wiring board and a semiconductor wafer may be 60,000 pins or more. It is desirable that vias connected to the pogo pins are arranged using through vias and bottom IVHs according to the above conditions. However, the function of automatically arranging vias according to such conditions does not exist in normal board design CAD, so manual placement is performed while visually checking each pogo pin on the CAD, and design time is reduced. Become enormous.

  When the determination time of the via type (through via or bottom side IVH) for one pogo pin is 10 seconds on average, the via arrangement time for all 60,000 pins takes 166 hours.

  As mentioned above, placing vias for all pogo pins in an optimal condition involves considerable difficulty.

  Therefore, as shown in FIG. 9, an area including the number of pogo pins for one DUT (Device under Test; electronic device to be tested) on a test object (semiconductor wafer) on a lattice point is treated as one block, and each block unit. In addition, after determining whether the block is a through via block or a bottom IVH block, the arrangement of each pogo pin is also determined. That is, when all through vias can be arranged at pogo pin locations in the block, all via via blocks are used, and when there is a location where even one of the pogo pins in the block cannot arrange through vias, the bottom IVH is all arranged. It is a design technique to make blocks.

  For example, if a pogo pin of 100 pins is treated as one block and the confirmation time of the via type (through via or bottom side IVH) of one block is 30 seconds, the arrangement time of all 60,000 pins is 5 hours. That is, by using this design method, the design time can be greatly shortened.

  Here, if an area of a certain pogo pin block partially overlaps with the electronic component placement area above it, the block is determined as a block on which the bottom IVH is placed, but the non-overlapping area is Ordinarily, through vias can be arranged. In this way, in the design method for determining the via type in units of blocks, the bottom side IVH may be arranged even though the through via can be arranged, so it is connected to the pogo pin that needs to be connected to the electronic component. The number of relay through vias to be greatly increased as compared to the case where the via type is not determined for each block.

  As the number of vias increases in both the top-side laminated portion and the bottom-side laminated portion, the area that can be wired in each layer decreases. That is, the wiring capacity of the layer is lowered. Excessive placement of relay through vias as described above leads to a reduction in wiring accommodation rate. Originally, when the connection between the pogo pin and the electronic component that can be connected by one layer in the top side laminated portion uses an excessive relay through via, one layer in the top side laminated portion and one layer in the bottom side laminated portion This requires a total of two layers, and the problem of lowering the wiring accommodation rate is particularly great.

  In addition, the wiring path is likely to be long due to the presence of excessive relay through vias, and there is a risk that electrical characteristics such as signals passing through the wiring path will be reduced accordingly.

  Therefore, various vias can be placed on the wiring board so that the upper and lower components required by as few vias as possible can be connected, and wiring board via placement that can reduce the man-hours and period required for the placement A determination device, method and program are desired.

  According to a first aspect of the present invention, a top surface on which a plurality of electronic components are mounted and having a plurality of interface portions to the outside, a first probe that requires connection to any one of the interface portions via any one of the electronic components, A lower surface connected to the second probe that needs to be connected to any one of the interface parts without passing through an electronic component, and the upper surface side laminated part and the lower surface side laminated part are coupled via the coupling layer. In a wiring board via arrangement determining apparatus for determining the arrangement of vias provided on a wiring board, (1) via arrangement information storage means for storing information of vias whose arrangement has been decided, and (2) based on position information of electronic components A through-via impossible area extracting means for extracting an area where a through-via cannot be arranged; and (3) a plurality of candidate points centered on each lattice point located at predetermined vertical and horizontal pitches. Through-via-placeable part extracting means for extracting a place where the through-via can be arranged based on a region where the through-via cannot be arranged and a clearance that must be secured at least between the pads on the upper surface and between the pads on the lower surface; (4) Through-via placement availability determination means for determining whether a through-via can be placed above a point where the first probe is connected based on a region where the through-via cannot be placed and a clearance; (5) Relay through via placement determining means for determining a location where a relay through via is provided from locations where the through via can be placed so that the wiring path length is shortened when the through via cannot be placed; and (6) the through via If the through vias cannot be placed, the via placement information storage means is determined. And having a via information writing means describing the information has been relayed through vias.

  According to a second aspect of the present invention, there is provided a top surface on which a plurality of electronic parts are mounted and having a plurality of interface parts to the outside, and a first probe that requires connection to any one of the interface parts via any one of the electronic parts. A lower surface connected to the second probe that needs to be connected to any one of the interface parts without passing through an electronic component, and the upper surface side laminated part and the lower surface side laminated part are coupled via the coupling layer. In the wiring board via arrangement determination method for determining the arrangement of vias provided on the wiring board, (1) the via arrangement information storage means stores information on vias whose arrangement has been determined, and (2) a through-via disabled area The extraction means extracts areas where the through vias cannot be arranged based on the position information of the electronic component, and (3) the through via arrangement possible place extraction means is located at every predetermined vertical and horizontal pitch. Through vias are arranged based on the area where through vias cannot be arranged from among a plurality of candidate points centered on the grid point and the clearance that must be secured at least between the pads on the upper surface and between the pads on the lower surface (4) The through-via placement availability determination means determines whether or not the through-via can be placed above the point where the first probe is connected based on the area where the through-via cannot be placed and the clearance. (5) The relay through via placement determination means provides the relay through via from the locations where the through via can be placed so that the wiring path length is shortened when the through via cannot be placed. (6) When the via information writing means can arrange the through via, it describes the information of the through via that can be arranged in the via arrangement information storage means, and the through via cannot be arranged. Characterized by describing the information of the relay through vias determined in the via arrangement information storage means.

  A wiring board via arrangement determination program according to a third aspect of the present invention provides a connection between an upper surface on which a plurality of electronic components are mounted and a plurality of interface portions to the outside, and any interface portion via any electronic component. And a lower surface connected to a second probe that needs to be connected to any one of the interface parts without passing through an electronic component, and the upper surface side laminated portion and the lower surface side laminated portion are coupled to each other. A computer mounted on a wiring board via arrangement determining device for determining an arrangement of vias provided on wiring boards coupled via layers; (1) via arrangement information storage means for storing information on vias whose arrangement has been determined; (2) Through-via-unavailable area extracting means for extracting areas where through-vias cannot be arranged based on position information of electronic components, and (3) positioned at predetermined vertical and horizontal pitches Penetration based on the area where through vias cannot be placed from the multiple candidate points centered on each lattice point and the clearance that must be secured at least between the pads on the upper surface and between the pads on the lower surface Through-via placement location extraction means for extracting locations where vias can be placed, and (4) placement of through-vias above the point where the first probe is connected based on the area and clearance where the through-via cannot be placed (5) When the through via cannot be arranged, the relay through via is selected from the places where the through via can be arranged so as to shorten the wiring path length. Relay through via arrangement determining means for determining a location to be provided; and (6) when the through via can be arranged, information on through vias that can be arranged in the via arrangement information storage means is described, and the through via If you can not place, characterized in that to function as a via information writing means describing the information of the relay through vias determined in the via arrangement information storage means.

  According to the present invention, various vias can be arranged on the wiring board so that the upper and lower components required by the smallest possible number of vias can be connected, and the number of man-hours and time required for the arrangement can be reduced. An arrangement determining apparatus, method, and program can be realized.

It is a block diagram which shows the hardware constitutions in the wiring board via arrangement | positioning determination apparatus of embodiment. It is explanatory drawing which shows the structure of the wiring board via arrangement | positioning determination program mounted in the wiring board via arrangement | positioning determination apparatus of embodiment. It is a flowchart which shows operation | movement of the wiring board via arrangement | positioning determination apparatus of embodiment. It is explanatory drawing of the clearance which is the distance which the other pad must ensure at least between the pads of the relay penetration via | veering taken in by the wiring board via arrangement | positioning determination apparatus of embodiment. It is a flowchart which shows the detail of the determination process of the relay penetration via corresponding to the pogo pin which applies bottom side IVH in the wiring board via arrangement | positioning determination apparatus of embodiment. It is explanatory drawing which shows the structural example of the temporary arrangement | positioning information file of a relay penetration via in the wiring board via arrangement | positioning determination apparatus of embodiment. It is a flowchart which shows the detail of the process which replaces the temporary arrangement information of a part of bottom side IVH with the penetration via arrangement information in the wiring board via arrangement determination apparatus of the embodiment. It is a schematic longitudinal cross-sectional view which takes out and shows a part of longitudinal cross-section of the wiring board of a probe card. It is explanatory drawing of the subject of the design method which determines a via kind in a block unit.

(A) Main Embodiment Hereinafter, an embodiment in which a wiring board via arrangement determining apparatus, method and program according to the present invention are applied to via arrangement in a wiring board of a probe card will be described with reference to the drawings.

(A-1) Configuration of Embodiment The wiring board via arrangement determination device of the embodiment may be constructed as a part of a wiring board CAD-dedicated device, or may be installed in a general-purpose computer such as a personal computer. Although it may be constructed by installing a wiring board via arrangement determination program, it has a hardware configuration as shown in FIG. 1, for example, regardless of which construction method is employed.

  In FIG. 1, the wiring board via arrangement determination device 20 is configured by connecting an external storage unit 22, a display unit 23, and an input unit 24 to a main control unit 21. Although omitted in FIG. 1, a printer unit and a communication unit may be connected to the main control unit 21.

  The main control unit 21 includes a CPU, a main memory, a working memory, and the like, and executes the wiring board via arrangement determination program 21P of the mounted embodiment.

  The external storage unit 22 corresponds to a memory external to the main control unit 21 such as a hard disk device or a USB memory, and stores various data. The external storage unit 22 stores, for example, board design CAD data 22A, which will be described later, and a board design CAD via additional arrangement file 22B.

  The display unit 23 is for displaying and outputting guidance information and design image information to the designer. The input unit 24 corresponds to a keyboard, a mouse, or the like, and takes in input information from a designer. That is, the display unit 23 and the input unit 24 constitute a man-machine interface with the designer.

  FIG. 2 is an explanatory diagram illustrating a functional unit (routine) configuration of the wiring board via arrangement determination program 21P according to the embodiment. Note that all or some of the functional units illustrated in FIG. 2 are not limited to a software implementation method, and may be implemented by hardware such as a dedicated chip.

  The wiring board via arrangement determination program 21P includes a design data reading unit 30, a pogo pin position extraction unit 31, an electronic component arrangement information extraction unit 32, a through via prohibited area extraction unit 33, a pogo pin classification unit 34, a clearance input reception unit 35, and relay penetration. Via placement possible location extraction unit 36, through via placement availability determination unit 37, relay through via placement unit 38, bottom side stacked portion wiring accommodation number input acceptance unit 39, bottom side IVH temporary placement unit 40, placement via information replacement unit 41 , Via arrangement information output unit 42 and the like.

  The functions executed by each of the functional units 30 to 42 will be clarified in the description of the operation described later.

(A-2) Operation of Embodiment Next, an operation (wiring board via arrangement determination method of the embodiment) executed by the wiring board via arrangement determination device 20 of the embodiment will be described with reference to the drawings. Here, FIG. 3 is a flowchart showing the operation (main flow) of the wiring board via arrangement determining apparatus 20 of the embodiment. In FIG. 3, some or all of the transitions between the processes indicated by blocks may be left to the designer's instruction, or may be automatically performed.

  When the main control unit 21 of the wiring board via arrangement determination device 20 starts the wiring board via arrangement determination method, first, the board design CAD data 22A is obtained from the external storage unit 22 in the working memory in the main control unit 21 (that is, work). Area) (step S100).

  Here, the board design CAD data 22A includes electronic component placement information on the upper surface of the wiring board, pad information on the lower surface of the wiring board, connection information between the pads, and the like.

  The electronic component arrangement information on the upper surface of the wiring board is, for example, pad information arranged for each electronic component mounted on the upper surface of the wiring board, and the pad is connected to the position (coordinates) and shape (including dimensions) of the pad. Information on electrodes and terminals of electronic components. In the case of an electronic component having a lead (foot), a via into which the lead is inserted is necessary, and such a lead insertion via is also referred to as a pad for connection with the electronic component in this specification. And That is, the pad information on the upper surface of the wiring board includes information on such a pad (more precisely, a lead insertion via).

  The pad information on the lower surface of the wiring board is information on a position (which is a position on the lower surface of the wiring board, hereinafter referred to as a pogo pin position) where the tip of the pogo pin needs to be contacted, and includes specific information on the pogo pin. ing. The shapes of the pads to which the tips of the pogo pins are connected are all the same and are determined in advance, and are not included in the information for each pad, but are the shape information common to the pads.

  The connection information between the pads is net information indicating which tester interface unit on the upper surface of the wiring board and which other pad the pad on the lower surface of the wiring board (in other words, pogo pin) is connected to.

  For example, the wiring board of the probe card has a disk shape, and the position of each point is defined by an XY coordinate system with the center of the circle as the origin. The positions of the upper surface and the lower surface of the wiring board are expressed in the same XY coordinate system, although the positions in the thickness direction (Z coordinate) are different.

  As is clear from the above, before starting the operation of determining the via arrangement, it is necessary that at least the electronic component arrangement information on the upper surface of the wiring board, the pad information on the lower surface of the wiring board, and the connection information between the pads are determined.

  When the main controller 21 reads the board design CAD data 22A into the working memory, the main controller 21 extracts all pogo pin position information from the board design CAD data 22A to form a pogo pin position information file (not shown in FIG. 3) (step). S101).

  Further, the main control unit 21 extracts the arrangement information of all the electronic components and forms an electronic component arrangement information file (not shown in FIG. 3) on the work area (step S102), and then adds the extracted electronic component arrangement information to the extracted electronic component arrangement information. Based on this, a through-via prohibited area is extracted, and a through-via prohibited area information file (not shown in FIG. 3) is formed on the work area (step S103). For example, the shape of the applicable figure is determined in advance for each type of electronic component, the position where the applied figure for the electronic component contains all the pads of the electronic component is searched, and the area of the applied figure after the search is penetrated The via prohibited area.

  In FIG. 3, the pogo pin position information is extracted prior to the extraction of the electronic component arrangement information and the extraction of the through via prohibited area. However, the order of these operations is not limited, and the electronic component is not limited. The extraction of the placement information and the through via prohibited area may be performed prior to the extraction of the pogo pin position information.

  Thereafter, the main control unit 21 classifies, for example, a pogo pin that needs to be connected to an electronic component and a pogo pin that only needs to be connected to a tester interface unit based on the pogo pin position and connection information between pads (step). S104). First, the main control unit 21 performs the processes of steps S105 to S108 on the pogo pin group that needs to be connected to the electronic component, and then performs steps on the pogo pin group that only needs to be connected to the tester interface unit. The processing of S109 to S112 is performed.

  FIG. 3 shows a case where the above-described steps S100 to S104 are also included in a series of operations for determining the via placement of the wiring board. However, the processing up to step S104 is performed separately, and the wiring board via placement determining device 20 is executed. The data read in step S101 to S104 may already be included in the data read.

  For a pogo pin group that needs to be connected to an electronic component, the main control unit 21 first takes a clearance value from the designer (step S105). FIG. 3 shows the case where the clearance value is taken in from the designer, but it may be included in the original board design CAD data 22A, and the wiring board via arrangement determination program 21P or the system uses the fixed data. You may hold as.

  FIG. 4 is an explanatory diagram of the clearance. The clearance is a distance that must be secured at a minimum between the upper pad 50U of the relay through via 50 and the upper pad 51U of the other through via 51, and the pad 50U at the upper end of the relay through via 50. Between the pad 50D at the lower end of the relay through via 50 and the pad 54 in contact with the pogo pin 53. This is the distance that must be. In the case of this embodiment, the input clearance value is commonly used for the three types of clearances described above, but the three types of clearance values may be different.

  When the clearance value is taken in, the main control unit 21 extracts a location where the relay through via can be arranged (expressed in the XY coordinate system) and forms a relay through via arrangement location information file F1 (step S106). In this embodiment, through vias centered on lattice points (intersections at lattices where lines in the X and Y directions intersect) having a predetermined pitch in the X and Y directions (values may vary depending on the direction) The area of the top pad is a candidate for the location where the relay through via is arranged, and each candidate is within the area not included in the extracted through via prohibited area (area where via can be arranged), and the neighboring pad When the clearance value taken in between can be secured, it is determined that the through via can be arranged.

  Further, the main control unit 21 determines whether or not a through via can be arranged for each pogo pin that needs to be connected to an electronic component. Via arrangement information that a through via is applied when possible and a bottom side IVH is applied when it is impossible. A file F2 is formed and held (step S107). For example, when the position of the target pogo pin is within the area not included in the through via prohibited area and the clearance value captured between the adjacent pads can be secured, It is determined that the through via is applied to the pogo pin, and in other cases, it is determined that the bottom IVH is applied to the target pogo pin.

  The processing order of steps S106 and S107 described above is not limited to the order shown in FIG. 3, and may be reversed.

  Thereafter, the main control unit 21 determines a relay through via (position) to be applied to each pogo pin to which the bottom IVH is applied (step S108).

  FIG. 5 is a flowchart showing details of the relay through via determination process (step S108) corresponding to each pogo pin to which the bottom side IVH is applied.

  The main control unit 21 repeats the processing loop LP1 including steps S200 and S201 until there is no unprocessed pogo pin described to apply the bottom IVH to the via arrangement information file F2.

  When the main control unit 21 sets a certain unprocessed pogo pin as a processing target (step S200), the main through-going via placement location information file F1 described in the relay penetration via placement location information file F1 The possible placement location where the route length of the route is shortest is searched, and the pogo pin to be processed is associated with the found placement possible location and the shortest route length and described in the temporary placement information file F3 of the relay through via (step S201). ). FIG. 6 is an explanatory diagram showing a configuration example of the provisional placement information file F3 of the relay through via. The relay through via temporary arrangement information file F3 has a table structure, and one line (one record; hereinafter referred to as a temporary arrangement record) includes pogo pin identification information (ID) and relay through via temporary arrangement information ( The searched placeable location) and the shortest path length (may further include other information). Here, the path length may be calculated as a linear distance between the pogo pin position in the XY coordinate system and the center position described in the XY coordinate system of the placeable positions, and may be two points in the X direction. It may be calculated as the sum of the absolute value of the difference and the absolute value of the difference in the Y direction. It may be calculated by a calculation method other than this.

  When the provisional placement information of the relay through via is obtained for all the pogo pins to which the bottom side IVH is applied, the main control unit 21 obtains the information (each temporary placement record) in the provisional placement information file F3 of the relay through via. Then, the shortest path length is rearranged from the longest one (step S202).

  Thereafter, the main control unit 21 repeats the processing loop LP2 including steps S203 to S207 until there is no unprocessed temporary arrangement record in the temporary arrangement information file F3 of the relay through vias rearranged.

  First, the main control unit 21 sets a temporary placement record having the longest shortest path length as a processing target from unprocessed temporary placement records at that time (step S203). Then, information described in the temporary placement record as the placement of the relay through via for the pogo pin related to the temporary placement record is obtained, and the information is added to the via placement information file F2 (step S204). From the placeable places in the placeable place information file F1, the same place as the relay through via placement place of the added temporary placement record is deleted (step S205).

  Here, in the process of step S203 described above, the temporary arrangement record to be processed may be left as it is, or may be deleted. In addition, in the process of adding relay through via information to the via arrangement information file F2 in step S204, in addition to the relay through via information, the bottom IVH and top IVH information paired with the relay through via are also combined. May be added.

  Thereafter, the main control unit 21 searches for and extracts a temporary placement record having the same temporary placement information as the temporary placement information (location where the relay through via can be placed) in the temporary placement record to be processed (step S206). When this happens, all of the extracted temporary placement records (pogo pins) are subjected to the same processing as in step S201 described above to update the temporary placement information, and then updated in the same manner as in step S202 described above. The temporary placement records are rearranged from the shorter shortest path length to the shorter one including the temporary placement records (step S207). Here, when the temporary placement information is updated, the information of the placeable place determined to be applied is deleted from the placeable places in the relay through via placeable place information file F1 by the process of step S205. The previous placeable location is not selected during the update process.

  With the processing shown in FIG. 5 as described above, the arrangement of relay through vias corresponding to each pogo pin to which the bottom side IVH is applied is determined. After this determination, the process shifts to a process for a pogo pin group that only needs to be connected to the tester interface unit.

  In this embodiment, vias corresponding to pogo pins that only need to be connected to the tester interface unit are based on the bottom IVH, and through vias are applied to some of the pogo pins. Note that the wiring arrangement determination process in the bottom-side laminated part or the top-side laminated part is executed after the processing of the wiring board via arrangement determining apparatus 20, but for the pogo pins determined to apply the bottom-side IVH, the bottom-side laminated part is used. It is often decided to connect to the tester interface part by wiring in the part, and for the pogo pin decided to apply the through via, it is often decided to connect to the tester interface part by wiring in the top side laminated part. I will.

  In the process for the pogo pin group that only needs to be connected to the tester interface unit, first, the main control unit 21 takes in the number of wires that can be accommodated in the bottom-side stacked unit input by the designer (step S109 in FIG. 3). Note that FIG. 3 shows a case where the number of wires that can be accommodated in the bottom side laminated portion is taken from the designer, but it may be included in the original board design CAD data 22A, and the wiring board via arrangement The determination program 21P or the system may hold it as fixed data.

  The number of wires that can be accommodated in step S109 is the number of wires that can be accommodated for a pogo pin group that only needs to be connected to the tester interface unit. However, the number of wires that can be accommodated in consideration of the relay through via and the bottom IVH paired with the relay through via is taken in, and twice the number of relay through vias described in the via arrangement information file F2 is taken in. By subtracting from the number of wires that can be accommodated, the number of wires that can be accommodated for a pogo pin group that only needs to be connected to the tester interface unit may be calculated.

  Thereafter, the main control unit 21 stores the position information of the pogo pins that only need to be connected to the tester interface unit in the bottom IVH temporary placement information file F4 as the bottom IVH temporary placement information (step S110). Note that the bottom IVH temporary arrangement information file F4 may be formed when the pogo pins are classified in step S104 described above.

  Next, the main control unit 21 extracts the locations where the through vias can be arranged from the temporarily arranged bottom side IVH so as to satisfy the number of wires that can be accommodated in the entire bottom side laminated unit, and the extracted bottom side The temporary arrangement information of IVH is replaced with the through via arrangement information and described in the via arrangement information file F2 (step S111).

  FIG. 7 is a flowchart showing details of the process (step S111) for replacing some of the temporary arrangement information on the bottom side IVH with through via arrangement information.

  In the process of replacing the bottom side IVH temporary placement information with the through via placement information, the main control unit 21 first sets the number of the bottom side IVH temporary placement information described in the bottom side IVH temporary placement information file F4 to the current bottom side. It is calculated as the number of wirings in the stacked portion (step S300).

  Thereafter, the main control unit 21 determines whether or not the number of wires in the current bottom-side stacked unit exceeds the number of wires that can be accommodated (step S301).

  If the number of wires in the current bottom side stacked portion exceeds the number of wires that can be accommodated, the main control unit 21 extracts temporary placement information for one bottom IVH from the bottom IVH temporary placement information file F4 (step S302), it is determined whether or not the temporary arrangement information (position) of the bottom IVH can be replaced with the through via (step S303). In the extraction of the temporary IVH temporary arrangement information from the bottom IVH temporary arrangement information file F4 in step S302, the information is deleted from the bottom IVH temporary arrangement information file F4. Here, the provisional arrangement information of the bottom IVH may be extracted according to the description order, or may be extracted in the order not according to the description order using random numbers. In the determination of whether or not the through via can be replaced in step S303, the position of the upper surface of the wiring board obtained by extending the temporarily arranged bottom side IVH is within a region not included in the through via prohibited region, It is determined whether or not a clearance value can be secured between.

  If it cannot be replaced with the through via, the main control unit 21 adds the via information related to the pogo pin to the via arrangement information file F2 by adding the temporary arrangement information of the bottom IVH to be processed as it is (step S21). S304), the process returns to the above-described step S302. On the other hand, if the via can be replaced with the through via, the main control unit 21 performs via information of the pogo pin corresponding to the temporary arrangement information of the bottom IVH to be processed, and the information of the through via is stored in the via arrangement information file F2. At the same time, the number of wires in the current bottom-side stack is reduced by 1 (step S305), and the process returns to step S301 described above.

  By repeatedly performing the replacement with the through via in step S305, the number of wires in the current bottom side stacked portion gradually decreases, and eventually becomes equal to the number of wires that can be accommodated.

  When the main control unit 21 obtains a result that the number of wires in the current bottom-side stacked unit does not exceed the number of wires that can be accommodated in the determination in step S301 described above, the main control unit 21 reads one from the bottom-side IVH temporary arrangement information file F4. After the bottom IVH temporary placement information is extracted (step S306), the via information related to the pogo pin is added to the via placement information file F2 without changing the bottom IVH temporary placement information to be processed (step S307). ), It is determined whether or not the bottom IVH temporary arrangement information file F4 is empty (step S308). If the bottom IVH temporary arrangement information file F4 is not empty, the process returns to the above-described step S306, and if the bottom IVH temporary arrangement information file F4 is empty, the series of processes shown in FIG.

  When the process of replacing some of the temporary IVH placement information on the bottom side IVH with the through via placement information (step S111) ends, the main control unit 21 inputs the information described in the via placement information file F2 using the board design CAD. The data is output to the external storage unit 22 in a possible format.

(A-3) Effect of Embodiment According to the above embodiment, the following effect can be obtained.

  Through-vias and relay-through vias for pogo pins with connections to electronic components are determined in consideration of the electronic component area and clearance without providing a block-unit allowable area. As a result, the wiring capacity can be improved.

  In addition, the location of the through via via is determined so that the shortest wiring route to the pogo pin is provided, so the wiring route length is shortened and electrical characteristics such as signals passing through the wiring route are deteriorated in advance. Can be prevented.

  For the pogo pin group that has connection only with the tester interface part, it is possible to wire in the top side laminated part by applying through vias instead of the bottom side IVH for the number exceeding the wiring capacity of the bottom side laminated part. As a result, it is possible to avoid increasing the number of layers in the bottom-side laminated portion.

  According to the above embodiment, since the main control unit can execute the arrangement of almost all vias, it is possible to reduce the manufacturing cost of the wiring board and reduce the number of manufacturing steps. it can.

(B) Other Embodiments In the above embodiment, the probe card is applied to the present invention. However, the technical idea of the present invention can be applied to other wiring boards.

  DESCRIPTION OF SYMBOLS 20 ... Wiring board via arrangement | positioning determination apparatus, 21 ... Main control part, 21P ... Wiring board via arrangement | positioning determination program, 22 ... External storage part, 23 ... Display part, 24 ... Input part, 30 ... Design data reading part, 31 ... Pogo pin Position extraction unit, 32 ... Electronic component arrangement information extraction unit, 33 ... Penetration via forbidden area extraction unit, 34 ... Pogo pin classification unit, 35 ... Clear input reception unit, 36 ... Place extraction portion for relay penetration via, 37 ... Penetration via Arrangement determination unit, 38 ... Relay through via arrangement unit, 39 ... Bottom side stacking part wiring capacity input receiving unit, 40 ... Bottom IVH temporary arrangement unit, 41 ... Arrangement via information replacement unit, 42 ... Via arrangement information output Department.

Claims (4)

A plurality of electronic components are mounted and an upper surface having a plurality of interface portions to the outside and a first probe that requires connection to any one of the interface portions via any one of the electronic components without passing through the electronic components. A lower surface connected to the second probe that needs to be connected to the interface portion, and a via provided in the wiring board to which the upper surface side laminated portion and the lower surface side laminated portion are coupled via the coupling layer In the wiring board via arrangement determining apparatus for determining the arrangement,
Via arrangement information storage means for storing information of vias whose arrangement has been determined;
Based on the position information of the electronic component, through-via-unavailable area extracting means for extracting an area where the through-via cannot be arranged;
Among a plurality of candidate locations centered on each lattice point located at predetermined vertical and horizontal pitches, a region where a through via cannot be disposed, and a clearance that must be secured at least between the pads on the upper surface and between the pads on the lower surface Based on, through via placement possible location extraction means for extracting the location where the through via can be placed, and
A through-via placement availability determining means for determining whether a through-via can be placed above a point to which the first probe is connected based on a region where the through-via cannot be placed and a clearance;
Relay through via placement determining means for determining a location to provide a relay through via from locations where the through via can be placed so as to shorten the wiring path length when the through via cannot be placed,
When the through via can be arranged, information on the through via that can be arranged in the via arrangement information storage unit is described, and when the through via cannot be arranged, the relay through via determined by the via arrangement information storage unit is described. A wiring board via arrangement determining device comprising: via information writing means for describing information. Wiring accommodation number acquisition means for acquiring the number of wirings connected to the second probe that can be accommodated by the lower surface side laminated portion;
The number of the second probes penetrates the lower surface side IVH of the second probe related to the region other than the region where the through vias cannot be arranged by a number more than the number of wirings that can be accommodated by the lower surface side stacked portion. 2. The wiring board via arrangement determining apparatus according to claim 1, further comprising: a lower surface side IVH replacing unit which describes the information in place of the via in the via arrangement information storage unit. A plurality of electronic components are mounted and an upper surface having a plurality of interface portions to the outside and a first probe that requires connection to any one of the interface portions via any one of the electronic components without passing through the electronic components. A lower surface connected to the second probe that needs to be connected to the interface portion, and a via provided in the wiring board to which the upper surface side laminated portion and the lower surface side laminated portion are coupled via the coupling layer In the wiring board via arrangement determination method for determining the arrangement,
The via arrangement information storage means stores information on vias whose arrangement has been determined.
The through-via impossible area extracting means extracts an area where the through-via cannot be arranged based on the position information of the electronic component,
The through-via-arrangable location extracting means includes a region where a through-via cannot be arranged, a space between pads on the upper surface, and a pad on the lower surface, out of a plurality of location candidates centered on each lattice point located at predetermined vertical and horizontal pitches. Based on the clearance that must be secured at a minimum, extract the location where the through via can be placed,
The through via arrangement availability determination means determines whether or not the through via can be arranged above the point to which the first probe is connected based on the area where the through via cannot be arranged and the clearance,
The relay through via arrangement determining means determines the location where the relay through via is provided from the locations where the through via can be arranged so that the wiring path length is shortened when the through via cannot be arranged,
Via information writing means describes through via information that can be arranged in the via arrangement information storage means when the through via can be arranged, and in the via arrangement information storage means when the through via cannot be arranged. A wiring board via placement determination method characterized by describing information on the determined relay through via. A plurality of electronic components are mounted and an upper surface having a plurality of interface portions to the outside and a first probe that requires connection to any one of the interface portions via any one of the electronic components without passing through the electronic components. A lower surface connected to the second probe that needs to be connected to the interface portion, and a via provided in the wiring board to which the upper surface side laminated portion and the lower surface side laminated portion are coupled via the coupling layer A computer installed in the wiring board via placement determination device that determines the placement,
Via arrangement information storage means for storing information of vias whose arrangement has been determined;
Based on the position information of the electronic component, through-via-unavailable area extracting means for extracting an area where the through-via cannot be arranged;
Among a plurality of candidate locations centered on each lattice point located at predetermined vertical and horizontal pitches, a region where a through via cannot be disposed, and a clearance that must be secured at least between the pads on the upper surface and between the pads on the lower surface Based on, through via placement possible location extraction means for extracting the location where the through via can be placed, and
A through-via placement availability determining means for determining whether a through-via can be placed above a point to which the first probe is connected based on a region where the through-via cannot be placed and a clearance;
Relay through via placement determining means for determining a location to provide a relay through via from locations where the through via can be placed so as to shorten the wiring path length when the through via cannot be placed,
When the through via can be arranged, information on the through via that can be arranged in the via arrangement information storage unit is described, and when the through via cannot be arranged, the relay through via determined by the via arrangement information storage unit is described. A wiring board via arrangement determination program which functions as via information writing means for describing information.

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