JP2010192768A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reflect a result of inspection of damage due to cleaning treatment on manufacture of a semiconductor device by providing a TEG (Test Element Group) having an easy-to-collapse pattern for a semiconductor device having a TEG for inspecting damage due to a cleaning treatment. <P>SOLUTION: A collapse pattern 6 patterned in a channel shape on a principal surface of a silicon substrate 1 and comprising a thermal oxide film 2 and a conductive film 3 is formed as the TEG for inspection of damage due to cleaning treatment to check damage to a wafer having been subjected to the cleaning treatment using an ultrasonic wave and a solution by observing a collapse state of the collapse pattern 6 through an SEM. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique that is effective when applied to the manufacture of a semiconductor device having a TEG including a pattern that tends to collapse.

  TEG (Test Element Group) is an evaluation element for finding design and manufacturing problems that occur in semiconductor devices, such as whether the characteristics of materials used in semiconductor devices affect the design of semiconductor devices. Are known. The TEG is also called a test structure, and the shape thereof is various such as a wafer shape and a chip shape.

  When investigating the causes of problems that occur at various stages, such as process development, design, and manufacturing of semiconductor devices, a part of the elements and structures that make up semiconductor devices are cut out, and dedicated circuits suitable for investigating the causes By using the TEG constructed and manufactured, the cause can be investigated early.

  In recent years, with the development of high-density mounting technology, there is a high possibility that fine elements will be damaged by the cleaning process, and the demand for TEG for inspecting the damage to the semiconductor device by the cleaning process is increasing.

  Regarding the collapse of the TEG pattern, a semiconductor device manufacturing technique for the purpose of preventing the collapse is known (for example, Patent Document 1 to Patent Document 5).

JP 2006-310755 A JP-A-11-345944 Japanese Patent Laid-Open No. 11-330399 Japanese Patent Laid-Open No. 11-154634 JP 05-326392 A

  Ultrasonic (Megasonic) cleaning treatment that can efficiently remove microparticles using the physical force of waves while the object to be cleaned is immersed in pure water or an aqueous solution, or cleaning liquid is used. In the water washing treatment, there is a demand for TEG having a pattern that tends to collapse for the purpose of damage evaluation. Conventionally, such a TEG has not existed because there was no need for a TEG having a pattern that easily collapses.

  An object of the present invention is to provide a technique for easily manufacturing a TEG having a pattern that easily collapses in a TEG for damage evaluation by wafer cleaning processing by applying a semiconductor pre-process.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A method of manufacturing a semiconductor device according to an invention of the present application is as follows:
In a method for manufacturing a semiconductor device, comprising: a step of forming a TEG for damage inspection by cleaning on a first semiconductor substrate; and a step of forming a pattern having the same structure as the TEG on a second semiconductor substrate.
(A) preparing the first semiconductor substrate;
(B) after the step (a), forming a film on the main surface of the first semiconductor substrate;
(C) after the step (b), patterning the film to form the TEG;
(D) After the step (c), a step of cleaning the first semiconductor substrate;
(E) after the step (d), evaluating whether the TEG has collapsed in the cleaning treatment step;
(F) After the step (e), forming a pattern having the same structure as the TEG on the second semiconductor substrate;
(G) After the step (f), the step of cleaning the second semiconductor substrate based on the evaluation of the step (e);
It is characterized by having.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  A TEG capable of easily producing a pattern that easily collapses on a semiconductor substrate in a semiconductor pre-process, and capable of inspecting the damage to the semiconductor substrate in a wafer cleaning process, Can be reflected in the production of

1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. It is principal part sectional drawing along the AA of FIG. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; It is a top view which shows the Example of the semiconductor device of this invention. It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, in the embodiment, etc., when “consisting of A” or “consisting of A” is used to exclude other elements, unless specifically stated that only those elements are stated. It goes without saying that it is not.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In addition, when referring to materials, etc., unless specified otherwise, or in principle or not in principle, the specified material is the main material, and includes secondary elements, additives It does not exclude additional elements. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (for example, SiGe) having silicon as a main element.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  In the drawings used in the following embodiments, even a plan view may be partially hatched to make the drawings easy to see.

(Embodiment 1)
This embodiment is applied to a method for manufacturing a semiconductor device, and FIGS. 1 and 2 show the structure of the semiconductor device in the present embodiment. FIG. 1 is a top plan view of a semiconductor device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along line AA in FIG.

  In FIG. 2, a patterned thermal oxide film 2 is formed on a main surface of a silicon substrate (hereinafter simply referred to as a substrate) 1, and a conductive film 3 patterned wider than the thermal oxide film 2 is formed on the thermal oxide film. As shown in FIG. 1, a thermal oxide film (not shown) and a conductive film patterned in a U-shape are arranged in the front, rear, left and right directions as shown in FIG.

  According to the present embodiment, for example, after performing a cleaning process with pure water, it is confirmed by using a scanning electron microscope (SEM) whether the collapse pattern 6 patterned in a U-shape is collapsed. Then, it is possible to examine the damage caused by the cleaning process on the wafer.

  Here, the collapse means that a part of the collapse pattern 6 is missing or the entire collapse pattern 6 is peeled off from the substrate 1 by the power of water such as an aqueous solution.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 3, a thermal oxide film 2 is formed on the substrate 1.

  Next, as shown in FIG. 4, a conductive film 3 made of polysilicon, a CVD oxide film 4, and a resist 5 are sequentially formed on the thermal oxide film 2, and the resist 5 is patterned.

  Next, as shown in FIG. 5, the CVD oxide film 4 is partially removed by dry etching using the resist 5 as a mask.

  Next, as shown in FIG. 6, after removing the resist 5 by ashing, the conductive film 3 and the thermal oxide film 2 are processed by dry etching using the CVD oxide film 4 as a mask.

  Next, as shown in FIG. 7, after the CVD oxide film 4 is removed by wet etching, the thermal oxide film 2 is partially removed by wet etching, thereby completing the collapse pattern 6. Here, the width L2 of the thermal oxide film 2 can be controlled within the range of the width L3 of the conductive film 3 by controlling the time of the wet etching process. By narrowing the width L2 of the thermal oxide film 2, it is possible to make the pattern more easily collapsed. Conversely, by widening the width L2, it is possible to make the pattern difficult to collapse.

  Further, by changing the size of the collapse pattern 6, the thickness H2 of the thermal oxide film 2, and the thickness H3 of the conductive film 3, the ease of collapse of the collapse pattern 6 can be controlled, and the required TEG It is possible to adjust the durability of the collapse pattern 6 according to the above.

  Furthermore, since the collapse pattern of the present embodiment is composed of an insulating film and a conductive film in the same manner as a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) structure, it can be formed in the same process as the MOSFET in the semiconductor pre-process, making it easy. Can be produced with excellent processing accuracy. For this reason, it is possible to apply to the damage evaluation by an extremely minute cleaning process without adding a new device or process.

  The TEG on which the collapse pattern 6 is completed is then cleaned in a cleaning apparatus, and the damage situation of the semiconductor wafer is evaluated by confirming the collapse status of the collapse pattern using the SEM.

  Next, a MOSFET having the same structure as the collapse pattern 6 is formed on another semiconductor substrate based on the information obtained by the damage evaluation. When the collapse pattern 6 has collapsed, the element is formed by cleaning under different conditions of the cleaning process in the step of forming the MOSFET.

  In addition, as shown in FIG. 1, the collapse pattern 6 is a U-shaped pattern, and a pattern that is more easily collapsed can be produced by arranging the collapse pattern 6 in the respective directions of front, rear, left, and right. The shape is not limited to a U-shape, and may be a T-shape, an L-shape, a linear shape, or the like as shown in FIGS. 8A, 8B, and 8C.

  Further, as shown in FIG. 7, the collapse pattern 6 has a width L3 of 50 nm to 150 nm, a thickness H3 of 50 nm to 500 nm, and a thickness H2 of the thermal oxide film 2 of 5 nm to 50 nm. Form with. The width L2 of the thermal oxide film 2 is formed to be equal to or smaller than the width L3 of the conductive film 3.

  Furthermore, when actually manufacturing the TEG having the collapse pattern 6 of the present embodiment, the structure shown in FIG. 1 or FIG. 8 (a), (b) or (c) is usually divided into one section. As a structure of the above, a TEG that is arranged on the entire surface of one wafer is used as a TEG.

(Embodiment 2)
As described in the first embodiment, the TEG in the present invention is mainly manufactured by forming only the collapse pattern on the entire upper surface of the wafer, but it can be manufactured in the same process as the conventional MOSFET. Therefore, it can be used as a TEG in a state where MOSFET elements and collapse patterns are mixed on the wafer. The present embodiment is applied to a method for manufacturing a TEG in which MOSFET elements and collapse patterns are mixed, and the manufacturing process will be described with reference to FIGS.

  First, as shown in FIG. 9, a thermal oxide film 2 and a conductive film 3 made of polysilicon are formed on the main surface of the substrate 1.

  Next, as shown in FIG. 10, with the resist 13 formed and patterned on the conductive film 3 as a mask, the conductive film 3 and the thermal oxide film 2 are partially processed by dry etching to form a gate made of the thermal oxide film 2. A gate electrode 8 composed of the insulating film 7 and the conductive film 3 is formed.

  Next, as shown in FIG. 11, after removing the resist 13 by ashing, a CVD oxide film 4 is deposited on the main surface of the substrate 1.

  Next, as shown in FIG. 12, after a patterned resist 5 is formed on a part of the CVD oxide film 4, the lower part of the resist 5, the side surfaces of the conductive film 3 and the thermal oxide film 2 are formed by dry etching. Then, the CVD oxide film 4 in the region other than the side surfaces of the gate electrode 8 and the gate insulating film 7 is removed. Thus, sidewalls 9 and 10 made of the CVD oxide film 4 are formed on the side surfaces of the thermal oxide film 2 and the conductive film 3 and the side surfaces of the gate insulating film 7 and the gate electrode 8, respectively. 8. A dummy MOSFET 11 including the sidewall 10 is formed.

  Note that the TEG manufactured in this embodiment is for the purpose of observing damage due to the cleaning process, and therefore the dummy MOSFET 11 does not include a source / drain region and does not have an electrical function as a MOSFET.

  Next, as shown in FIG. 13, after removing the resist 5 by ashing, a resist 12 patterned so as to cover the dummy MOSFET 11 is formed on the main surface of the substrate 1.

  Next, as shown in FIG. 14, after the conductive film 3 and the thermal oxide film 2 are processed by dry etching using the CVD oxide film 4 as a mask, the CVD oxide film 4 and the sidewalls 9 are removed by wet etching. .

  Next, as shown in FIG. 15, a part of the thermal oxide film 2 is removed by wet etching, thereby forming a collapse pattern 6 composed of the thermal oxide film 2 and the conductive film 3. Thereafter, the resist 12 is removed by ashing to complete the TEG of the present embodiment.

  Here, as in the first embodiment, by forming the collapse pattern 6 that is easy to collapse, it is possible to observe the damage received on the wafer by the cleaning process using an ultrasonic wave or an aqueous solution. As can be seen from the fact that the collapse pattern 6 can be formed in parallel with the dummy MOSFET 11 in the semiconductor pre-process, the collapse pattern 6 has the same structure as the MOS structure. Can be manufactured.

  The TEG on which the collapse pattern 6 is completed is then cleaned in a cleaning apparatus, and the damage situation of the semiconductor wafer is evaluated by confirming the collapse status of the collapse pattern using the SEM.

  Next, a MOSFET having a pattern having the same structure as the collapse pattern 6 is formed on another semiconductor substrate based on the information obtained by the damage evaluation.

  It should be noted that the pattern shape of the collapse pattern 6 can be various designs depending on the required damage evaluation such as a U-shape or T-shape, as shown in FIGS.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The method for manufacturing a semiconductor device according to the present invention is widely used for manufacturing a semiconductor device having a TEG structure used for damage evaluation by a cleaning process or an ultrasonic device.

1 Substrate (silicon substrate)
2 Thermal oxide film 3 Conductive film 4 CVD oxide film 5 Resist 6 Collapse pattern 7 Gate insulating film 8 Gate electrode 9 Side wall 10 Side wall 11 Dummy MOSFET
12 resist 13 resist

Claims (4)

In a method for manufacturing a semiconductor device, comprising: a step of forming a TEG for damage inspection by cleaning on a first semiconductor substrate; and a step of forming a pattern having the same structure as the TEG on a second semiconductor substrate.
(A) preparing the first semiconductor substrate;
(B) after the step (a), forming a film on the main surface of the first semiconductor substrate;
(C) after the step (b), patterning the film to form the TEG;
(D) After the step (c), a step of cleaning the first semiconductor substrate;
(E) after the step (d), evaluating whether the TEG has collapsed in the cleaning treatment step;
(F) After the step (e), forming a pattern having the same structure as the TEG on the second semiconductor substrate;
(G) After the step (f), the step of cleaning the second semiconductor substrate based on the evaluation of the step (e);
A method for manufacturing a semiconductor device, comprising:   In the step (b), the TEG is formed by sequentially laminating an insulating film and a conductive film on the main surface of the first semiconductor substrate, and then patterning by dry etching and wet etching, and the insulating film is wider than the conductive film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is narrowly formed and is easily collapsed during the cleaning process in the step (d).   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step (b), the film is patterned into a U-shape when viewed from above.   The method of manufacturing a semiconductor device according to claim 1, wherein the cleaning process is ultrasonic cleaning.

Images