JP2009164452A - Evaluation method of semiconductor device, and semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an evaluation method of a semiconductor device capable of accurately monitoring the variations in a local region and efficiently executing the cause analysis of product defect occurrence. <P>SOLUTION: Separately from a mask for a product to be used in the manufacturing line of the semiconductor device, a dedicated mask for evaluation for monitoring the manufacturing line is prepared (step S1). Then, on the manufacturing line of the semiconductor device, a plurality of evaluation elements (transistors or the like, for instance) are formed within at least one chip region of a wafer using the mask for the evaluation, and a wafer for the evaluation is formed (step S2). Then, electrical characteristics are measured for the plurality of evaluation elements formed on the wafer for the evaluation (step S3). Then, a physical parameter is analyzed for the plurality of evaluation elements formed on the wafer for the evaluation (step S4). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a high-density circuit element (for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), ROM (Read Only Memory), flash memory, SoC (System-on-Chip). The present invention relates to a method for evaluating a semiconductor integrated circuit, a liquid crystal display panel, or a magnetic head. The present invention also relates to a semiconductor wafer used for such an evaluation method.

  When mass-producing high-density circuit elements by performing various processes such as film formation and photolithography processes on the wafer substrate, evaluation, analysis, countermeasures, etc. of circuit element characteristics are extremely effective in improving product yield. It becomes a method.

Japanese Patent Laying-Open No. 2003-197752 (FIG. 1) T. Mizuno et al., "Experimental Study of Threshold Voltage Fluctuation Due to Statistical Variation of Channel Dopant Number in MOSFET's", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 11, pp. 2216-2221, 1994

  In Patent Document 1, a large number of chips are provided on one semiconductor wafer at an arrangement pitch Lx in the X direction and an arrangement pitch Ly in the Y direction. In the effective chip region, Nx first chips are arranged along the chip X side. The characteristic monitor units are arranged at the pitch px, and the Ny second characteristic monitor units are arranged at the pitch py along the chip Y side, and Nx × px = Lx and Ny × py = Ly are established.

  However, since only about one transistor of the same size for evaluating characteristic variation can be arranged for each chip region, only a few tens of transistors can be evaluated over the entire wafer. For this reason, it is possible to evaluate wafer in-plane variations (in-plane distribution of characteristics due to processes), but random variations (for example, due to impurity discreteness, line edge roughness, local thickness distribution of gate oxide film) It is not possible to evaluate the characteristic variation of the transistors to be used.

  Further, in Non-Patent Document 1, it is possible to evaluate the characteristic variation due to the discrete distribution of impurities. However, the separation of other components, which physical parameter influences the characteristic variation, and which manufacturing process I can not give a guide on how to improve.

  With such a conventional technique, it is possible to analyze the in-plane distribution of the process. However, in an integrated circuit or a semiconductor memory in which transistors are arranged at a very high density in one chip such as an SRAM, individual transistors are affected. Therefore, it is impossible to analyze the variation in characteristics of the local region that causes the manufacturing yield to decrease.

  Also, in process generations where the wiring pattern spacing is 0.1 μm or more, variations in device characteristics affect device characteristics such as physical parameters (for example, transistor gate length, gate width, gate oxide film thickness, sidewall oxide film thickness, etc.) Therefore, the physical parameters to be solved according to the defect in the element characteristics were clear.

  However, as the process generation progresses, the device characteristic variation is affected by a plurality of physical parameters, so that countermeasures are becoming more complicated, and the conventional technology as described above can no longer cope with it.

  An object of the present invention is to provide a semiconductor device evaluation method capable of accurately monitoring variations in local regions and efficiently performing cause analysis of product defect occurrence.

  Another object of the present invention is to provide a semiconductor wafer suitable for such an evaluation method.

  According to one embodiment of the present invention, a dedicated evaluation mask for monitoring the production line is prepared separately from the product mask used in the semiconductor device production line. Next, in the semiconductor device manufacturing line, a plurality of evaluation elements (for example, transistors) are formed in at least one chip region of the wafer using the evaluation mask, thereby forming an evaluation wafer. Next, electrical characteristics of a plurality of evaluation elements formed on the evaluation wafer are measured. Next, physical parameters are analyzed for a plurality of evaluation elements formed on the evaluation wafer.

  In particular, by measuring the electrical characteristics of multiple evaluation elements and applying a general statistical analysis method, the distribution of characteristics in the wafer surface and the shot distribution (regulated for each area exposed at one time in the photolithography process) Distribution), systematic distribution (distribution with spatial regularity in the chip), and random distribution.

  Further, it is evaluated how the physical parameters of the evaluation element exhibiting abnormal characteristics vary with respect to the random variation in characteristics. For example, a sensitivity table indicating the sensitivity of the influence of variations in physical parameters unique to the semiconductor device manufacturing line on variations in electrical characteristics is created. By calculating this sensitivity table, the policy for improving and taking measures against the production line related to the physical parameters becomes clear.

  According to this embodiment, by using a mask for forming a plurality of evaluation elements arranged two-dimensionally, it is possible to accurately monitor the variation in the local region, and to efficiently perform the cause analysis of the product defect occurrence. it can. The product yield can be improved by feeding back the evaluation result thus obtained to the production line of the semiconductor device.

Embodiment 1 FIG.
FIG. 1 is an overall flowchart showing an example of a semiconductor device evaluation method according to the present invention. In step S0, the same wafer as a product semiconductor wafer (eg, Si, GaAs, etc.) is prepared. In step S1, an evaluation TEG (Test Element Group) mask set for forming a plurality of evaluation elements arranged two-dimensionally in one chip area is prepared.

  In step S2, a plurality of evaluation elements are formed in at least one chip region of the wafer using a TEG mask set on the product manufacturing line, and the evaluation wafer 100 is manufactured.

  In step S <b> 3, electrical characteristics are measured for a plurality of evaluation elements formed on the evaluation wafer 100. In step S4, physical parameters are analyzed for a plurality of evaluation elements formed on the evaluation wafer 100.

  FIG. 2A is a partial plan view showing an example of the evaluation wafer 100, and FIG. 2B is a circuit diagram showing an evaluation circuit arranged in one chip area CA shown in FIG. It is. The evaluation wafer 100 is provided with a plurality of chip areas CA, and a plurality of evaluation elements TE are arranged in at least one chip area CA, preferably in all the chip areas CA, using the TEG mask set in step S1. An evaluation element group TEG is formed.

  As shown in FIG. 2B, a plurality of evaluation elements TE are arranged in a matrix in one chip area CA, and a row decoder circuit DY and a column for selecting one of the plurality of evaluation elements TE are arranged. A decoder circuit DX is arranged.

  The evaluation element TE is selected from the group consisting of a transistor element, a capacitor element, a resistance element, and a logic circuit (for example, a ring oscillator in which an odd number of inverters are connected in a ring shape). Here, a case where a MOS (Metal Oxide Semiconductor) -FET (Field Effect Transistor) is used as the evaluation element TE will be described.

  As shown in FIG. 2A, a plurality of pads PD are arranged around the chip area CA, and each pad PD can contact a plurality of contact pins connected to an inspection apparatus such as a wafer tester. . An address signal for designating the evaluation element TE is supplied to the row decoder circuit DY and the column decoder circuit DX from the outside via the pad PD. Further, the electric signal from the evaluation element TE designated by the address signal can be taken out through the pad PD.

  FIG. 3 is a cross-sectional view showing a typical CMOS (Complementary-MOS) manufacturing process in the manufacturing line in Step S2. The manufacturing process described here is merely an example, and is optimized according to the target device process and manufacturing line.

  First, as shown in FIG. 3A, after an oxide film 101 is formed on a wafer W, a mask 102 is provided and a shallow groove element isolation region 103 for element isolation is formed by etching. Next, as shown in FIG. 3B, an STI (Shallow Trench Isolation) layer 104 is formed by embedding an oxide film serving as an isolation layer in the element isolation region 103.

  Next, as shown in FIG. 3C, a gate electrode 105 is formed using multilayer film formation, photolithography, and dry etching techniques. Next, as shown in FIG. 3D, after forming an extension for a shallow source / drain region and a halo for suppressing a short channel effect, a gate sidewall insulating film 106 is formed. To do.

  Next, as shown in FIG. 3E, after forming deep source / drain regions for forming electrodes, a metal silicide layer 107 for reducing resistance is formed. Next, as shown in FIGS. 3F to 3H, an interlayer insulating film 108, a tungsten contact 109, and a metal wiring 110 are formed in this order, thereby forming a three-layer metal wiring as shown in FIG. 110, 111, 112 are formed. Finally, a passivation film is formed, and a pad PD is disposed thereon, whereby the evaluation wafer 100 is completed.

  FIG. 4 is a configuration diagram showing the measurement system used in step S3. This measurement system includes a wafer tester 10 and a measuring instrument 11. The wafer tester 10 includes a plurality of contact pins for selecting any one of the plurality of chip areas CA arranged on the evaluation wafer 100 and making electrical contact with each pad PD of the selected chip area CA. The measuring instrument 11 supplies an address signal for designating a specific evaluation element TE to the row decoder circuit DY and the column decoder circuit DX via the pad PD, and supplies an electrical signal to the evaluation element TE via the pad PD. Or an electrical signal from the evaluation element TE is acquired.

  As shown in FIG. 2B, a plurality of evaluation elements TE are arranged in a matrix in one chip area CA. In step S3, the electrical characteristics of all the evaluation elements TE are measured. For example, when the evaluation element TE is a transistor, the electrical characteristics to be measured are typically drain current-gate voltage dependency.

  FIG. 5A is a graph showing typical drain current-gate voltage characteristics, and FIG. 5B is a graph showing an example of a cumulative frequency distribution of threshold voltage variations. After measuring the drain current-gate voltage characteristics of all the evaluation elements TE and determining the threshold voltage of each element TE according to a predetermined standard, the frequency distribution of threshold voltage variations is counted, and the cumulative frequency Convert to distribution graph.

  As a result, as shown in FIG. 5B, the threshold voltage of the transistor fluctuates in the range of 0.3 V to 0.5 V even within a narrow area of one chip area CA. It can be seen that the average value of the cumulative frequency distribution 50% indicates 0.4V.

  In this case, since the transistor characteristics are acquired in the same chip area CA, the influence of the dependence of the process on the wafer surface (for example, film thickness distribution) and the dependence of the photolithography shot (for example, gate length dependence) Etc.) is considered to be minimal. On the other hand, the analysis of the variation due to the influence of the process can be performed by examining the in-plane distribution of the threshold and the in-shot distribution and examining the strength of the correlation with the process parameter.

  The problem is a characteristic that fluctuates in one chip area CA. In order to investigate the cause, for example, as shown in FIG. Physical analysis is performed on a transistor having a value voltage of 0.5V and a transistor having an average value of 0.4V.

  FIG. 6A is a perspective view showing the structure of one transistor formed by the manufacturing process of FIG. 3, and FIG. 6B is an exploded perspective view with the gate electrode separated. In order to investigate the correlation with the electrical characteristics of the transistor, the physical parameters to be analyzed are, for example, the stress ST applied to the transistor element, the length GL and width GW of the gate electrode 105, the shape of the gate electrode 105, and the line edge roughness GR. The thickness GT of the gate oxide film 101, the state of the PN junction 130, the discrete distribution 131 of channel impurities, and the like.

  In order to examine the values of the physical parameters shown in FIG. 6, an analysis using a physical parameter consistent analysis method as shown in FIGS. 7 to 13 is performed. As shown in FIG. 7, the evaluation element TE located in the area MA where the electrical characteristics of the element are measured is extracted from the evaluation element group TEG arranged in the chip area CA of the evaluation wafer 100.

  Thereafter, the passivation film and the wiring layer are removed by mechanical polishing and chemical etching, so that the first wiring layer is removed as shown in FIG. In this state, the focused laser beam 20 is irradiated, and the stress ST is measured using microscopic Raman spectroscopy or confocal Raman spectroscopy.

  Next, the interlayer insulating film is removed by chemical etching so that the gate sidewall insulating film 106 is exposed as shown in FIG. Since there is a silicon nitride liner layer on the gate sidewall insulating film 106, only the interlayer insulating film is removed using a hydrofluoric acid-based etchant, and then the silicon nitride film in the liner layer is removed to obtain a gate. The sidewall insulating film 106 can be exposed. In this state, the dimension of the gate sidewall insulating film 106 is evaluated using an offline scanning electron microscope.

  Next, as shown in FIG. 10, the gate sidewall insulating film 106 is removed by chemical etching. In general, since the gate sidewall insulating film 106 is formed of a silicon oxide film or a stacked layer of a silicon oxide film and a silicon nitride film, it can be removed using a hydrofluoric acid-based and phosphoric acid-based etching solution. Silicide is also removed by the hydrofluoric acid-based etching solution, and thus disappears in the step of removing the gate sidewall insulating film 106. In this state, the length GL and the width GW and the line edge roughness GR of the gate electrode 105 are evaluated using a scanning electric microscope, and from the image (white band) obtained by scanning electric microscope observation, Evaluate the shape.

  Next, the gate electrode 105 is removed in a hydrazine aqueous solution, a potassium hydroxide aqueous solution, or a sodium hydroxide aqueous solution. Since these etching solutions have a very large etching ratio between silicon and silicon oxide film, only the silicon is etched and the silicon oxide film is not etched at all. In the state shown in FIG. 11, the capacitance analysis of the gate oxide film 101 is performed using a probe microscope to identify the film thickness GT.

  Next, as shown in FIG. 12, the gate oxide film 101 is removed using chemical etching, and the state of the PN junction 130 formed by extension / halo is evaluated using a probe microscope.

  Finally, as shown in FIG. 13, the focused ion beam 140 is irradiated to expose only the channel region 139 of the transistor, and the discrete impurity distribution 131 in the channel region is evaluated using an atom probe.

  By calculating the correlation between the physical parameters obtained by the analysis in this way and the variations in the measured electrical characteristics (for example, the threshold voltage of the transistor), the variations in the physical parameters unique to the semiconductor device production line are calculated. Then, a sensitivity table indicating the sensitivity of the influence on the variation of the electrical characteristics is created.

The correlation between the threshold voltage variation σVth of the n transistors belonging to the evaluation element group TEG and the physical parameter a _i can be expressed by the following equation.

  In this equation, the left side is characteristic variation, the right side first term is physical parameter variation, and the right side second term is sensitivity parameter. This sensitivity parameter indicates the sensitivity of the influence of variations in physical parameters on the production line on variations in electrical characteristics. In view of this, it is possible to reduce variations in the elements created on the production line by taking a process measure for a highly sensitive physical parameter. By implementing this measure, it is possible to improve the yield by taking measures against foreign matters and the like, and to improve the yield that has fallen due to distribution.

Embodiment 2. FIG.
Also in the present embodiment, steps S0 to S4 are performed in the same manner as in FIG.

  14A is a partial plan view showing another example of the evaluation wafer 100, and FIG. 14B shows an evaluation circuit arranged in one chip area CA shown in FIG. 14A. It is a circuit diagram. The evaluation wafer 100 is provided with a plurality of chip areas CA, and a plurality of evaluation elements TE are arranged in at least one chip area CA, preferably in all the chip areas CA, using the TEG mask set in step S1. An evaluation element group TEG is formed.

  As shown in FIG. 14B, a plurality of evaluation elements TE are arranged in a matrix in one chip area CA, and a row decoder circuit DY and a column for selecting one of the plurality of evaluation elements TE are arranged. A decoder circuit DX is arranged.

  In the present embodiment, a resistance element (for example, well resistance, diffusion layer resistance, via resistance, polysilicon resistance, silicide resistance, wiring resistance, etc.) is used as the evaluation element TE. In this case, the electrical characteristic measured in step S3 is a resistance value.

  Therefore, as in FIG. 5, the resistance values of all the evaluation elements TE are measured, the frequency distribution of the resistance value variation is counted, and converted into a cumulative frequency distribution graph. Then, the maximum value and the minimum value of the resistance value variation, the average value of the cumulative frequency distribution 50%, and the like are calculated.

  Next, in step S4, physical analysis is performed on an element having a large variation in resistance value. With respect to the target evaluation element group TEG, the appearance such as dimensions is observed or length measurement is performed. Measurement of the resistance region is not performed for a diffusion resistor that defines a resistance region by ion implantation. After removing the interlayer insulating film, the amount and distribution of impurities are directly measured using an atom probe or the like.

  FIG. 15 is a perspective view showing a state of physical analysis of the resistance element. An STI insulating film 211 is formed on the silicon substrate 210, and interlayer insulating films 212 and 213 are formed thereon. A wiring 214 formed as the evaluation element TE is disposed on the upper surface of the interlayer insulating film 213, and vias 215 are connected to both ends thereof.

  In the case of performing physical analysis, the size and shape of the wiring 214 are confirmed after removing the interlayer insulating film. Thereafter, the grain is observed using an evaluation technique such as planar TEM analysis. The correlation between the obtained physical parameter and the variation in the measured electrical characteristic (for example, the resistance value of the resistance element) is calculated, and a sensitivity table is created as in the first embodiment. As a result, focusing on the most sensitive physical parameter, it is possible to take measures on the production line so that the variation is reduced.

Embodiment 3 FIG.
Also in the present embodiment, steps S0 to S4 are performed in the same manner as in FIG.

  FIG. 16A is a partial plan view showing still another example of the evaluation wafer 100, and FIG. 16B shows an evaluation circuit arranged in one chip area CA shown in FIG. FIG. The evaluation wafer 100 is provided with a plurality of chip areas CA, and a plurality of evaluation elements TE are arranged in at least one chip area CA, preferably in all the chip areas CA, using the TEG mask set in step S1. An evaluation element group TEG is formed.

  As shown in FIG. 16B, a plurality of evaluation elements TE are arranged in a matrix in one chip area CA, and a row decoder circuit DY and a column for selecting one of the plurality of evaluation elements TE are arranged. A decoder circuit DX is arranged.

  In the present embodiment, a capacitor element (for example, a gate capacity, a total diffusion capacity, a capacitor capacity, etc.) is used as the evaluation element TE. In this case, the electrical characteristic measured in step S3 is a capacitance value.

  Therefore, as in FIG. 5, the capacitance values of all the evaluation elements TE are measured, the frequency distribution of the capacitance value variation is counted, and converted into a cumulative frequency distribution graph. Then, the maximum value, minimum value, and average value of the cumulative frequency distribution 50% are calculated.

  Next, in step S4, a physical analysis is performed on an element having a large variation in capacitance value. With respect to the target evaluation element group TEG, the appearance such as dimensions is observed or length measurement is performed. For example, the thickness distribution of the capacitive film after the upper electrode is removed is directly measured using a probe microscope.

  The correlation between the obtained physical parameter and the variation of the measured electrical characteristic (for example, the capacitance value of the capacitor element) is calculated, and a sensitivity table is created as in the first embodiment. As a result, focusing on the most sensitive physical parameter, it is possible to take measures on the production line so that the variation is reduced.

Embodiment 4 FIG.
The object of the present embodiment is to incorporate an evaluation element into a part of a product wafer, constantly monitor quality variations, and perform physical analysis of the element when an abnormality occurs.

  Also in this embodiment, the procedure of steps S0 to S4 is executed as in FIG. 1, but in step S1, instead of preparing a TEG mask set dedicated for evaluation, one product chip and a dicing line for the product chip A product mask set for forming a plurality of evaluation elements two-dimensionally arranged therein is prepared.

  In step S2, a plurality of evaluation elements are formed in the wafer dicing line using the product mask set in the product manufacturing line to manufacture a product wafer.

  In step S3, electrical characteristics are measured for a plurality of evaluation elements formed on the product wafer. In step S4, physical parameters are analyzed for a plurality of evaluation elements formed on the product wafer.

  FIG. 17 is a plan view showing an example of the product wafer 400. The product wafer 400 is provided with a plurality of product chip areas CA, and a dicing line DL along the XY direction is secured at the boundary between adjacent product chip areas CA.

  In the present embodiment, an evaluation element group TEG including a plurality of evaluation elements TE is incorporated in a part of the dicing line DL. In the evaluation element group TEG, as in FIG. 2B, a plurality of evaluation elements TE are arranged in a matrix within the range of the dicing line DL, and a row for selecting one of the plurality of evaluation elements TE. Decoder circuit DY and column decoder circuit DX are arranged.

  The evaluation element TE is selected from the group consisting of a transistor element, a capacitor element, a resistance element, and a logic circuit (for example, a ring oscillator in which an odd number of inverters are connected in a ring shape). Around the evaluation element group TEG, a plurality of pads PD for transmitting / receiving electrical signals to / from the outside are disposed within the range of the dicing line DL.

  The product wafer 400 thus obtained is used to measure the electrical characteristics of the evaluation element TE arranged in the dicing line DL, so that the quality variation is constantly monitored in parallel with the mass production of the product chip. Data can be acquired. Since the evaluation element group TEG is disposed on the dicing line DL, the evaluation element group TEG is automatically cut off when the chip is divided, and no trace remains on the product chip.

  When a characteristic abnormality occurs during the manufacture of a product chip, the cause analysis of the defect can be performed earlier by performing the measurement of the electrical characteristics of the evaluation element group TEG and the integrated physical analysis in association with each other.

  Furthermore, by forming a larger number of TEGs in the wafer surface than in the normal characteristic monitoring TEGs, it is possible to improve the accuracy of monitoring such as variations in the wafer surface.

  INDUSTRIAL APPLICABILITY The present invention is extremely useful industrially in that it can accurately monitor variations in local regions and can efficiently perform cause analysis of product defect occurrence.

It is a whole flowchart which shows an example of the evaluation method of the semiconductor device which concerns on this invention. FIG. 2A is a partial plan view showing an example of the evaluation wafer 100, and FIG. 2B is a circuit diagram showing an evaluation circuit arranged in one chip area CA shown in FIG. It is. It is sectional drawing which shows the manufacturing process of the typical CMOS in the manufacturing line of step S2. It is a block diagram which shows the measurement system used by step S3. FIG. 5A is a graph showing typical drain current-gate voltage characteristics, and FIG. 5B is a graph showing an example of a cumulative frequency distribution of threshold voltage variations. FIG. 6A is a perspective view showing the structure of one transistor formed by the manufacturing process of FIG. 3, and FIG. 6B is an exploded perspective view with the gate electrode separated. It is explanatory drawing which shows a mode that the evaluation element TE of the wafer for evaluation 100 is extracted. It is a fragmentary perspective view which shows the mode of stress measurement. It is a fragmentary perspective view which shows the mode of evaluation of the gate side wall insulating film. It is a fragmentary perspective view which shows the mode of evaluation of the gate electrode. 4 is a partial perspective view showing a state of evaluation of a gate oxide film 101. FIG. It is a fragmentary perspective view which shows the mode of evaluation of the state of PN junction. It is a fragmentary perspective view which shows the mode of evaluation of the discrete impurity distribution 131 of a channel area | region. 14A is a partial plan view showing another example of the evaluation wafer 100, and FIG. 14B shows an evaluation circuit arranged in one chip area CA shown in FIG. 14A. It is a circuit diagram. It is a perspective view which shows the mode of the physical analysis of a resistance element. FIG. 16A is a partial plan view showing still another example of the evaluation wafer 100, and FIG. 16B shows an evaluation circuit arranged in one chip area CA shown in FIG. FIG. 3 is a plan view showing an example of a product wafer 400. FIG.

Explanation of symbols

10 wafer tester, 11 measuring instrument, 100 wafer for evaluation,
101 gate oxide film, 105 gate electrode, 106 gate sidewall insulating film,
130 PN junction, 131 discrete impurity distribution in channel region,
400 product wafers,
CA chip area, DX column decoder circuit, DY row decoder circuit,
TE evaluation element, TEG evaluation element group, PD pad,
DL dicing line.

Claims (9)

Preparing an evaluation mask for forming a plurality of evaluation elements arranged two-dimensionally in one chip region;
Forming a plurality of evaluation elements in at least one chip region of the wafer using the evaluation mask in a semiconductor device production line; and forming an evaluation wafer;
Measuring electrical characteristics of a plurality of evaluation elements formed on the evaluation wafer;
Analyzing the physical parameters of a plurality of evaluation elements formed on the evaluation wafer.   2. The semiconductor device evaluation method according to claim 1, wherein the plurality of evaluation elements are selected from a group consisting of a transistor element, a capacitor element, a resistance element, and a logic circuit. The plurality of evaluation elements are transistor elements,
2. The method of evaluating a semiconductor device according to claim 1, wherein the electrical characteristic to be measured is a threshold voltage of a transistor element. The plurality of evaluation elements are transistor elements,
The physical parameters to be analyzed were selected from the group consisting of stress on the transistor element, gate length, gate width, gate shape, gate line edge roughness, gate oxide film thickness, PN junction state, and discrete distribution of channel impurities. The semiconductor device evaluation method according to claim 1, wherein the number is at least one.   A sensitivity table that calculates the correlation between the measured variation in electrical characteristics and the variation in analyzed physical parameters, and shows the sensitivity of the effects of variations in physical parameters unique to the semiconductor device production line on the variation in electrical characteristics The method for evaluating a semiconductor device according to claim 1, further comprising: The plurality of evaluation elements are arranged in a matrix in the chip region,
2. The semiconductor device evaluation method according to claim 1, wherein a row decoder circuit and a column decoder circuit for selecting one of a plurality of evaluation elements are provided in the chip region. Preparing a product mask for forming one product chip and a plurality of evaluation elements two-dimensionally arranged in a dicing line of the product chip;
Forming a plurality of evaluation elements in a wafer dicing line using the product mask in a production line of a semiconductor device, and producing a product wafer;
Measuring electrical characteristics of a plurality of evaluation elements formed on a product wafer;
Analyzing a physical parameter for a plurality of evaluation elements formed on a product wafer. A method for evaluating a semiconductor device, comprising:   A semiconductor wafer comprising a plurality of evaluation elements arranged two-dimensionally in at least one chip region.   A semiconductor wafer, wherein one product chip and a plurality of evaluation elements arranged two-dimensionally in a dicing line of the product chip are formed.