JP2006140276A - Semiconductor wafer and semiconductor device using the same and chip size package, and semiconductor wafer manufacturing method and semiconductor wafer testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer for which the cutting width and the positional deviation amount of a scribe region can be easily measured when cutting the semiconductor wafer by the scribe region to separate it into individual chips, to provide a semiconductor device using the semiconductor wafer and a chip size package, and also to provide a semiconductor wafer manufacturing method and a semiconductor wafer testing method. <P>SOLUTION: The semiconductor wafer has a pattern 26 which is formed near the peripheral edge of the front surface of a silicon substrate and on a scribe line 24 to measure the width and positional deviation amount of a cutting region at the time of cutting the semiconductor wafer by the scribe line 24. The pattern 26 is built up with a plurality of small rectangular patterns 26a which are formed into a chevron shape so as to cross the scribe line 24, and long patterns 26b and 26b which are so formed as to overlap seal rings 31 and 31 on both sides of the scribe line 24. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor wafer, a semiconductor element using the semiconductor wafer, a chip size package (CSP), and a method for manufacturing and inspecting a semiconductor wafer, and more particularly, to a semiconductor wafer using a cutting device such as a dicing blade. Can be easily measured with high accuracy without using a special measuring instrument. It is about the technology that can be done.

In recent years, as in notebook personal computers, digital camera-equipped mobile phones, etc., the progress of miniaturization, thinning, and weight reduction of electronic devices has been remarkable, replacing the conventional dual inline package (Dual Inline Package). Chip-sized semiconductor elements have been used.
As a chip-sized semiconductor element, for example, a CSP in which an integrated circuit is formed on the surface of a semiconductor substrate and a resin sealing layer is formed so as to cover the integrated circuit is proposed and put into practical use (for example, a patent) Reference 1).
In this CSP, a plurality of integrated circuits are formed vertically and horizontally on the surface of a semiconductor substrate to produce a semiconductor wafer having a grid-like region surrounding each integrated circuit as a scribe region, and this semiconductor wafer is formed using a dicing blade. It is manufactured by dicing (cutting) along the scribe region to form individual semiconductor chips.

FIG. 9 is a cross-sectional view showing a cross-sectional structure in the vicinity of a dicing line (cutting region) after dicing of a semiconductor wafer. In the figure, 1 is a silicon substrate, 2 is formed on the surface (one main surface) 1a of the silicon substrate 1. The field oxide films, 3a to 3c are first to third interlayer insulating films formed on the field oxide film 2, 4a to 4c are seal rings provided on the openings 2a of the field oxide film 2, and 5 is a first ring. A passivation film covering the three interlayer insulating film 3c and the seal ring 4c, 6 is a scribe line (scribe area), 7 is a chip area (semiconductor element area), and 8 is a dicing line (cut area).
In this dicing process, the width w of the dicing line 8 and the width W of the scribe line 6 are set so that the positional deviation amount s of the center axis Ax ′ of the dicing line 8 with respect to the center axis Ax of the scribe line 6 falls within the standard range. Is set. For example, when the width w of the dicing line 8 is 50 μm, the width W of the scribe line 6 is about 100 μm.

FIG. 10 is a plan view showing the semiconductor wafer after the dicing step, 11 is a semiconductor chip separated by the dicing line 8, and 12 is a solder ball provided in a matrix on the semiconductor chip 11, these solder balls. Reference numeral 12 is electrically connected to an integrated circuit (not shown) formed on the surface 1 a of the silicon substrate 1.
In the semiconductor chip 11 thus obtained, the dicing line 8 at the time of dicing may bite into the chip region 7 beyond a predetermined range due to misalignment or the like, and may damage the seal rings 4a to 4c. This damage makes it easy for moisture in the atmosphere to enter the semiconductor chip 11 and degrades reliability over the long term. Therefore, it is necessary to perform an inspection for that purpose.
Therefore, the following two types of inspection methods are used.

"Inspection method 1"
The distances t ₁ and t ₂ from the solder ball 12 to the end portions 13 and 14 of the semiconductor chip 11 are measured, and the distance d from the seal ring 4c to the dicing line 8 is calculated based on these distances t ₁ and t ₂ How to ask.
"Inspection method 2"
A method in which a predetermined number of semiconductor chips 11 are extracted for each product lot, the peripheral portion of the semiconductor chips 11 is broken, and the distance d from the seal ring 4c to the dicing line 8 is directly measured.
In these inspection methods, if the obtained distance d is within the standard value, it is determined that there is no risk of damage, and the product lot is regarded as a non-defective product. On the other hand, if the distance d is smaller than the standard value, it is determined that there is a risk of damage, and the product lot is regarded as a defective product.
Japanese Patent Laid-Open No. 9-252027

By the way, in the conventional inspection method 1, the distances t ₁ and t ₂ from the solder ball 12 to the end portions 13 and 14 of the semiconductor chip 11 are relatively long, and these distances t ₁ and t ₂ are low in pattern accuracy. Since the measurement is based on the position of the solder ball 12, the measurement accuracy of these distances t ₁ and t ₂ is low. Therefore, there problem that the accuracy is also lowered a distance d from the seal ring 4c obtained by calculation a measurement less accurate distance t _1, t ₂ based on up to the dicing line 8.
In addition, there is a problem in that a dedicated measuring device for measuring these distances t ₁ and t ₂ is required.

Further, in the conventional inspection method 2, since the distance d from the seal ring 4c to the dicing line 8 is directly measured, the measurement accuracy of the distance d is improved, but the inspection takes time and effort. It was.
Further, since this inspection is a destructive inspection, there is a problem that the semiconductor chip after the inspection becomes unusable.

  The present invention has been made in view of the above circumstances, and when a semiconductor wafer is cut and separated in a scribe region using a cutting device such as a dicing blade to form individual semiconductor chips, A semiconductor wafer capable of easily measuring the cutting width and its positional deviation amount with high accuracy without using a special measuring instrument, a semiconductor element using the semiconductor wafer, a chip size package, and a semiconductor wafer manufacturing method, An object of the present invention is to provide a method for inspecting a semiconductor wafer.

In order to solve the above-mentioned problems, the present invention provides the following semiconductor wafer, a semiconductor element and chip size package using the same, a semiconductor wafer manufacturing method, and a semiconductor wafer inspection method.
That is, the semiconductor wafer of the present invention is a semiconductor wafer in which a semiconductor element is formed in each of a plurality of semiconductor element formation regions partitioned by a scribe region on one main surface of a semiconductor substrate, The semiconductor substrate is formed with a pattern for measuring the width of the cutting region and the amount of displacement when the semiconductor substrate is cut at the scribe region.

In this semiconductor wafer, a pattern for measuring the width of the cutting region and the amount of displacement when the semiconductor substrate is cut in the scribe region is formed on one main surface of the semiconductor substrate. By observing the semiconductor substrate, it is possible to easily measure the width of the cut region and the amount of displacement when the semiconductor substrate is cut at the scribe region.
Since this pattern is directly formed on one main surface of the semiconductor substrate, it is possible to directly measure the width of the cutting region and the amount of displacement thereof based on this pattern, and the measurement accuracy thereof. Is expensive.

The pattern is formed of a line-symmetric figure.
With such a configuration, it is possible to directly and accurately measure the width of the cutting region and the amount of displacement when the cutting is performed in the scribe region.

The pattern is formed in the vicinity of a peripheral edge portion of the one main surface.
By adopting such a configuration, the vicinity of the peripheral portion of one main surface of the semiconductor wafer, which has been conventionally regarded as an ineffective area, is effectively used. In order to form a pattern, the integrated circuit formation area can be expanded, or the semiconductor There is no need to increase the diameter of the wafer.

The pattern is formed in the vicinity of a peripheral portion of the one main surface and on an extension of the scribe region.
By adopting such a configuration, it becomes possible to directly and accurately measure the width of the cutting region and the amount of displacement in the scribe region based on this pattern.

It is preferable to add identification information to the pattern.
The identification information preferably includes numerical information or character information.
With such a configuration, identification information including numerical information or character information can be quickly read from the pattern.

The semiconductor element of the present invention is a semiconductor element obtained from the semiconductor wafer of the present invention, wherein the semiconductor substrate is cut at the scribe region.
In this semiconductor element, the width of the cutting region and the amount of displacement when the semiconductor substrate is cut in the scribe region are directly measured with high accuracy, so that the width of the cutting region in the inspection process of the semiconductor element and its The measurement accuracy of the positional deviation amount is improved and the time required for the measurement is shortened.

A chip size package according to the present invention includes the semiconductor element according to the present invention.
With such a configuration, the semiconductor element used has no defect in the cut portion, and the electrical characteristics and reliability of the chip size package are improved.

  The method for producing a semiconductor wafer according to the present invention is a method for producing a semiconductor wafer, wherein a semiconductor element is formed in each of a plurality of semiconductor element forming regions partitioned by a scribe region on one principal surface of a semiconductor substrate, A pattern for measuring the width of the cutting region and the amount of displacement when the semiconductor substrate is cut at the scribe region is formed on the one main surface during or after the semiconductor element forming step of forming It has the pattern formation process to perform.

  In this method of manufacturing a semiconductor wafer, the width of the cutting region and its position when the semiconductor substrate is cut in the scribe region on the one main surface during or after the semiconductor device forming step for forming the semiconductor device. By having a pattern forming process for forming a pattern for measuring the amount of deviation, the semiconductor substrate is scribed on one main surface of the semiconductor substrate by slightly changing a part of the normal semiconductor wafer manufacturing process. A pattern for measuring the width of the cutting area and the amount of positional deviation when it is cut with is easily formed, and there is almost no delay in work time and increase in manufacturing cost due to this pattern formation.

The semiconductor element forming step includes a step of forming an external connection terminal electrically connected to the semiconductor element, and the pattern forming step is performed simultaneously with the step.
In this manufacturing method, by performing the pattern forming step simultaneously with the step of forming the external connection terminal, a pattern is formed on one main surface of the semiconductor wafer with almost no change in the normal manufacturing step. As a result, it is possible to easily measure the width of the cutting region and the amount of displacement when the semiconductor substrate is cut at the scribe region on a normal production line without increasing the cost. It becomes possible.

  According to the semiconductor wafer inspection method of the present invention, a semiconductor element is formed in each of a plurality of semiconductor element formation regions partitioned by a scribe region on one main surface of a semiconductor substrate, and the semiconductor substrate is scribed on the one main surface. A method for inspecting a semiconductor wafer by forming a pattern for measuring the width of a cutting area and the amount of displacement when the area is cut, and observing changes in the pattern before and after cutting in the scribe area. The quality of cutting is evaluated based on the change of the pattern.

  In this semiconductor wafer inspection method, the change in pattern before and after cutting in the scribe region of one main surface of the semiconductor substrate is observed, and the quality of cutting is evaluated based on the change in this pattern. The quality of cutting in the scribe region can be easily determined visually, and the workability in the manufacturing process can be improved and the manufacturing cost can be reduced easily.

According to the semiconductor wafer of the present invention, a pattern for measuring the width of the cutting region and the amount of positional deviation when the semiconductor substrate is cut in the scribe region is formed on one main surface of the semiconductor substrate. By visually observing the pattern, it is possible to easily measure the width of the cut region and the amount of displacement when the semiconductor substrate is cut at the scribe region. Therefore, it is possible to easily determine whether or not the semiconductor wafer is defective due to cutting, and it is possible to easily determine whether the semiconductor wafer is good or not in a short time.
Further, since this pattern is directly formed on one main surface of the semiconductor substrate, the width of the cutting region and the amount of displacement can be directly and accurately measured based on this pattern.

  According to the semiconductor device of the present invention, since the semiconductor substrate having the pattern for measuring the width of the cutting region and the amount of displacement thereof is cut at the scribe region, the cutting region of each semiconductor device is cut. And the amount of positional deviation can be easily and accurately measured visually. Therefore, it is possible to easily determine whether or not a defect due to cutting occurs in the semiconductor element, and it is possible to easily determine whether the semiconductor element is good or not in a short time.

According to the chip size package of the present invention, since the semiconductor element of the present invention is provided, it is possible to use a semiconductor element having no defects at the cut portion, and to improve the electrical characteristics and reliability of the chip size package. Can be made.
In addition, since a semiconductor element having no defects is used at the cut portion, the product yield can be improved and the cost of the product can be reduced.
As a result, it is possible to provide a chip size package that is excellent in electrical characteristics and reliability and is low in cost.

  According to the method for manufacturing a semiconductor wafer of the present invention, the width of the cutting region when the semiconductor substrate is cut in the scribe region on the one main surface during or after the semiconductor element forming step for forming a semiconductor element. And a pattern forming process for forming a pattern for measuring the amount of misalignment, the semiconductor substrate is formed on one main surface of the semiconductor substrate by slightly changing a part of the manufacturing process of a normal semiconductor wafer. It is possible to easily form a pattern for measuring the width of the cut region and the amount of displacement when the scribe region is cut, and there is almost no delay in work time and increase in manufacturing cost due to this pattern formation. .

  According to the semiconductor wafer inspection method of the present invention, the change in the pattern before and after cutting in the scribe region is observed, and the quality of the cutting is evaluated based on the change in the pattern. It is possible to easily determine whether or not cutting is good visually. Therefore, the quality of the cutting can be determined easily and promptly, and the workability in the manufacturing process can be improved and the manufacturing cost can be reduced.

Embodiments of a semiconductor wafer, a semiconductor element, a chip size package (CSP), a semiconductor wafer manufacturing method, and a semiconductor wafer inspection method according to the present invention will be described with reference to the drawings.
These embodiments are specifically described for better understanding of the gist of the invention, and do not limit the present invention unless otherwise specified.

“First Embodiment”
FIG. 1 is a plan view showing a silicon wafer (semiconductor wafer) according to a first embodiment of the present invention. In the figure, 21 is a silicon substrate (semiconductor substrate), and 22 is the vicinity of the peripheral edge of the silicon substrate 21 in the −Y direction. An orientation flat 23 is formed, 23 is a scribe line (scribe region) that divides the surface (one main surface) 21a of the silicon substrate 21 into a band-like region extending in the X direction, and 24 is a surface 21a of the silicon substrate 21 in the Y direction. A scribe line (scribe region) that divides into an elongated band-like region, 25 is a chip region (semiconductor element formation region) defined by scribe lines 23, 23, 24, and 24 orthogonal to each other, and 26 is a surface 21a of the silicon substrate 21. A pattern formed in the vicinity of the peripheral edge in the -Y direction and on the scribe line 24, 27 is a silicon substrate 21 periphery and the vicinity of the X direction of the surface 21a of a pattern formed on the scribe line 23.

  As shown in FIG. 2, the pattern 26 is for measuring the width w of the cutting region and the amount of displacement s when the silicon substrate 21 is cut by the scribe line 24 using a cutting device such as a dicing blade. Thus, a plurality of rectangular micropatterns 26a are formed in a plan view Λ shape so as to cross the scribe line 24, and seal rings 31, 31 provided on the chip regions 25, 25 on both sides of the scribe line 24, respectively. A strip-shaped long pattern 26b, 26b is formed so as to overlap, and the tips of these two rows of micropatterns 26a, 26a,... Overlap the center line Ax of the scribe line 24, and the micropattern 26a, 26a,... The other end of each row passes above the seal ring 31 and extends to the chip region 25.

  As shown in FIG. 3, the pattern 27 is obtained by rotating the pattern 26 by 90 °. The width 27 of the cutting region when the silicon substrate 21 is cut by the scribe line 23 using a cutting device such as a dicing blade and the pattern 27 This is for measuring the amount of displacement s. A plurality of rectangular micropatterns 27a are formed on the scribe line 23 in a Λ shape in plan view, and are provided in the chip regions 25, 25 on both sides of the scribe line 23, respectively. The strip-shaped long patterns 27b, 27b are formed so as to overlap the seal rings 31, 31 and the tips of these two rows of micro patterns 27a, 27a,... Overlap the center line Ax of the scribe line 23, And the other ends of the micropatterns 27a, 27a,... Pass through the seal ring 31 and extend to the chip region 25. Yes.

These patterns 26 and 27 are formed at predetermined positions on the surface 21 a of the silicon substrate 21 by a pattern forming process provided during or after the process of forming a semiconductor element such as an integrated circuit in the chip region 25.
More specifically, the patterns 26 and 27 are formed of a copper post made of copper metal that is electrically connected to a semiconductor element such as an integrated circuit formed in the chip region 25, and is formed on the copper post and at least the upper end portion. Are formed simultaneously with the step of forming either a solder bump exposing the solder bump or a solder electrode which is an external terminal of the semiconductor element.
Therefore, it is possible to form the patterns 26 and 27 only by changing the mask pattern and the like, and there is no need to separately provide a process for forming the patterns 26 and 27, so that there is no possibility of increasing the manufacturing cost.

Next, an inspection method for this silicon wafer will be described.
Prior to dicing (cutting) the silicon substrate 21, the arrangement of the minute patterns 26a, 26a,... Sandwiched between the long patterns 26b, 26b is a Λ shape that is symmetrical with respect to the central axis Ax. .
When the silicon substrate 21 is diced along the scribe line 24 using a cutting device such as a dicing blade, the central portion of the pattern 26 is deleted by the dicing line 32 and the minute patterns 26a and 26a are formed on both sides as shown in FIG. , ... will remain.

  For example, when the shapes of the minute patterns 26a, 26a,... Remaining on both sides are symmetric as shown in FIG. 4A, the distance from the side surface of the dicing line 32 to the seal rings 31, 31 is equal. Therefore, the center axis Ax ′ of the dicing line 32 substantially coincides with the center axis Ax of the scribe line 24.

  When the shapes of the minute patterns 26a, 26a,... Remaining on both sides are as shown in FIG. 4B, the distance from the side surface of the dicing line 32 to the seal rings 31, 31 is narrow on the right side. Since the left side is wide, the center axis Ax ′ of the dicing line 32 is shifted from the center axis Ax of the scribe line 24 by a positional shift amount s.

  When the shape of the minute patterns 26a, 26a,... Remaining on both sides is as shown in FIG. 4C, the distance from the side surface of the dicing line 32 to the seal rings 31, 31 is equal, but the dicing is performed. Since the distance from the side surface of the line 32 to the seal rings 31 and 31 is extremely narrow, the width w of the dicing line 32 is slightly narrower than the width W of the scribe line 24.

  In this way, the quality of the dicing is evaluated by observing the shapes of the minute patterns 26a, 26a,... Remaining on both sides of the dicing line 32. Can be easily discriminated visually. Therefore, the quality of dicing can be determined easily and promptly, and the workability in the manufacturing process can be improved and the manufacturing cost can be reduced.

Further, since the shapes of the minute patterns 26a, 26a,... Remaining on both sides of the dicing line 32 are directly observed, the width w of the dicing line 32 and its positional deviation amount s can be directly measured with high accuracy.
Regarding the pattern 27, the quality of the dicing line can be evaluated in the same manner as the pattern 26.

.. And 24, 24,... Can be separated into individual chips (regions) 25 on which integrated circuits and the like are formed. . Therefore, the chip size package (CSP) of this embodiment can be obtained using this chip 25.
Since this chip 25 has no defect in the dicing line 32, the CSP using this chip 25 also has improved electrical characteristics and reliability.

“Second Embodiment”
FIG. 5 is a plan view showing a pattern formed on a silicon wafer (semiconductor wafer) according to the second embodiment of the present invention. The pattern 41 of the present embodiment is different from the pattern 26 of the first embodiment described above. The point is that in the pattern 26 of the first embodiment, a plurality of rectangular micropatterns 26a are formed in a Λ shape in plan view, whereas in the pattern 41 of this embodiment, spot-like micropatterns 41a having a small diameter are used. Is formed in a Λ shape in plan view.

  Also in this silicon wafer inspection method, just like the silicon wafer inspection method of the first embodiment, by observing the shape of the minute patterns 41a, 41a,... Sandwiched between the long patterns 26b, 26b, The quality of dicing can be evaluated. Therefore, even if it is not a skilled person, the quality of the dicing in the scribe line 24 can be determined visually and easily, and the workability in the manufacturing process can be improved and the manufacturing cost can be reduced.

“Third Embodiment”
FIG. 6 is a plan view showing a pattern formed on a silicon wafer (semiconductor wafer) according to the third embodiment of the present invention. The pattern 51 of this embodiment is different from the pattern 26 of the first embodiment described above. The point is that in the pattern 26 of the first embodiment, a plurality of rectangular micropatterns 26a are formed in a Λ shape in plan view so as to cross the scribe line 24, whereas in the pattern 51 of this embodiment, the scribe line is formed. This is that a plurality of rectangular micropatterns 26 a are formed in a plane Λ shape so as to fit within the line 24.

Also in this silicon wafer inspection method, the quality of dicing can be evaluated in exactly the same way as the silicon wafer inspection method of the first embodiment.
That is, when dicing is performed along the scribe line 24 using a cutting device such as a dicing blade, the central portion of the pattern 51 is deleted by the dicing line 32 and micro patterns 26a, 26a,. Will remain.

For example, when the shapes of the minute patterns 26a, 26a,... Are symmetrical as shown in FIG. 7A, the center axis Ax ′ of the dicing line 32 substantially coincides with the center axis Ax of the scribe line 24. It will be.
In addition, when the shape of the minute patterns 26a, 26a,... Is as shown in FIG. 7B, the center axis Ax ′ of the dicing line 32 is displaced by the amount s of the center axis Ax of the scribe line 24. It will be shifted only.
When the shape of the minute patterns 26a, 26a,... Is as shown in FIG. 7C, the distance from the side surface of the dicing line 32 to the seal rings 31, 31 is extremely small. The width w is slightly narrower than the width W of the scribe line 24.

In this way, as in the inspection method of the first embodiment, by visually observing the shapes of the minute patterns 26a, 26a,... Remaining on both sides of the dicing line 32, the quality of dicing in the scribe line 24 can be visually checked. Moreover, it can be easily discriminated. Therefore, the quality of dicing can be determined easily and promptly, and the workability in the manufacturing process can be improved and the manufacturing cost can be reduced.
Further, since the pattern 51 of the present embodiment is formed so as to be accommodated in the scribe line 24, it can be inspected even after the individual chip 25 is formed.

“Fourth Embodiment”
FIG. 8 is a plan view showing a pattern formed on a silicon wafer (semiconductor wafer) according to the fourth embodiment of the present invention. The pattern 61 of the present embodiment is different from the pattern 51 of the third embodiment described above. The point is that, in the pattern 51 of the third embodiment, a plurality of rectangular micropatterns 26a are formed in a Λ shape in plan view, whereas in the pattern 61 of this embodiment, the spot-like micropattern 41a having a small diameter is used. Is formed in a Λ shape in plan view.

  Also in this silicon wafer inspection method, just like the silicon wafer inspection method of the third embodiment, by observing the shapes of the minute patterns 41a, 41a,... Sandwiched between the long patterns 26b, 26b, The quality of dicing can be evaluated. Therefore, even if it is not a skilled person, the quality of the dicing in the scribe line 24 can be determined visually and easily, and the workability in the manufacturing process can be improved and the manufacturing cost can be reduced.

  In the present invention, patterns 26, 27 for measuring the width w of a cutting region and the amount of displacement s when the silicon substrate 21 is cut by a scribe line 24, in the vicinity of the peripheral edge of the surface 21a of the silicon substrate 21. Since 41, 51 and 61 are formed, the present invention can be applied not only to CSP but also to semiconductor chips such as CSP other than this type, and its industrial effect is very large.

It is a top view which shows the silicon wafer of the 1st Embodiment of this invention. It is a top view which shows the pattern formed in the silicon wafer of the 1st Embodiment of this invention. It is a top view which shows the other pattern formed in the silicon wafer of the 1st Embodiment of this invention. It is a top view which shows the inspection method of the silicon wafer of the 1st Embodiment of this invention. It is a top view which shows the pattern formed in the silicon wafer of the 2nd Embodiment of this invention. It is a top view which shows the pattern formed in the silicon wafer of the 3rd Embodiment of this invention. It is a top view which shows the inspection method of the silicon wafer of the 3rd Embodiment of this invention. It is a top view which shows the pattern formed in the silicon wafer of the 4th Embodiment of this invention. It is sectional drawing which shows the cross-sectional structure of the dicing line vicinity after the dicing of the conventional semiconductor wafer. It is a top view which shows the semiconductor wafer after the conventional dicing.

Explanation of symbols

  21 ... Silicon substrate, 21a ... Surface, 22 ... Orientation flat, 23, 24 ... Scribe line (scribe region), 25 ... Chip (region), 26, 27, 41, 51, 61 ... Pattern, 26a, 27a, 41a ... Fine pattern, 26b, 27b ... long pattern, 31 ... seal ring, 32 ... dicing line.

Claims (11)

A semiconductor wafer formed by forming a semiconductor element in each of a plurality of semiconductor element formation regions partitioned by a scribe region on one main surface of a semiconductor substrate,
A semiconductor wafer, wherein a pattern for measuring a width of a cut region and a positional deviation amount when the semiconductor substrate is cut in the scribe region is formed on the one main surface.   The semiconductor wafer according to claim 1, wherein the pattern is a line-symmetric figure.   The semiconductor wafer according to claim 1, wherein the pattern is formed in the vicinity of a peripheral edge portion of the one main surface.   The semiconductor wafer according to claim 1, wherein the pattern is formed in the vicinity of a peripheral portion of the one main surface and on an extension of the scribe region.   5. The semiconductor wafer according to claim 1, wherein identification information is given to the pattern.   6. The semiconductor wafer according to claim 5, wherein the identification information includes numerical information or character information. A semiconductor element obtained from the semiconductor wafer according to any one of claims 1 to 6,
A semiconductor element obtained by cutting the semiconductor substrate at the scribe region.   A chip size package comprising the semiconductor device according to claim 7. A method for producing a semiconductor wafer, wherein a semiconductor element is formed in each of a plurality of semiconductor element formation regions partitioned by a scribe region on one main surface of a semiconductor substrate,
For measuring the width of the cut region and the amount of displacement when the semiconductor substrate is cut in the scribe region on the one main surface during or after the semiconductor element forming step of forming the semiconductor element. A method of manufacturing a semiconductor wafer, comprising a pattern forming step of forming a pattern.   10. The semiconductor wafer according to claim 9, wherein the semiconductor element forming step includes a step of forming an external connection terminal electrically connected to the semiconductor element, and the pattern forming step is performed simultaneously with the step. Manufacturing method. A semiconductor element is formed in each of a plurality of semiconductor element formation regions partitioned by a scribe region on one main surface of the semiconductor substrate, and a cutting region when the semiconductor substrate is cut at the scribe region on the one main surface. A method for inspecting a semiconductor wafer by forming a pattern for measuring the width and the amount of displacement thereof,
A method for inspecting a semiconductor wafer, comprising: observing a change in the pattern before and after cutting in the scribe region, and evaluating the quality of cutting based on the change in the pattern.

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