KR100681679B1 - Method for fabricating of semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to prevent previously occurrence of defects by forming a copper layer on a depressed substrate in a metal wiring layer formation process. An element formation layer manufacturing process is performed to manufacture an element formation layer on a silicon substrate in order to pattern a plurality of elements including a MOS transistor(S1). A pattern density inspection process is performed to inspect the pattern density of the element formation layer(S2,S3). A metal layer formation process is performed to form a metal layer on the element formation layer when the pattern density is uniform(S4).

Description

Method for fabricating a semiconductor device {Method for Fabricating of Semiconductor Device}

1 is a flow chart showing a semiconductor device manufacturing method according to the present invention.

2A to 2C are cross-sectional views illustrating a method of manufacturing an element formation layer.

3A and 3B are photographic views showing examples of pattern density inspection according to the present invention.

<Description of Reference Number Used in Drawing>

2: silicon substrate 4: gate

6: spacer 10: source, drain region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly, to a semiconductor device manufacturing method capable of improving a defective rate.

Semiconductor devices are fabricated by stacking a number of layers having various patterns formed on a silicon substrate. For example, a silicon substrate includes an element formation layer in which a MOS transistor or the like is patterned on an oxide layer obtained by thermally oxidizing a silicon substrate, and metal wiring layers are stacked thereon.

In the process of laminating each layer, before forming a new layer, a process of planarizing the existing layer is performed. This process utilizes the Chemical Mechanical Polishing (CMP) method.

The CMP process is affected by the height difference of the lower layer, so that the erosion phenomenon occurring in a specific area in the lower layer affects the upper layer.

This sinking phenomenon is closely related to the pattern density of the device formed on the substrate. In more detail, when tungsten (W) or copper (Cu) is CMP, the dissimilar material is polished. If the pattern density is higher than the periphery according to the pattern density (that is, the specific gravity of the material with high polishing rate increases) Occurs higher than the intrinsic polishing rate during the CMP process. Due to this phenomenon, a sinking phenomenon occurs in a portion having a high pattern density compared to a portion having a low pattern density.

When the sinking phenomenon occurs according to the pattern density in the device forming layer, the metal wiring layer stacked on it also affects the metal wiring layer. In the process of forming the copper wiring, such a problem occurs that the copper layer remains in the recess.

In the case of such a sinking phenomenon in the device formation layer, even if the semiconductor device is completed through numerous processes thereafter, the device eventually becomes a defective device, thus causing a waste of time and manufacturing cost.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving a defective rate.

In order to achieve these objects, according to the method of manufacturing a semiconductor device according to the present invention, a first step of manufacturing a device forming layer in which a plurality of devices including a MOS transistor is patterned on a silicon substrate, and inspecting the pattern density of the device forming layer And a third step of forming a metallization layer on the device formation layer when the pattern density is uniform in the second step. In this case, the second step includes scanning to the largest unit area, and scanning to the detailed unit area for a region having a pattern density of more than 15% among the maximum unit areas. The step of performing a pattern inspection is to set a window size of 40 μm × 40 μm to the maximum unit area, and the step of scanning to the detail unit area comprises a 1 μm × 1 μm window size as the detail unit area. It is characterized in that the step of pattern inspection.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a flowchart illustrating a method of manufacturing a semiconductor device according to the present invention. First, according to an embodiment of the present invention to fabricate a device forming layer on a silicon substrate to manufacture a semiconductor device (S1).

A method of forming such an element formation layer will be briefly described with reference to FIGS. 2A to 2C.

Referring to FIG. 2A, a gate 4 is formed on the silicon substrate 2, and spacers 6 for self-alignment are formed on sidewalls of the gate 4. In addition, the source / drain regions 10 may be formed by implanting impurities into the silicon substrate 2 at both sides of the gate 4.

2B, an interlayer insulating layer 12 is formed on the entire surface of the substrate 2 on which the gate 4 is formed. The photoresist pattern 11 for forming contact holes is formed on the interlayer insulating layer 12.

Subsequently, the interlayer insulating layer 12 is selectively etched using the photoresist pattern 11 as a mask to form the contact hole 13 as shown in FIG. 2C to manufacture the device forming layer 15.

After the device formation layer 15 is manufactured, pattern density inspection is performed. Pattern density inspection uses Technology Computer-Aided Design (TCAD). The order of inspecting the pattern density proceeds in the order of inspecting the detailed region (S3) according to the result of the rough inspection (S2) while scanning a wide region.

For example, in order to scan a large area at one time for a window of a window as shown in FIG. 3A, the entire wafer area is inspected while setting the 40 µm x 40 µm silicon substrate area to be the maximum unit area to be scanned.

At this time, the area where the pattern density is high, such as area A, is found, and the area is divided into detailed areas and examined. For example, the pattern density is examined while scanning the area where the pattern density is higher than 15% by dividing it into subunit areas of 1 µm x 1 µm at one time as shown in FIG. 3B. Thus, by dividing into detailed unit areas, the precise pattern density at the detailed position can be examined.

As described above, in the inspection of the pattern density of the detailed region, the region of which the pattern density is 18% or more is corrected.

That is, the pattern density may be redesigned or a dummy pattern may be formed to lower or uniform the pattern density.

Then, the metal wiring layer is formed on the silicon substrate having no abnormality in the pattern density inspection. (S4) The metal wiring layer embeds a metal wiring material, that is, polysilicon, tungsten, copper, aluminum, and an alloy thereof, in the contact hole. It is formed by connecting the connection between the device and the device and between the device and an external power supply.

As described above, the copper layer is formed on the recessed substrate in the process of forming the metal wiring layer, thereby preventing the defect from occurring. That is, according to the method of manufacturing a semiconductor device according to the present invention, by inspecting the pattern density due to the cause of the failure, the defective element can be removed in advance to increase the yield.

In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used for this purpose, they are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope of the invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

Claims (3)

A first step of manufacturing a device forming layer in which a plurality of devices including a MOS transistor are patterned on a silicon substrate, A second step of inspecting a pattern density of the device forming layer; And forming a metallization layer on the device formation layer when the pattern density is uniform in the second step. In claim 1, The second step is Scanning in the maximum unit area, And scanning the detailed unit region in a region of the maximum unit region in which the pattern density is higher than 15%. In claim 2, In the second step The scanning in the maximum unit area is a step of pattern inspection by setting a window size of 40 μm × 40 μm to the maximum unit area, The scanning in the sub-unit area is a step of performing a pattern inspection using a 1 µm × 1 µm window size as the sub-unit area.

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