JP2006108571A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure the flatness of an interlayer insulating film in a die region, and to provide multiple functions to a scribe region or minimize the scribe region. <P>SOLUTION: A semiconductor device having a multilayered wiring structure comprises an interlayer insulating film formed on a substrate having a die region 11 and a scribe region 12, a multilayered metal wiring layer (wiring pattern) 13 formed in the interlayer insulating film of the die region 11, and a dummy pattern 15 formed on the same layer as the metal wiring layer 13 and formed in the interlayer insulating film of the die region 11. Alignment marks 16 are formed in the dummy pattern 15 to form a lithography mark pattern. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having Cu damascene wiring.

  FIG. 6 is a top view for explaining a semiconductor device having a conventional alignment mark. As shown in FIG. 6, a wiring pattern 33 is formed in the die region 31, and a scribe region 32 exists around the die region 31. FIG. 6 shows a wafer for process evaluation, and the wiring pattern 33 is a measurement pattern for process evaluation. By cutting the scribe region 32, it is separated into semiconductor chips. In the scribe region 32, a target for alignment of the exposure apparatus, a lithography mark pattern such as an alignment mark pattern 36 and a focus monitor pattern 37 are formed. Various proposals have been made regarding alignment marks (see, for example, Non-Patent Document 1 and Non-Patent Document 2).

  However, with the recent miniaturization of semiconductor devices, the accuracy of dimensional accuracy required in the manufacturing process of semiconductor devices is increasing. As a practical alignment target, alignment accuracy of about 50 nm is essential for 90 nm node wiring and about 30 nm for 65 nm node wiring. This is because, at the 65 nm node, the wiring width target is miniaturized to about 100 nm, and even if the patterns are aligned with an alignment accuracy of 30 nm, a pattern deviation of 30% is allowed.

  Furthermore, chemical mechanical polishing (CMP) technology has become widespread in multilayer wiring technology. Techniques have been proposed in which dummy wiring is formed in an insulating film for the purpose of accelerating the polishing rate and insulating film dummy is formed in the wiring for the purpose of suppressing the polishing rate. By this technique, the wiring data rate in the wafer surface can be made uniform, and the polishing rate can be made uniform in the wafer surface. This technique will be described below.

  LSIs (Large Scale Integrated Circuits) such as microprocessors (MPUs) and custom LSIs that are known as typical semiconductor devices have been miniaturized year by year as the degree of integration has improved. In addition, the semiconductor region (impurity diffusion region) constituting the element is being formed with a small depth, and the size of the contact via provided in the interlayer insulating film for drawing the wiring out of the semiconductor region is also limited. Therefore, miniaturization of wiring is inevitable.

As a structure suitable for fine wiring, a so-called damascene structure is used in which a wiring groove is provided in an interlayer insulating film and a wiring is formed by embedding a conductor in the wiring groove (for example, Patent Document 1). reference.). This damascene structure will be described below with reference to FIG.
As shown in FIG. 7, a gate electrode 43 constituting a MOSFET as a semiconductor element is formed on a substrate 41 via a gate insulating film 42, and a source / drain region 44 as a semiconductor region is formed in an upper layer of the substrate 41. Yes. A contact plug 47 connected to the source / drain region 44 is formed in the silicon oxide film as the first interlayer insulating film 45 covering the gate electrode 43.
In the second interlayer insulating film 48 formed on the first interlayer insulating film 45, a first wiring 51 composed of strip-shaped wirings 51a, 51b, 51c,. A strip-shaped second wiring 52 is formed in parallel with 51. The first wiring 51 and the second wiring 52 have the above-described damascene structure. The wiring 51 b constituting the first wiring 51 is connected to the source / drain region 44 through the contact plug 47.
Here, the first wiring 51 is formed so that the plurality of wirings 51a, 51b, 51c,... Are dense, that is, the wiring density is increased. On the other hand, the second wiring 52 is formed by sparsely forming a single wiring. When the first wiring 51 and the second wiring 52 are formed, the surface of the second interlayer insulating film 48 is planarized by the CMP method. However, erosion 53 occurs on the surface of the second interlayer insulating film 48 in the vicinity of the first wiring 51 formed by densely arranging the plurality of wirings 51a, 51b, 51c,.

Next, a method for manufacturing the semiconductor device shown in FIG. 7 will be described with reference to FIG.
First, as shown in FIG. 8A, a MOSFET is formed using a known method. Specifically, element isolation and a well region are formed on the p-type silicon substrate 41 (not shown). Next, a gate electrode 43 is formed on the silicon substrate 41 with a gate insulating film 42 interposed therebetween. Then, impurity ions are implanted into the silicon substrate 41 using the gate electrode 43 as a mask. As a result, source / drain regions 44 are formed in the upper layer of the silicon substrate 41 in a self-aligned manner with respect to the gate electrode 43.

  Next, as shown in FIG. 8B, a first interlayer insulating film 45 made of a silicon oxide film or the like is formed on the entire surface of the silicon substrate 41 by a CVD method. A contact hole 46 connected to the source / drain region 44 is formed in the first interlayer insulating film 45 by lithography and etching. Thereafter, a plug 47 is formed by embedding a conductive material such as tungsten in the contact hole 46.

Next, as shown in FIG. 8C, a second interlayer insulating film 48 made of a silicon oxide film or the like is formed on the first interlayer insulating film 45 and the plug 47 by a CVD method. Then, a wiring trench 49 is formed in the second interlayer insulating film 48 by lithography and etching.
Subsequently, as shown in FIG. 8D, a conductor film 50 such as copper or aluminum is formed on the second interlayer insulating film 48 including the inside of the wiring trench 49. Then, unnecessary conductor film 50 is removed by CMP using second interlayer insulating film 48 as a stopper film. As a result, as shown in FIG. 8E, the first wiring 51 and the second wiring 52 each having a damascene wiring structure and having a damascene wiring structure are formed at desired positions of the second interlayer insulating film 48. Thereafter, as shown in FIG. 9, a third interlayer insulating film 54 is formed on the first wiring 51, the second wiring 52, and the second interlayer insulating film 48, thereby protecting the semiconductor element (MOSFET) from the external atmosphere. .
Here, the surface of the second interlayer insulating film 48 constituting the first wiring 51 and located between the densely arranged wirings 51 a, 51 b, 51 c,... It is inferior in strength as compared with the surface of the film 48. Therefore, when the conductor film 50 is subjected to CMP, weak portions are concentrated and polished, so that a recess is formed on the surface of the second interlayer insulating film 48 located between the wirings 51a, 51b, 51c,. That is, so-called erosion 53 occurs.
Incidentally, the conventional semiconductor device shown in FIGS. 8 and 9 has a problem that the flatness of the second interlayer insulating film 48 is inferior because the generation of erosion 53 cannot be avoided when the conductive film 50 is polished. Therefore, the upper layer wiring formed in the upper layer of the interlayer insulating film 48 with poor flatness, for example, the wiring formed in the third interlayer insulating film 54 is inconvenienced such as deformation or disconnection.

In order to solve the above-described problems, a method has been proposed in which a dummy wiring is formed between a first wiring in which wirings are densely arranged and a second wiring.
FIG. 10 is a plan view showing a conventional semiconductor device having dummy wirings, and FIG. 11 is a cross-sectional view taken along the line DD ′ of FIG. By forming the dummy wiring 55 around the second wiring 52 which is an isolated wiring, the wiring density in the second interlayer insulating film 48 can be made uniform. As a result, the mechanical strength of the surface of the second interlayer insulating film 48 can be made uniform, and the occurrence of erosion on the surface of the second interlayer insulating film 48 during the CMP of the conductor film 50 can be prevented. That is, the dummy wiring 55 is indispensable for flattening the second interlayer insulating film 48.

  However, if dummy wirings are simply formed randomly in order to flatten the interlayer insulating film, there is a problem that it is difficult to efficiently reduce the wiring capacity. In an extreme case, coupling of the dummy wiring 55 with the signal wiring 52 increases the effective capacitance, which increases the wiring capacitance, resulting in a problem that the circuit operation speed is reduced. Therefore, a method has been proposed in which the dummy wiring 55 is arranged at a distance L from the signal wiring 52 (see, for example, Patent Document 2).

M. Adel, 7 others, “Performance Study of New Segmented Overlay Marks for Advanced Wafer Processing”, 2003, SPIE Mike Adel, 7 others, “Characterization of Overlay Mark Fidelity”, 2003, SPIE US Pat. No. 6,232,231 JP 2000-286263 A

However, the CMP dummy pattern arranged in the die region of the conventional semiconductor device has no function by itself. That is, although the dummy wiring is not a useful structure after the completion of CMP, it has been necessary to provide the dummy wiring in the die region in order to planarize the interlayer insulating film described above. Therefore, conventionally, a dummy structure having no function exists in the product region (die region).
On the other hand, lithography mark patterns such as alignment marks and focus monitor marks have been arranged in the scribe area. For this reason, it is necessary to limit the number of lithography mark patterns by the area of the scribe region, or to make a large scribe region.
In recent years, with the miniaturization of wiring, multilayering of wiring has progressed. Therefore, in addition to the lithography mark pattern, it is necessary to form many monitor patterns such as a via chain pattern for via inspection and a layer resistance measurement pattern for wiring inspection in the scribe area. There were many cases that had to be done.

  The present invention has been made to solve the above-described conventional problems, and has an object of ensuring the flatness of the interlayer insulating film in the die region and making the scribe region multifunctional or downsized.

A semiconductor device according to the present invention is a semiconductor device having a multilayer wiring structure,
An interlayer insulating film formed on a substrate having a die region and a scribe region;
A multilayer metal wiring layer formed in the interlayer insulating film of the die region;
A dummy pattern formed in the same layer as the metal wiring layer and formed in the interlayer insulating film of the die region,
A lithography mark pattern is formed in the dummy pattern.

  In the semiconductor device according to the present invention, the lithography mark pattern is the same as the via alignment mark pattern formed in the same layer as the via constituting the metal wiring layer and the upper layer wiring or the lower layer wiring constituting the metal wiring layer. An alignment mark pattern having a wiring alignment mark pattern formed in the layer is preferable.

  In the semiconductor device according to the present invention, the outermost peripheral pattern constituting the alignment mark pattern and the dummy pattern are arranged apart from each other by a distance that can be recognized by the alignment measuring instrument. Is preferred.

  In the semiconductor device according to the present invention, the lithography mark pattern is a focus monitor pattern, and the outermost peripheral pattern constituting the focus monitor pattern and the dummy pattern can recognize the focus monitor pattern by a focus measuring instrument. It is preferable that they are spaced apart by a certain distance.

  In the semiconductor device according to the present invention, it is preferable that an area ratio of the lithography mark pattern in the die region is 10% or more.

  As described above, the present invention can ensure the flatness of the interlayer insulating film in the die region by using the dummy pattern in the die region and the lithography mark, and can make the scribe region multifunctional or downsized. Can do.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view for explaining a semiconductor device according to the first embodiment of the present invention. Specifically, it is a plan view showing a wafer having a test pattern for measuring the via resistance of a two-layer copper wiring.
As shown in FIG. 1, a wiring pattern 13 formed by embedding a conductive film such as a Cu film in a wiring groove formed in the interlayer insulating film is formed in the die region 11. In the first embodiment, the wiring pattern 13 is a via resistance measurement pattern, and the pattern 13 is connected to the pad 14. The length of one side of the pad 14 is, for example, 100 μm. A dummy wiring pattern (hereinafter referred to as “dummy pattern”) 15 is formed around the wiring pattern 13 and the pad 14 so as to be separated by a region having a length L1 (hereinafter referred to as “prohibited region”). The length L1 of the forbidden region is determined by the coupling capacitance, and is 10 μm, for example. As described in the prior art, the dummy pattern 15 is disposed to ensure high flatness of the interlayer insulating film during CMP.

In the first embodiment, an overlay mark 16 is formed inside the dummy pattern 15. That is, the dummy wiring pattern 15 in the die region 11 functions as the alignment mark 16. Thereby, a degree of freedom occurs in the arrangement of the alignment marks 16 in the semiconductor device. The area ratio of the alignment mark 16 in the die region 11 is preferably 10% or more.
The length A1 of one side of the alignment mark 16 is 24 μm, for example. The alignment marks 16 are regularly arranged, for example, in a lattice shape having a length A2 of 200 μm, and are also arranged in the center of the lattice. Further, the reason why the alignment marks 16 are not arranged in a perfect grid is that there are alignment marks 16 that disappear due to the arithmetic processing with the dummy pattern 15.

  A focus monitor mark 17, a layer resistance measurement pattern 18 for wiring inspection, and a via chain pattern 19 for via inspection are arranged in the scribe area 12 positioned around the die area 11.

  Here, there are a first method in which the scribe area is set as the prohibited area and a second method in which the scribe area is not set as the prohibited area. FIG. 1 shows the first method with the scribe area 12 as a prohibited area. In the second method, when the alignment mark is developed in a grid on the existing mask, it is necessary to perform a margin setting operation between the alignment mark and the fine alignment mark of the existing mask. In the first method, this margin setting work is unnecessary. Therefore, the first method is desirable for developing the mark in accordance with the existing mask.

FIG. 2 is an enlarged plan view showing the alignment mark in FIG.
As shown in FIG. 2, the alignment mark 16 has a square via alignment mark 16a and four wiring alignment marks 16b arranged outside the via alignment mark 16a.
The length D of one side of the via alignment mark 16a is, for example, 5 μm. The length B of the wiring alignment mark 16b is, for example, 7 μm, and the width C is, for example, 0.5 μm. An interval E between the via alignment mark 16a and the wiring alignment mark 16b is, for example, 2 μm. The length F of the recognition mark 16c is 3 μm, for example, and the width G is 1 μm, for example.
In order to make the alignment mark 16 recognizable by scanning, the dummy pattern 15 is separated from the outermost wiring alignment mark 16b of the alignment mark 16 by a length L2. The length L2 is determined by the accuracy of the alignment measuring device that performs scanning, and is, for example, 10 μm.

FIG. 3 is a cross-sectional view showing a first example of the alignment mark.
As shown in FIG. 2, the alignment mark 16 has a via alignment mark 16a and a wiring alignment mark 16b surrounding the mark 16a. As shown in FIG. 3, the wiring alignment mark 16 b is formed in the same layer as the lower metal wiring 23, and the via alignment mark 16 a is formed in the same layer as the via 25. Specifically, the wiring alignment mark 16 b is formed in a dummy pattern 15 a formed in the same layer as the lower layer metal wiring 23. The via alignment mark 16 a is formed in a dummy pattern 15 b formed in the same layer as the via 25.

Next, a method for manufacturing the structure shown in FIG. 3 will be described.
First, a first interlayer insulating film 22 is formed on a base layer 21 formed on a substrate (not shown). Here, although not shown, a semiconductor element such as a MOSFET is formed on the substrate. Next, a plurality of grooves to be the lower metal wiring 23, the dummy pattern 15a, and the wiring alignment mark 16b are formed in the first interlayer insulating film 22 by using a lithography technique and a dry etching technique. A conductive film such as a film is deposited. Thereafter, by performing CMP of the Cu film using the first interlayer insulating film 22 as a stopper film, the lower metal wiring 23, the dummy pattern 15 a and the wiring alignment mark 16 b are formed in the first interlayer insulating film 22.
Next, a second interlayer insulating film 24 is formed on the entire surface of the substrate. Next, using the same technique as described above, a plurality of grooves to be the via 25, the dummy pattern 15b, and the via alignment mark 16a are formed in the second interlayer insulating film 24, and the conductive film is formed so as to fill the grooves. Deposit. Thereafter, CMP of the conductive film is performed using the second interlayer insulating film 24 as a stopper film, thereby forming vias 25, dummy patterns 15 b and via alignment marks 16 a in the second interlayer insulating film 24.
Next, a third interlayer insulating film 26 is formed on the entire surface of the substrate. Next, using the same method as described above, a groove to be the upper metal wiring 27 is formed in the third interlayer insulating film 26, and a conductive film is deposited so as to fill the groove. Thereafter, the upper layer metal wiring 27 is formed in the third interlayer insulating film 26 by performing CMP of the conductive film using the third interlayer insulating film 26 as a stopper film.

  A silicon oxide film may be formed by CVD as the interlayer insulating films 22, 24, and 26. A low dielectric constant film having a lower relative dielectric constant than that of the silicon oxide film is used in order to reduce the propagation of electric signals. It may be formed. As the low dielectric constant film, a silicon oxide film doped with an organic group such as a SiOC film may be formed by a CVD method. An MSQ (Methyl Silsesquioxane) film, an HSQ (Hydrogen Silsesquioxane) film, or a polymer (for example, SiLK (registered trademark) manufactured by Dow Chemical Co., Ltd.), those having pores introduced therein, or a laminated film thereof may be formed by a spin coating method.

FIG. 4 is a cross-sectional view showing a second example of the alignment mark.
In the first example shown in FIG. 3, the wiring alignment mark 16 b is formed in the same layer as the lower metal wiring 23. In the second example shown in FIG. 4, the wiring alignment mark 16 b is formed in the same layer as the upper metal wiring 26. Specifically, the wiring alignment mark 16 b is formed in a dummy pattern 15 c formed in the same layer as the upper metal wiring 27. The via alignment mark 16a is the same as the first example shown in FIG.

Next, a method for manufacturing the structure shown in FIG. 4 will be described. The description will focus on the differences from the method of manufacturing the structure shown in FIG.
First, the first interlayer insulating film 22 is formed on the base layer 21. Next, after forming a trench to be the lower metal wiring 23 in the first interlayer insulating film 22, a conductive film is deposited. Thereafter, the lower metal wiring 23 is formed in the first interlayer insulating film 22 by performing CMP of the conductive film.
Next, using the same method as described above, a second interlayer insulating film 24 is formed on the entire surface of the substrate, and vias 25, dummy patterns 15 b and via alignment marks 16 a are formed in the second interlayer insulating film 24.
Next, a third interlayer insulating film 26 is formed on the entire surface of the substrate. Then, a plurality of grooves to be upper metal wiring 27, dummy pattern 15c, and wiring alignment mark 16b are formed in the third interlayer insulating film 26, and a conductive film is deposited. Thereafter, CMP of the conductive film is performed using the third interlayer insulating film 26 as a stopper film, thereby forming the upper metal wiring 27, the dummy pattern 15 c, and the box mark 16 b in the third interlayer insulating film 26.

As described above, in the first embodiment, the alignment mark 16 is formed in the dummy pattern 15 so that the dummy pattern 15 formed in the die region 11 has the function of the alignment mark 16. Therefore, the via alignment mark 16a constituting the alignment mark 16 can accelerate the CMP polishing rate in the via 25 formation process, and the wiring alignment mark 16b located outside the via alignment mark 16a is in the metal wiring 23 and 27 formation process. The CMP polishing rate can be promoted. For this reason, the flatness of the interlayer insulating film can be ensured.
Further, since the pattern alignment measurement can be performed inside the die region 11, accurate alignment measurement information in the product can be collected.

  Further, since the alignment marks 16 can be arranged inside the die region 11, it is not necessary to arrange the alignment marks 16 in the scribe region 12, or the number of alignment marks 16 arranged in the scribe region 12 is greatly reduced. be able to. Therefore, a TEG (for example, a monitor pattern) having other functions can be disposed in the portion where the conventional alignment mark 16 of the scribe region 12 has been disposed. Alternatively, when the alignment mark, the focus monitor 17 and the monitor pattern (layer resistance measurement pattern 18 and via chain pattern 19) are arranged in the scribe area 12, the width of the scribe area 12 must be widened. The scribe region 12 can be reduced by the area occupied by the alignment mark 16.

  The shape of the dummy pattern 15 may be arbitrary, and the alignment mark 16 can be disposed inside the pad-shaped or T-shaped dummy pattern.

Embodiment 2. FIG.
In the first embodiment described above, the dummy wiring pattern in the die region 11 functions as the alignment mark. However, in the second embodiment of the present invention, the dummy wiring pattern in the die region 11 functions as the focus monitor pattern. There is a feature. Hereinafter, the difference from the first embodiment will be mainly described.

FIG. 5 is an enlarged plan view showing the focus monitor in the semiconductor device according to the second embodiment of the present invention.
As shown in FIG. 5, the focus monitor 20 includes a wiring 20a having a large line width and a wiring 20b having a small line width connected to the wiring 20a. Specifically, the plurality of wirings 20b are arranged so as to extend from the long side of the wiring 20a in the outer peripheral direction. By measuring the length H of the thin wiring 20b in the focus monitor 20, the focus position can be monitored. The focus monitor 20 is formed inside the dummy pattern 15 in the metal wiring layer and the via layer.
It is desirable to set the wiring width and wiring interval of the thin wiring 20b to the minimum wiring width of the product node. For example, in a 65 nm node / back end system, both the wiring width and the wiring interval are preferably about 90 nm.
In addition, the wiring length H of the thin wiring 20b is preferably about 200 nm in consideration of the resist receding phenomenon. This is because resist receding can occur about 100 nm, and when the wiring length H is 100 nm or less, the thin wiring 20b may disappear and only the thick wiring 20a may be formed.
Further, in order to make the focus monitor 20 recognizable by scanning, the dummy pattern 15 and the outermost wiring 20b of the focus monitor 20 are separated by a length L3. The length L3 is determined by the accuracy of the focus measuring instrument that performs scanning, and is, for example, 10 μm.
An alignment mark can be formed in the scribe region.

As described above, in the second embodiment, the focus monitor 20 is formed in the dummy pattern 15 so that the dummy pattern 15 formed in the die region has the function of the focus monitor. Therefore, the focus monitor 20 can increase the CMP polishing rate in the wiring and via formation process. For this reason, the flatness of the interlayer insulating film can be ensured.
Further, the focus monitor 20 according to the second embodiment is more suitable as a CMP dummy than the alignment mark 16 according to the first embodiment because the wiring area can be increased. That is, since the wiring area ratio of the focus monitor mark is high, the CMP polishing rate can be increased.
Further, in the second embodiment, the polishing rate can be easily controlled by optimizing the ratio of the wiring width I of the thick wiring 20a and the wiring width J of the thin wiring 20b that constitute the focus monitor 20. it can.
In addition, since it is possible to develop the focus monitor mark over the entire die area, it is possible to satisfy a narrow depth of focus tolerance in a high-resolution lithography technique using a high NA (Numerical Aperture) lens. it can.

  Further, since the focus monitor 20 can be arranged inside the die area, it is not necessary to arrange the focus monitor in the scribe area, or the number of focus monitors arranged in the scribe area can be greatly reduced. Therefore, a TEG (for example, a monitor pattern) having other functions can be disposed in a portion where the conventional focus monitor 20 is disposed in the scribe area. Alternatively, when the mark, focus monitor, and monitor pattern (layer resistance measurement pattern, via chain pattern) are arranged in alignment with the scribe area and the width of the scribe area has to be widened, the focus monitor 20 occupies it. The scribe area can be reduced by the area.

  The shape of the dummy pattern 15 may be arbitrary, and the focus monitor 20 can be arranged inside a pad-type or T-shaped dummy pattern.

It is a top view for demonstrating the semiconductor device by Embodiment 1 of this invention. It is a top view which expands and shows the alignment mark in FIG. It is sectional drawing which shows the 1st example of the alignment mark. It is sectional drawing which shows the 2nd example of the alignment mark. In the semiconductor device by Embodiment 2 of this invention, it is a top view which expands and shows a focus monitor. It is a top view for demonstrating the semiconductor device which has the conventional alignment mark. It is sectional drawing for demonstrating the semiconductor device which has a damascene structure. FIG. 8 is a process cross-sectional view for explaining the manufacturing method of the semiconductor device shown in FIG. 7 (No. 1); FIG. 8 is a process cross-sectional view for explaining the manufacturing method of the semiconductor device shown in FIG. 7 (No. 2). It is a top view which shows the conventional semiconductor device which has a dummy wiring. It is D-D 'sectional drawing of FIG.

Explanation of symbols

11 Die area 12 Scribe area 13 Wiring pattern 14 Pad 15 Dummy wiring pattern 16 Alignment mark 16a Via alignment mark 16b Wiring alignment mark 17 Focus monitor 18 Layer resistance measurement pattern 19 Via chain pattern 20 Focus monitor 20a, 20b Wiring 21 Underlayer 22 Second 1 interlayer insulating film 23 lower layer metal wiring 24 second interlayer insulating film 25 via 26 third interlayer insulating film 27 upper layer metal wiring

Claims (5)

A semiconductor device having a multilayer wiring structure,
An interlayer insulating film formed on a substrate having a die region and a scribe region;
A multilayer metal wiring layer formed in the interlayer insulating film of the die region;
A dummy pattern formed in the same layer as the metal wiring layer and formed in the interlayer insulating film of the die region,
A semiconductor device, wherein a lithography mark pattern is formed in the dummy pattern. The semiconductor device according to claim 1,
The lithography mark pattern includes a via alignment mark pattern formed in the same layer as the via forming the metal wiring layer, and a wiring alignment mark formed in the same layer as the upper layer wiring or the lower layer wiring configuring the metal wiring layer. A semiconductor device, characterized in that the semiconductor device is an alignment mark pattern having a pattern. The semiconductor device according to claim 2,
A semiconductor device characterized in that an outermost peripheral pattern constituting the alignment mark pattern and the dummy pattern are arranged apart from each other by a distance that allows the alignment measuring device to recognize the alignment mark pattern. The semiconductor device according to claim 1,
The lithography mark pattern is a focus monitor pattern, and the outermost peripheral pattern constituting the focus monitor pattern and the dummy pattern are spaced apart by a distance that allows the focus monitor pattern to be recognized by the focus measuring instrument. A semiconductor device characterized by the above. The semiconductor device according to claim 1,
An area ratio of the lithography mark pattern in the die region is 10% or more.

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