JP2002134397A - Photomask, semiconductor device, method for exposing semiconductor chip pattern and chip alignment accuracy inspecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photomask, a semiconductor device, a method for exposing a semiconductor chip pattern, and a chip alignment accuracy inspecting device capable of accurate alignement by eliminating deviations, distortions or the like of a chip array. SOLUTION: When a plurality of semiconductor chip patterns 30 are sequentially arranged adjacent on one water and then exposed, marks 31a, 31b, 31c, and so on for measuring aligning accuracy for measuring positional relation of the adjacent semiconductor chip patterns 30 are provided on the peripheries of the patterns 30. The deviation amount the alignment accuracy of the chip array are measured, based on the superposed positional relation between the adjacent chips of the marks 31a, 31b, and 31c for measuring the alignment accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photomask used for arranging a plurality of semiconductor device chips on a single wafer, a semiconductor device manufactured using the same, and a semiconductor for patterning the photomask. The present invention relates to a chip pattern exposure method and a chip alignment accuracy inspection device for inspecting the alignment accuracy of the chip arrangement.

[0002]

2. Description of the Related Art In semiconductor devices such as integrated circuits, fine patterns and high integration have been increasingly promoted in recent years with the increase in memory capacity and the increase in the functions of logic such as CPUs. In addition to integrated circuits, for example, CCD
In an image pickup device such as a charge coupled device (Charge Coupled Device), similar fine patterning and high integration are being promoted as one type of semiconductor device by utilizing the fine pattern forming technology cultivated in integrated circuits. I have.

In a semiconductor device such as an integrated circuit, exposure is generally performed by a step-and-repeat method using a so-called stepper exposure device until a generation to which the 0.25 [μm] rule is applied. I was However, in the generation to which the 0.25 to 0.18 [μm] rule is applied, in a manufacturing process of one semiconductor device, an exposure process by a step-and-repeat method and a so-called scanner exposure device (also referred to as a scan exposure device) ) And an exposure step by a scanning method have been used together.

That is, in an element pattern forming step in which it is strongly required to precisely form a fine pattern of less than 0.25 [μm] such as each structural portion of an element or a wiring pattern, exposure by a scanning method (hereinafter, referred to as a scanning method) , This is the first
Of the resist pattern used in the ion implantation, for example, a line width of 0.25.
In a process of forming a so-called rough layer pattern having a relatively low definition of [μm] or more, it is general to perform exposure by a step-and-repeat method (hereinafter, referred to as a second exposure process). It is becoming more and more.

[0005] As the fine patterning and high integration of such semiconductor devices have progressed, the alignment (alignment) accuracy when arranging chips of a plurality of semiconductor devices on one wafer has become increasingly higher. Is being demanded.

[0006]

However, in the conventional semiconductor chip pattern exposure method, for example, when the above-described scanner method and step-and-repeat method are used in combination, there is a deviation in the chip arrangement in the first exposure step. If this occurs, the alignment accuracy in the second exposure step may be significantly reduced due to the shift, and it is extremely difficult to correct such a chip arrangement shift in the second exposure step. There are cases.

That is, first, a first exposure process is performed by a scanner exposure apparatus, for example, using the outer shape of the wafer as a reference for alignment.
Since a reference position mark or the like that enables strict alignment has not been provided yet, a deviation or an error may occur in the exposure shape or position of the semiconductor chip pattern at this stage.

Subsequently, using a stepper exposure device, a second exposure process is performed to transfer the second pattern while performing alignment with respect to the first pattern formed in the first exposure process. . The alignment at this time is performed using a mask alignment pattern or the like formed in the first exposure step as a reference position. In general, the degree of freedom of alignment adjustment of the shape and position of the exposure pattern in a stepper exposure apparatus is used. Is lower than that of the scanner exposure apparatus, so it is difficult to accurately follow the chip arrangement and shape deviation already occurring in the first exposure step in the second exposure step using this stepper exposure apparatus. In many cases.

As described above, in the conventional semiconductor chip pattern exposure method, for example, the first pattern exposed using a scanner exposure apparatus is liable to cause a chip arrangement shift, a distortion of the outer shape of the semiconductor chip pattern, and the like. There was a problem of becoming. In addition, there has been a problem that it is often difficult to precisely align such a first pattern with a second pattern exposed by, for example, a stepper exposure apparatus after the first pattern is formed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to perform high-precision alignment by eliminating a chip arrangement shift, a distortion of an outer shape of a semiconductor chip pattern, and the like. An object of the present invention is to provide a photomask, a semiconductor device manufactured using the same, a method of exposing a semiconductor chip pattern for patterning the photomask, and a chip alignment accuracy inspection device for inspecting alignment accuracy of the chip arrangement.

[0011]

A photomask according to the present invention is a photomask used when a plurality of semiconductor chip patterns are sequentially arranged on a single wafer so as to be adjacent to each other and exposed. In addition, alignment accuracy measurement marks for measuring the positional relationship between adjacent semiconductor chip patterns are provided around each of the semiconductor chip patterns.

A semiconductor device according to the present invention is formed by arranging a plurality of semiconductor chip patterns one by one on a single wafer so as to be sequentially adjacent to each other, exposing the semiconductor chip patterns, and performing processing based on the semiconductor chip patterns. Semiconductor device in which at least a part of an alignment accuracy measurement mark capable of measuring a positional relationship between adjacent semiconductor chip patterns on one wafer is left around each of the semiconductor chip patterns. It is.

The method for exposing a semiconductor chip pattern according to the present invention is an exposure method for arranging and exposing a plurality of semiconductor chip patterns one by one on a single wafer so as to be adjacent to each other. The method includes a step of providing an alignment accuracy measurement mark around each of them and measuring a positional relationship between adjacent semiconductor chip patterns.

The chip alignment accuracy inspection apparatus according to the present invention is used in an exposure step for arranging and exposing a plurality of semiconductor chip patterns one by one sequentially on a single wafer so as to be adjacent to each other. A positioning accuracy measurement mark is provided at a predetermined position around each semiconductor chip pattern, and the positional relationship between the positioning accuracy measurement marks of adjacent semiconductor chip patterns is measured, and the measurement result is Based on this, information on the positional relationship between adjacent semiconductor chip patterns is detected (understood).

A photomask, a semiconductor device,
In a semiconductor chip pattern exposure method and a chip alignment accuracy inspection apparatus, a positional relationship between adjacent semiconductor chip patterns exposed on one wafer is measured by a positioning accuracy measurement provided around each of the semiconductor chip patterns. It is measured based on the positional relationship between the use marks or the state of overlap.

Further, in the semiconductor device according to the present invention, at least a part of the alignment accuracy measurement mark used at the time of exposing the semiconductor chip pattern can be used during the process of processing the chip or after the semiconductor device is completed. By leaving the mark on the chip, the above-described alignment accuracy measurement mark is used as information to be used as a judgment material in quality control and quality assurance of the alignment accuracy of the semiconductor chip. Note that the above semiconductor device is
It may be formed as a semiconductor chip on one wafer and cut into individual chips by cutting the wafer, or may be arranged on a single wafer without being cut as individual semiconductor chips. It may be in a formed state.

In the chip alignment accuracy inspection apparatus according to the present invention, information on the positional relationship between adjacent semiconductor chip patterns is grasped based on the measured positional relationship between the alignment accuracy measurement marks.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a process from a step of exposing a semiconductor chip pattern using a photomask according to the present embodiment to a step of forming individual semiconductor chips on a wafer and measuring the alignment accuracy and the like. It is a flow chart schematically showing main manufacturing steps.

This manufacturing process includes a first exposure step 1 for exposing a first pattern on a resist on a wafer using a scanner exposure apparatus, and a first exposure step for forming a first pattern based on the resist pattern. A patterning step 2;
A first measurement step 3 for measuring the positional relationship and alignment accuracy between adjacent chips of the first pattern, and a second step of exposing the second pattern by a sputter exposure apparatus.
Exposure step 4 and the second
A second patterning step 5 for forming the first pattern, a second measuring step 6 for measuring the alignment accuracy between chips adjacent to the second pattern, and a first patterning step in the next first exposure step 1. An exposure pattern correction process 7 for calculating data for performing the adjustment and correcting the positional relationship between the chips of the first pattern based on the data is provided as main processes.

More specifically, in the first exposure step 1,
As shown in FIG. 2, the alignment accuracy measurement mark 31
a, 31b, 31c, 31d, 31e, 31f, 31
g, 31h (hereinafter, referred to as the alignment accuracy measurement mark 31 when these are collectively referred to) is a pattern provided with two for each vertex of the rectangular (rectangular or square) outer shape of each semiconductor chip pattern 30 Using a photomask 8 on which is formed, a chip is exposed one chip at a time by a scanner exposure device, and a first pattern in which a semiconductor chip pattern 30 and alignment accuracy measurement marks 31 are arranged as shown in FIG. Is formed on the resist on the wafer. By developing the latent image, a first resist pattern is formed.

In the first patterning step 2, a first pattern is formed on the wafer by performing, for example, dry etching on the basis of the resist pattern.

More specifically, for example, a pattern as shown in FIG. 4 can be suitably used as the pattern of the alignment accuracy measurement mark 31. That is, a total of four alignment accuracy measurement marks 31a, 31b, 3 formed on the left side and lower side around the semiconductor chip pattern 30.
1c and 31d are patterns A as shown in FIG.
And a total of four alignment accuracy measurement marks 31e, 31f, 31g, 31h formed on the right side and the upper side.
Is a pattern B as shown in FIG. As shown in FIG. 3, these patterns A and B are formed by a plurality of semiconductor chip patterns 30 having a predetermined (regular) shape.
If they are correctly arranged for each position, adjacent chips overlap in a normal state as shown in FIG. However, when the position of each chip is shifted in the x direction (vertical direction in the figure) or the y direction (horizontal direction in the figure), FIG.
As shown in (D), the pattern A and the pattern B are relatively biased. By measuring the size of the deviation, it is possible to detect (determine) the amount of misalignment between adjacent chips and the alignment accuracy. Alternatively, as shown in FIG.
When there is an oblique deviation, it is possible to detect that there is a deviation in the rotational direction in the positional relationship between adjacent chips, the amount of deviation, the alignment accuracy in the rotational direction, and the like.

In the first measurement step 3, the amount of deviation between the pattern A and the pattern B as described above is measured by a chip alignment accuracy inspection device, and based on the measurement result, the difference between the chips of the first pattern is determined. Detects positional deviation and alignment accuracy. More specifically, the first
In the case where the first pattern is formed without correcting the positional relationship between the chips of the above pattern, the shift amount between the pattern A and the pattern B is a measurement result as shown in an example in FIG. From the data of the shift amount, FIG.
The alignment accuracy of the positional relationship between the semiconductor chip patterns 30 as shown in FIG.

In this example, the shift amount (unit [nm], hereinafter the same) between the pattern A and the pattern B measured by the upper left side Site 11 of the semiconductor chip pattern 30 is Δx =
−26.3, Δy = −3.8, and the shift amount between the pattern A and the pattern B measured in the upper right side of the Site 12 is Δx
= -19.1, Δy = -9.7, Site21 on the right side
The amount of deviation between pattern A and pattern B measured at
x = 46.7, Δy = 24.2, Site22 on the lower right side
The amount of deviation between pattern A and pattern B measured at
x = 39.6, Δy = 29.8.

The alignment accuracy (unit [ppm], hereinafter the same) calculated by the chip alignment accuracy inspection apparatus based on the measurement result is a shot magnification x (x
(The amount of deviation in the direction expressed by the shot magnification) is 2.15
2. The shot magnification y (the amount of displacement in the y direction expressed by the shot magnification) is -0.306, the shot rotation (the amount of displacement in the rotation direction) is 1.348, and the shot orthogonality (the amount of shot orthogonality shift). ) Is -0.313.

In addition to the patterns shown in FIG. 4 as the patterns of the alignment accuracy measurement marks 31, FIG.
Rectangular patterns A and B as shown in (A) and (B)
Alternatively, cross-shaped patterns A and B as shown in FIGS. 7A and 7B can be preferably used. In addition, in correspondence with the positive / negative of the resist, for example, FIG.
As shown in (A), (B) and (C), it is also possible to use a mask pattern in which the positive / negative of FIGS. 4, 6 and 7 is inverted.

In the second exposure step 4, a resist is applied on the wafer on which the first pattern has been formed as described above, and the resist is exposed to a second pattern by a sputter exposure apparatus. At this time, based on the data of the amount of displacement between the pattern A and the pattern B measured in the first measurement step 3 or the data of the amount of displacement of the positional relationship between adjacent chips, the first pattern for each chip of the first pattern is obtained. The alignment may be corrected for each shot of each chip of the second pattern. Also in the second exposure step 4, a second alignment accuracy measurement mark 32 as shown in the example of FIG. 9A is provided for each vertex around each chip. The mark 31 for measuring the alignment accuracy of the first pattern as shown in an example in FIG.
May be distinguishably overlapped with each other, so that the relative positional relationship and alignment accuracy of the chip of the second pattern with respect to the chip position of the first pattern may be measured.

In the second patterning step 5, based on the resist pattern in the second exposure step 4, for example, by a dry etching method or a wet etching method,
A second pattern is formed.

In the second measurement step 6, if the second alignment accuracy measurement mark 32 as shown in FIG. 9 is formed in the second pattern, the second alignment accuracy measurement is performed. The relative positional relationship between the pattern mark 32 and the pattern A and the pattern B of the first alignment accuracy measurement mark 31 is measured by a chip alignment accuracy inspection device, and based on the measurement result, each chip is measured. A positional deviation amount and an alignment accuracy between the first pattern and the second pattern are measured. Alternatively, even when the second alignment accuracy measurement mark 32 is not formed, the occurrence of the positional deviation between the first pattern and the second pattern and the amount of the positional deviation can be determined with a general accuracy by a general measuring method. measure. In addition, when the deviation amount measured at this time is out of the predetermined allowable range, it can be determined that an alignment failure has occurred.

More specifically, when the second pattern is formed without correcting the positional relationship between chips adjacent to the first pattern, the second pattern with respect to the first pattern is formed by a general alignment method. The amount of misalignment remaining after performing pattern alignment
The measurement results are as shown in an example in FIG. 10A, and the alignment accuracy of the positional relationship between the chips as shown in FIG. 10B is calculated from the data.

In this example, the amount of misalignment in the x direction (Residualx, unit [nm], the same applies hereinafter) is 31.
5. The amount of misalignment (Residualy) in the y direction is 4
6.7. The alignment accuracy calculated by the chip alignment accuracy inspection apparatus based on the measurement result is as follows: shot magnification x is -1.99, shot magnification y is -0.77, shot rotation is -2.56, and shot orthogonality is 0. .54.

In the exposure pattern correction step 7, a calculation method as shown in FIG. 11 is used on the basis of the data of the shift amount as shown in FIG. 5 obtained in the first measurement step 3. Then, the correction value is calculated and the position and shape of each chip of the first pattern in the next first exposure step 1 are corrected (adjusted) to correct the alignment of the chip arrangement. Furthermore, it is also possible to correct the alignment of the shot position of each chip of the second pattern with respect to each chip of the first pattern based on the data of the amount of deviation between the first pattern and the second pattern. Here, in FIG. 11, the Shot magnification X shown in FIG.
x, Shot magnification Y is My, Shot rotation is Rs, Sh
ot orthogonality is Os, and chip size (outer dimension) is A
x and Ay.

When the first pattern is formed by correcting the positional relationship between adjacent chips in this way,
The displacement between the pattern A and the pattern B results in a measurement result as shown in an example in FIG. 12A. From the data of the displacement, the alignment accuracy of the positional relationship between the chips as shown in FIG. Is calculated.

In this example, the shift amount between the pattern A and the pattern B measured at the Site 11 is Δx = −6.2,
Δy = 2.0, the deviation amount between pattern A and pattern B measured at Site 12 is Δx = 0.9, Δy = −1.
2. Pattern A and pattern B measured at Site 21
Δx = 13.1, Δy = −0.9, Si
The deviation amount between the pattern A and the pattern B measured at te22 is Δx = 5.3, Δy = 3.9, and the deviation amount in the case where the correction shown in FIG. In comparison with the amount, the shift amount is corrected to a fraction to several tenths. The alignment accuracy calculated by the chip alignment accuracy inspection device is
The shot magnification x is 0.460, the shot magnification y (shot magnification in the y direction) is 0.018, the shot rotation (accuracy in the rotation direction) is 0.075, and the shot orthogonality is 0.047.
FIG. 5 when no correction is performed
Compared with the alignment accuracy shown in FIG. 9A, the accuracy is improved by one or two digits, and it can be confirmed that effective correction is performed.

After the first pattern is formed by correcting the positional relationship between the adjacent chips, the second exposure step 4 is performed while performing alignment of each shot with respect to the first pattern. When the second pattern is formed, as shown in an example in FIG. 13, the shift amount (Residualx) in the x direction is 26.7, and the shift amount (Residualy) in the y direction is 33.9. As compared with the shift amount as shown in FIG. 10 when the correction is not performed, the shift amount is 5 [nm] in the x direction and 13 [n] in the y direction.
m] means that alignment can be performed with sufficiently high precision in an actual process. The alignment accuracy calculated by the chip alignment accuracy inspection apparatus based on the measurement result is such that the shot magnification x is 0.57, the shot magnification y is -0.42, the shot rotation is 0.88, and the shot orthogonality is 0. .19, the accuracy of each parameter is about twice or more higher than the alignment accuracy as shown in FIG. 10 when the correction is not performed. It can be confirmed that is performed.

As described above, the displacement between adjacent chips of the first pattern is corrected to improve the alignment accuracy of the chip arrangement in the first pattern and the alignment accuracy of the first pattern and the second pattern. It is possible to achieve improvement.

The alignment accuracy measurement mark 31
May be slightly disadvantageous in maintaining the measurement accuracy in the rotation direction. For example, as shown in FIG. 14, one piece is disposed at the center of each side around the semiconductor chip pattern 30. Is also good.

The measurement and correction of the shift amount and the alignment accuracy may be performed for each chip as described in the above embodiment, or the shift amounts of all chips formed on one wafer may be measured. The average value or the average value of the alignment accuracy may be calculated, and the correction common to all the chips may be performed based on the calculated average value and the average value of the alignment accuracy.

In the above embodiment, the steps up to the step of arranging the semiconductor chips on the wafer have been described. However, when the wafer is cut and separated into individual semiconductor chips, each of the semiconductor chips is separated. The alignment accuracy measurement mark may be left partially. In this way, when the separated semiconductor chip is handled during the mounting process or as a product, the alignment accuracy measurement mark remaining on the chip is used to determine the alignment accuracy of the semiconductor chip. Alternatively, the information can be used as information for assurance, which can contribute to quality control and quality assurance of the semiconductor chip.

[0041]

As described above, claims 1 to 4
According to the photomask according to any one of the claims, the semiconductor device according to the fifth or sixth aspect, the semiconductor chip pattern exposure method according to any one of the seventh to twelfth aspects, and the chip alignment accuracy inspection apparatus according to the thirteenth aspect The positional relationship between adjacent semiconductor chip patterns exposed on one wafer is determined based on the positional relationship between overlapping alignment measurement marks provided around each of the semiconductor chip patterns or the state of overlap. Since measurement is performed, it is possible to manage and correct the positional relationship between adjacent semiconductor chip patterns exposed on one wafer based on the measurement result, and to achieve high-precision alignment of the chip arrangement. And the shape of the semiconductor chip pattern can be corrected with high accuracy.

According to the semiconductor device of the present invention, at least a part of the alignment accuracy measurement mark used at the time of exposing the semiconductor chip pattern is removed during the processing of the semiconductor chip. Since it is left on the chip even after it is completed as a semiconductor device, the mark for measuring the alignment accuracy is used as information to determine the alignment accuracy of the semiconductor chip during the processing process or as a product. This can be applied to the improvement of alignment accuracy in the semiconductor chip, quality control or quality assurance, and the like.

According to the chip alignment accuracy inspection apparatus of the present invention, information on the positional relationship between adjacent semiconductor chip patterns is grasped based on the measured positional relationship between the alignment accuracy measurement marks. Based on the information, correction of alignment in the next product lot or wafer exposure process, or inspection of alignment accuracy of semiconductor chips,
Quality control and quality assurance can be performed.

[Brief description of the drawings]

FIG. 1 is a flowchart schematically illustrating main manufacturing steps from a step of exposing a semiconductor chip pattern using a photomask according to the present embodiment to a step of measuring alignment accuracy and the like of each semiconductor chip. FIG.

FIG. 2 is a diagram showing an example of a mask pattern provided with an alignment accuracy measurement mark formed on a photomask.

FIG. 3 is a diagram showing an example of a first pattern formed by arranging semiconductor chip patterns and alignment accuracy measurement marks on a wafer.

FIG. 4 is a diagram showing an example of a pattern of alignment accuracy measurement marks.

FIG. 5 is a diagram illustrating an example of a measurement result of a shift amount of a mark for measuring alignment accuracy between adjacent chips.

FIG. 6 is a diagram showing another example of the pattern of the alignment accuracy measurement mark.

FIG. 7 is a diagram showing still another example of the pattern of the alignment accuracy measurement mark.

FIG. 8 is a diagram exemplifying a pattern of a mark for measuring alignment accuracy in which a positive / negative is inverted.

FIG. 9 is a diagram showing an example of a second alignment accuracy measurement mark.

FIG. 10 is a diagram illustrating an example of a remaining alignment shift amount and alignment accuracy when a second pattern is formed without correcting the first pattern.

FIG. 11 is a diagram showing an example of a calculation method for calculating data of a correction value used to correct the position and shape of each chip of the first pattern.

FIG. 12 is a diagram illustrating an example of a shift amount and an alignment accuracy when a first pattern is formed by correcting a positional relationship between adjacent chips.

FIG. 13 is a diagram illustrating an example of a shift amount and an alignment accuracy in a case where a second pattern is formed after a first pattern is formed by performing a correction.

FIG. 14 is a diagram showing another example of the arrangement of the alignment accuracy measurement marks.

[Explanation of symbols]

1. First exposure step, 2. First patterning step, 3.
.. A first measurement step, 4 a second exposure step, 5 a second patterning step, 6 a second measurement step, 7 an exposure pattern correction step, 8 a photomask, 30 a semiconductor chip pattern, 31 … Positioning accuracy measurement mark

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/30 522B

Claims (13)

[Claims] 1. A photomask used when a plurality of semiconductor chip patterns are sequentially arranged one by one on a single wafer so as to be adjacent to each other and exposed, and a position between adjacent semiconductor chip patterns is provided. A photomask, wherein a mark for measuring alignment accuracy for measuring a relationship is provided around each of the semiconductor chip patterns. 2. The semiconductor chip pattern according to claim 1, wherein an outer shape of the semiconductor chip pattern is substantially rectangular or substantially square, and at least two alignment accuracy measurement marks are provided for each of four vertexes of the semiconductor chip pattern. The photomask according to claim 1, wherein: 3. The photomask according to claim 1, wherein the exposure of the semiconductor chip pattern is performed by a scanner exposure device. 4. The photomask according to claim 3, wherein the exposure of the semiconductor chip pattern is performed by a stepper exposure device. 5. A semiconductor device formed by arranging a plurality of semiconductor chip patterns one by one on a single wafer so as to be sequentially adjacent to each other, exposing the semiconductor chip patterns, and performing processing based on the semiconductor chip patterns. Wherein at least a part of an alignment accuracy measurement mark capable of measuring a positional relationship between adjacent semiconductor chip patterns on the one wafer is left around each of the semiconductor chip patterns. Semiconductor device. 6. The semiconductor chip pattern, wherein an outer shape is substantially rectangular or substantially square, and at least two alignment accuracy measurement marks are provided at each of four vertexes of the semiconductor chip pattern. 6. The semiconductor device according to claim 5, wherein 7. An exposure method for arranging and exposing a plurality of semiconductor chip patterns one by one on a single wafer so as to be successively adjacent to each other, wherein alignment accuracy measurement is performed around each of the semiconductor chip patterns. A method for exposing a semiconductor chip pattern, comprising the steps of: providing a use mark and measuring a positional relationship between adjacent semiconductor chip patterns. 8. The semiconductor chip pattern according to claim 1, wherein an outer shape of the semiconductor chip pattern is substantially rectangular or substantially square, and at least two alignment accuracy measurement marks are provided for each of four vertexes of the semiconductor chip pattern. 8. The method for exposing a semiconductor chip pattern according to claim 7, wherein: 9. The method according to claim 7, wherein the exposure of the semiconductor chip pattern is performed by a scanner exposure device. 10. Exposure of the semiconductor chip pattern includes:
8. The method according to claim 7, wherein the step is performed by a stepper exposure apparatus. 11. A semiconductor chip pattern exposed after a semiconductor chip pattern whose measurement is performed, based on information on a positional relationship between the semiconductor chip patterns obtained in the step of measuring the positional relationship. 8. The method according to claim 7, further comprising the step of adjusting the shape and / or position of the semiconductor chip pattern. 12. A semiconductor chip on a wafer to be exposed after a wafer whose measurement is performed, based on information on a positional relationship between the semiconductor chip patterns obtained in the step of measuring the positional relationship. 8. The method according to claim 7, further comprising adjusting a shape and / or a position of the pattern. 13. A chip alignment accuracy inspection apparatus used in an exposure process of arranging and exposing a plurality of semiconductor chip patterns one by one sequentially on one wafer and exposing the semiconductor chip pattern, A positioning accuracy measurement mark is provided at a predetermined position around each, and the positional relationship between the positioning accuracy measurement marks between adjacent semiconductor chip patterns is measured, and based on the measurement result,
A chip alignment accuracy inspection apparatus, wherein information on a positional relationship between the adjacent semiconductor chip patterns is grasped.