CN114578662A - Overlay mark - Google Patents
Overlay mark Download PDFInfo
- Publication number
- CN114578662A CN114578662A CN202210185959.1A CN202210185959A CN114578662A CN 114578662 A CN114578662 A CN 114578662A CN 202210185959 A CN202210185959 A CN 202210185959A CN 114578662 A CN114578662 A CN 114578662A
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- CN
- China
- Prior art keywords
- mark
- pattern
- overlay
- measurement
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
- G03F7/7085—Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Epidemiology (AREA)
- Public Health (AREA)
- Health & Medical Sciences (AREA)
- Environmental & Geological Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Multimedia (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention provides an overlay mark, which is formed in a semiconductor substrate and comprises a first measurement mark, a second measurement mark and an auxiliary pattern; a first measurement mark is formed in the first layer; the second measurement mark is formed in a second layer formed at the same position after the first layer; the auxiliary patterns are uniformly distributed around the outer side of the first measurement mark and are located in the same layer as the first measurement mark. According to the invention, the linear pattern auxiliary patterns which are densely and symmetrically distributed are added around the existing overlay mark pattern, so that the problem of inaccurate measurement precision caused by asymmetric overlay marks in the photoetching process is solved, and the measurement precision and the device yield are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an overlay mark.
Background
The photolithography process is a key step in the manufacture of semiconductor integrated circuits, and the overlay accuracy (overlay) of photolithography is one of the key parameters for measuring the photolithography process, and refers to the offset between the upper and lower patterns of a wafer, i.e., the overlay error. Overlay accuracy is typically assessed by measuring the offset between the overlay marks of the upper and lower layers to measure overlay error.
With the increase of the number of stacked layers of circuits in an integrated circuit chip and from the viewpoint of cost reduction, a photoresist with a thickness of more than 3 μm is required to be used when performing a stacking process in a photolithography process, which poses a great challenge to the detection of overlay accuracy.
In the conventional thick photoresist lithography process, the photoresist contains a large amount of solvent due to the non-uniform density of the pattern around the overlay mark, and the gas expands and releases after exposure and baking, so that the profile of the photoresist pattern will incline to one side, as shown in fig. 1, which is a schematic cross-sectional view showing the inclination of the conventional overlay mark pattern, of course, fig. 1 shows only the right-inclined view, and also the inclination in other directions. After the inclination occurs, the profile of the overlay mark is asymmetric, and then the measured position is different from the actual position during overlay measurement, a measurement error is introduced, and the measured data is affected, so that the overlay precision obtained by measurement is inaccurate, and the yield of the device is seriously affected.
Disclosure of Invention
In view of the above, the present invention provides an overlay mark to solve the problem of inaccurate overlay accuracy caused by asymmetric overlay mark profile in the existing process.
The present invention provides an overlay mark formed in a semiconductor substrate, including:
a first measurement mark formed in the first layer;
a second measurement mark formed in a second layer formed at the same position after the first layer; and
and the auxiliary patterns are uniformly distributed around the outer side of the first measuring mark and are positioned on the same layer as the first measuring mark.
Preferably, the pattern of the first measurement mark is a square ring shape.
Preferably, the pattern of the second measurement marks is a square.
Preferably, the square ring pattern of the first measurement mark is larger in area than the block pattern of the second measurement mark.
Preferably, the auxiliary pattern is formed of a densely symmetrically arranged straight line pattern.
Preferably, the auxiliary patterns include four sets of linear patterns, namely two sets of linear patterns in the X direction and two sets of linear patterns in the Y direction.
Preferably, each set of linear patterns comprises a plurality of uniformly distributed parallel linear patterns.
Preferably, the length of the linear pattern in the Y direction is greater than the length of the linear pattern in the X direction.
The laminated mark provided by the invention comprises the first measurement mark and the second measurement mark which are used for measuring the alignment precision, and the auxiliary pattern is arranged outside the first measurement mark, so that the pattern of the laminated mark is more uniform, the influence of the distortion of the patterns of the first measurement mark and the second measurement mark on the measurement precision is avoided, and the measurement precision and the device yield are improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram illustrating a conventional overlay mark pattern being skewed;
FIG. 2 is a schematic diagram of a conventional overlay mark;
FIG. 3 is a schematic diagram of an overlay mark according to an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout this specification, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
Overlay accuracy (OVL) refers to the overlay position accuracy of the current layer pattern and the previous layer pattern in the lithography manufacturing process. Overlay mark (overlay mark) is commonly used to measure the overlay accuracy (overlay) between two layers. Specifically, as shown in fig. 2, a schematic diagram of a conventional overlay mark is shown, which has a square ring-shaped overlay mark pattern 10 and a current layer lithography pattern 20 on a silicon wafer. The overlay mark pattern 10 is formed on the silicon wafer in a previous process, for example, using a photolithography and etching process, to provide an alignment reference for a new layer pattern to be formed. A square ring shape is a typical shape of an overlay mark. This layer of the silicon wafer pattern having the overlay mark pattern 10 is referred to as an alignment layer. The overlay accuracy is measured by measuring the distances a, b, c, d between the current layer lithography pattern 20 and four boundaries inside the overlay mark pattern 10 of the aligned layer, respectively, wherein the offset value of the current layer and the aligned layer in the x-axis direction is (d-c)/2, and the offset value in the y-axis direction is (a-b)/2.
Of course, fig. 2 shows only one of the most common box-in-box type overlay marks, and there are other types of overlay marks, such as bar-in-bar type (bar-in-bar) and Advanced Image Metrology (AIM). The following describes the technical solution of the present invention by using an inner-outer box type (box-in-box) overlay mark shown in fig. 2 as an example and by using a specific embodiment in combination with the accompanying drawings.
FIG. 3 is a schematic diagram of an overlay mark according to an embodiment of the present invention. As shown in fig. 3, the overlay mark according to the embodiment of the present invention includes a first measurement mark 11, a second measurement mark 12, and an auxiliary pattern 13. Specifically, the overlay mark of the embodiment of the present invention is formed in the semiconductor substrate, and the first measurement mark 11 is formed in the first layer. The second measurement mark 12 is formed in a second layer formed at the same position after the first layer. That is, the first measurement mark 11 is a front layer measurement mark in a layer in the semiconductor substrate, and the second measurement mark 12 is a rear layer measurement mark at the same position in a layer subsequent to the layer. The auxiliary patterns 13 are uniformly distributed around the outer side of the first measurement mark 11 at the same layer as the first measurement mark 11. The auxiliary pattern 13 makes the pattern of the overlay mark uniform so that the patterns of the first measurement mark 11 and the second measurement mark 12 are not inclined.
In the embodiment of the present invention, the pattern of the first measurement mark 11 is a square ring shape, and the pattern of the second measurement mark 12 is a square block shape. In other embodiments, the pattern of the first measurement mark and the second measurement mark may be of other pattern types.
In the embodiment of the present invention, the auxiliary patterns 13 are formed by densely and symmetrically distributed linear patterns, and include four groups of linear patterns, which are two groups of linear patterns in the X direction and two groups of linear patterns in the Y direction, respectively, and are distributed in parallel around the outer side of the square ring pattern of the first measurement mark 11, each group of linear patterns includes a plurality of linear patterns uniformly distributed in parallel, here, the dummy pattern may be other pattern designs, and in other embodiments of the present invention, the dummy pattern may also be other shape patterns uniformly distributed in other blank portions, for example, a uniformly distributed square pattern array, and the object of the present invention can also be achieved.
The overlay mark of the embodiment of the invention is based on the technical problems that the pattern density of the existing overlay mark is uneven, a large amount of solvent is contained in a photoresist in the thick photoresist photoetching process, the profile of a photoresist pattern can incline downwards to one side due to gas expansion and release after exposure and baking, the measurement result is further influenced, and the yield of a device is seriously influenced. The laminated mark on the same layer can be formed by the same photoetching and etching process, and no additional step is required to be added in the process. The formation of the corresponding pattern by using the photolithography and etching processes is common knowledge and common means of those skilled in the art, and detailed process procedures thereof will not be described herein.
In summary, the overlay mark provided by the present invention makes the pattern of the overlay mark more uniform, and prevents the patterns of the first measurement mark and the second measurement mark from being tilted. The measurement accuracy and the device yield are improved under the condition of not influencing the existing measurement system.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. An overlay mark formed in a semiconductor substrate, comprising:
a first measurement mark formed in the first layer;
a second measurement mark formed in a second layer formed at the same position after the first layer; and
and the auxiliary patterns are uniformly distributed around the outer side of the first measuring mark and are positioned on the same layer as the first measuring mark.
2. The overlay mark of claim 1 wherein the pattern of the first measurement mark is a square ring.
3. The overlay mark according to claim 1 wherein the pattern of the second measurement mark is in the form of a square.
4. The overlay mark according to claim 2 or 3 wherein the square ring shape of the first measurement mark is larger in area than the square shape of the second measurement mark.
5. The overlay mark according to claim 1 wherein said auxiliary pattern is formed of a densely symmetrically arranged rectilinear pattern.
6. The overlay mark according to claim 5 wherein said auxiliary pattern comprises four sets of linear patterns, respectively two sets of linear patterns in the X direction and two sets of linear patterns in the Y direction.
7. The overlay mark of claim 6 wherein each set of linear patterns comprises a plurality of uniformly distributed parallel linear patterns.
8. The overlay mark according to claim 7 wherein the length of said Y-direction linear pattern is greater than the length of said X-direction linear pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210185959.1A CN114578662A (en) | 2022-02-28 | 2022-02-28 | Overlay mark |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210185959.1A CN114578662A (en) | 2022-02-28 | 2022-02-28 | Overlay mark |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114578662A true CN114578662A (en) | 2022-06-03 |
Family
ID=81776653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210185959.1A Pending CN114578662A (en) | 2022-02-28 | 2022-02-28 | Overlay mark |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114578662A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115586714A (en) * | 2022-12-13 | 2023-01-10 | 合肥新晶集成电路有限公司 | Alignment pattern and measurement method |
| WO2024000635A1 (en) * | 2022-06-30 | 2024-01-04 | 长鑫存储技术有限公司 | Measurement pattern and preparation method therefor, and measurement method |
-
2022
- 2022-02-28 CN CN202210185959.1A patent/CN114578662A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024000635A1 (en) * | 2022-06-30 | 2024-01-04 | 长鑫存储技术有限公司 | Measurement pattern and preparation method therefor, and measurement method |
| CN115586714A (en) * | 2022-12-13 | 2023-01-10 | 合肥新晶集成电路有限公司 | Alignment pattern and measurement method |
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