CN114578662A - Overlay mark - Google Patents

Abstract

The invention provides an overlay mark, which is formed in a semiconductor substrate and comprises a first measurement mark, a second measurement mark and an auxiliary pattern; a first measurement mark is formed in the first layer; the second measurement mark is formed in a second layer formed at the same position after the first layer; the auxiliary patterns are uniformly distributed around the outer side of the first measurement mark and are located in the same layer as the first measurement mark. According to the invention, the linear pattern auxiliary patterns which are densely and symmetrically distributed are added around the existing overlay mark pattern, so that the problem of inaccurate measurement precision caused by asymmetric overlay marks in the photoetching process is solved, and the measurement precision and the device yield are improved.

Description

an engraving mark

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to an overlay mark.

Background technique

The lithography process is a key step in the manufacture of semiconductor integrated circuits. The overlay accuracy of lithography is one of the key parameters to measure the lithography process. It refers to the offset between the upper and lower layers of the wafer. Also called overlay error. Overlay error is usually measured by measuring the offset between the upper and lower overlay marks to evaluate overlay accuracy.

With the increase in the number of superimposed layers of circuits in integrated circuit chips and the consideration of cost reduction, photoresist with a thickness greater than 3 μm needs to be used when performing the superimposition process in the lithography process. a huge challenge.

In the existing thick-resist lithography process, due to the uneven density of the pattern around the overlay mark, and the photoresist contains a large amount of solvent, the gas expands and releases after exposure and baking, causing the outline of the photoresist pattern to move to one side Inclination, as shown in FIG. 1 , is shown as a schematic cross-sectional view of the existing overlay mark pattern being tilted. Of course, what is shown in FIG. 1 is only a schematic diagram of tilting to the right, and there are other directions of tilting. After the inclination occurs, the outline of the overlay mark will be asymmetric, and the measured position during overlay measurement will be different from the actual position, which will introduce measurement errors and affect the measured data, which will result in The overlay accuracy is inaccurate, which seriously affects the yield of the device.

SUMMARY OF THE INVENTION

In view of this, the present invention provides an overlay mark to solve the problem that the outline of the overlay mark is asymmetrical in the prior art process, resulting in inaccurate overlay accuracy.

The present invention provides an overlay mark formed in a semiconductor substrate, comprising:

a first measurement mark formed in the first layer;

a second measurement mark formed in a second layer formed at the same location after the first layer; and

The auxiliary graphics are evenly distributed around the outer side of the first measurement mark, and are located on the same layer as the first measurement mark.

Preferably, the pattern of the first measurement mark is a square ring.

Preferably, the pattern of the second measurement mark is square.

Preferably, the square ring pattern of the first measurement mark has a larger area than the block figure of the second measurement mark.

Preferably, the auxiliary graphics are composed of densely distributed straight-line graphics.

Preferably, the auxiliary graphics include four sets of linear graphics, which are two sets of linear graphics in the X direction and two sets of linear graphics in the Y direction.

Preferably, each group of linear graphics includes a plurality of evenly distributed and parallel linear graphics.

Preferably, the length of the linear pattern in the Y direction is greater than the length of the linear pattern in the X direction.

The laminated mark provided by the present invention not only includes the first measurement mark and the second measurement mark for measuring the overlay accuracy, but also provides auxiliary graphics outside the first measurement mark, so that the graphics of the laminated mark is more uniform and avoids the need for a second measurement mark. The distortion of the patterns of the first measurement mark and the second measurement mark affects the measurement accuracy, thereby improving the measurement accuracy and the device yield.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1 shows the schematic diagram that the existing overlay mark pattern is inclined;

Figure 2 shows a schematic diagram of a conventional overlay mark;

FIG. 3 is a schematic diagram of an overlay mark according to an embodiment of the present invention.

Detailed ways

The present invention is described below based on examples, but the present invention is not limited to these examples only. In the following detailed description of the invention, some specific details are described in detail. The present invention can be fully understood by those skilled in the art without the description of these detailed parts. Well-known methods, procedures, procedures, components and circuits have not been described in detail in order to avoid obscuring the essence of the present invention.

Furthermore, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless clearly required by the context, words such as "including", "comprising" and the like throughout this application should be construed in an inclusive rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

In the description of the present invention, it should be understood that the terms "first", "second" and the like are used for descriptive purposes only, and should not be construed as indicating or implying relative importance. Also, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

Overlay (overlay, OVL) refers to the overlapping position accuracy of the current layer pattern and the previous layer pattern in the photolithography manufacturing process. Generally, overlay marks are used to measure the overlay accuracy between two layers. Specifically, as shown in FIG. 2 , which is a schematic diagram of an existing stack mark, the silicon wafer has a square ring-shaped overlay mark pattern 10 and a current layer lithography pattern 20 . The overlay mark pattern 10 is formed on the silicon wafer in the previous process, such as photolithography and etching, and is used to provide an alignment reference for a new layer pattern to be formed. A square ring is a typical shape of an overlay mark. This layer of silicon wafer pattern with the overlay mark pattern 10 is called the aligned layer. Measuring the overlay accuracy is to measure the distances a, b, c, and d between the lithography pattern 20 of the current layer and the four boundaries inside the overlay mark pattern 10 of the aligned layer, and the offset of the current layer and the aligned layer in the x-axis direction. The shift value is (d-c)/2, and the offset value in the y-axis direction is (a-b)/2.

Of course, what is shown in Figure 2 is just one of the most common box-in-box overlay marks, there are other types of overlay marks, such as bar-in-bar, advanced image measurement Type (advanced imagine mrtology, AIM). Taking the box-in-box engraving mark shown in FIG. 2 as an example below, the technical solutions of the present invention will be further described with reference to the accompanying drawings and through specific embodiments.

FIG. 3 is a schematic diagram of an overlay mark according to an embodiment of the present invention. As shown in FIG. 3 , the overlay mark according to the embodiment of the present invention includes a first measurement mark 11 , a second measurement mark 12 and an auxiliary graphic 13 . Specifically, the overlay mark of the embodiment of the present invention is formed in the semiconductor substrate, and the first measurement mark 11 is formed in the first layer. The second measurement mark 12 is formed in a second layer formed at the same position after the first layer. That is, the first measurement mark 11 is a front layer measurement mark in a certain layer in the semiconductor substrate, and the second measurement mark 12 is a rear layer measurement mark at the same position in a layer after the layer. The auxiliary patterns 13 are evenly distributed around the outer side of the first measurement mark 11 , and are located on the same layer as the first measurement mark 11 . The auxiliary pattern 13 makes the pattern of the stacked marks uniform, so that the patterns of the first measurement mark 11 and the second measurement mark 12 are not inclined.

In the embodiment of the present invention, the pattern of the first measurement mark 11 is a square ring, and the pattern of the second measurement mark 12 is a square shape. In other embodiments, the patterns of the first measurement mark and the second measurement mark may also be of other pattern types.

In the embodiment of the present invention, the auxiliary graphics 13 are composed of densely distributed linear graphics, including four sets of linear graphics, which are respectively two sets of linear graphics in the X direction and two sets of linear graphics in the Y direction, which are distributed parallel to the first Around the outer side of the square annular figure of the measurement mark 11, each group of linear figures includes a plurality of evenly distributed and parallel linear figures. Here, the dummy pattern can be other pattern designs. In other embodiments of the present invention, the dummy pattern Other shapes of patterns evenly distributed in other blank parts, such as a uniformly distributed square pattern array, can also achieve the purpose of the present invention.

The overlay mark of the embodiment of the present invention is based on the pattern of the existing stack mark. Due to the uneven pattern density, the photoresist contains a large amount of solvent during the thick-resist lithography process. After exposure and baking, the gas expands and releases, resulting in the photoresist. The outline of the pattern will be inclined to one side, which will affect the measurement results and seriously affect the technical problem of the yield of the device. The existing overlay marks are improved by adding dense symmetry around the existing overlay marks. The distributed straight-line graphic auxiliary graphic method avoids the pattern of the first measurement mark and the second measurement mark from being inclined, and the existing overlay marks are not changed, and the existing measurement system will not be affected. The stacked marks on the same layer can be formed by the same photolithography and etching process, and no additional steps are required in the process. It is common knowledge and common means for those skilled in the art to form corresponding patterns by photolithography and etching processes, and the detailed process is not repeated here.

To sum up, the laminated mark provided by the present invention makes the pattern of the laminated mark more uniform, and avoids the pattern of the first measurement mark and the second measurement mark from being inclined. Improved measurement accuracy and device yield without affecting existing measurement systems.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. An overlay mark formed in a semiconductor substrate, comprising:

a first measurement mark formed in the first layer;

a second measurement mark formed in a second layer formed at the same position after the first layer; and

and the auxiliary patterns are uniformly distributed around the outer side of the first measuring mark and are positioned on the same layer as the first measuring mark.

2. The overlay mark of claim 1 wherein the pattern of the first measurement mark is a square ring.

3. The overlay mark according to claim 1 wherein the pattern of the second measurement mark is in the form of a square.

4. The overlay mark according to claim 2 or 3 wherein the square ring shape of the first measurement mark is larger in area than the square shape of the second measurement mark.

5. The overlay mark according to claim 1 wherein said auxiliary pattern is formed of a densely symmetrically arranged rectilinear pattern.

6. The overlay mark according to claim 5 wherein said auxiliary pattern comprises four sets of linear patterns, respectively two sets of linear patterns in the X direction and two sets of linear patterns in the Y direction.

7. The overlay mark of claim 6 wherein each set of linear patterns comprises a plurality of uniformly distributed parallel linear patterns.

8. The overlay mark according to claim 7 wherein the length of said Y-direction linear pattern is greater than the length of said X-direction linear pattern.

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