WO2024000635A1

WO2024000635A1 - Measurement pattern and preparation method therefor, and measurement method

Info

Publication number: WO2024000635A1
Application number: PCT/CN2022/104882
Authority: WO
Inventors: 邱少稳
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-06-30
Filing date: 2022-07-11
Publication date: 2024-01-04
Also published as: CN117369215A

Abstract

A semiconductor measurement accuracy monitoring method and apparatus, and a device and a medium. A measurement pattern comprises a target layer, and a first measurement mark pattern (11), a second measurement mark pattern (21), a plurality of first auxiliary mark patterns (12) and a plurality of second auxiliary mark patterns (21), which are located in different regions on the target layer, wherein the first measurement mark pattern (11) comprises a plurality of first mark units (111), which are distributed in an array, and the first mark units (111) have a first preset parameter, which comprises a first preset etch offset; and the second measurement mark pattern (21) comprises a plurality of second mark units (211), which are distributed in an array, and the second mark units (211) have a second preset parameter, which comprises a second preset etch offset. The semiconductor measurement accuracy monitoring apparatus can quickly and accurately measure an etch offset, due to a single etching process, of a semiconductor structure, which is acquired after execution of the etching process multiple times.

Description

Measurement patterns and preparation methods and measurement methods

Cross-references to related applications

This disclosure requires the priority of the Chinese patent application submitted to the China Patent Office on June 30, 2022, with the application number 202210761136.9 and the application name "Measurement Patterns and Preparation Methods, Measurement Methods, Devices, Equipment and Media", The entire contents of said patent application are incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the field of semiconductor technology, and in particular to a measurement pattern, a preparation method thereof, and a measurement method.

Background technique

With the rapid development of integrated circuit manufacturing processes, the market has increasingly higher requirements for the performance and quality of semiconductor products. Semiconductor etching is a very important process step in the semiconductor manufacturing process. Etching is mainly a process of patterning semiconductor structures based on patterned masks. Environmental errors or manual errors will inevitably be introduced during the actual etching process, resulting in There is a difference between the pattern on the patterned mask or the designed pattern and the actual etched pattern.

However, as semiconductor devices continue to shrink, research on the structural differences of semiconductor devices before and after etching becomes more and more in-depth, and measurement accuracy requirements are becoming higher and higher. For semiconductor structures obtained through multiple etching processes, traditional offset measurement technology can generally only measure the overall offset of the semiconductor structure caused by etching, and it is difficult to quickly and accurately measure each time. The etching offset actually produced by the etching process. Therefore, the relevant parameters of the etching machine or the etching process cannot be accurately fed back and adjusted based on the etching offset obtained by measurement.

Contents of the invention

According to various embodiments of the present disclosure, a measurement pattern, a preparation method thereof, and a measurement method are provided.

According to some embodiments, the first aspect of the present disclosure provides a measurement pattern, including a target layer and a first measurement mark pattern, a second measurement mark pattern, and a plurality of first auxiliary mark patterns located in different areas on the target layer. and several second auxiliary mark patterns; the first measurement mark pattern includes a plurality of first mark units distributed in an array, and the first mark unit has a first preset parameter including a first preset etching offset; the second The measurement mark pattern includes a plurality of second mark units distributed in an array, and the second mark units have second preset parameters including a second preset etching offset.

According to some embodiments, the first auxiliary mark pattern, the second auxiliary mark pattern, the first measurement mark pattern and the second measurement mark pattern are located on the same layer.

According to some embodiments, the first measurement mark pattern and the second measurement mark pattern are located in the middle cutting lane area of the target layer; the first auxiliary mark pattern and the second auxiliary mark pattern are located in the edge cutting lane area of the target layer, and Surround the first measurement mark pattern and the second measurement mark pattern.

According to some embodiments, the first auxiliary mark pattern and the first measurement mark pattern are located on the same layer; the second auxiliary mark pattern and the second measurement mark pattern are located on the same layer; wherein the first auxiliary mark pattern and the second auxiliary mark pattern are Located on different floors.

According to some embodiments, the first auxiliary mark pattern has a third preset etching offset, and the third preset etching offset is associated with at least part of the first preset parameters; the second auxiliary mark pattern has a fourth preset The etching offset, the fourth preset etching offset is associated with at least part of the second preset parameters.

According to some embodiments, the first marking unit includes a first alignment mark located on the target layer and a second alignment mark located on the front layer of the target layer, for determining based on the asymmetry of the light intensity distribution of the zero-order diffracted light. Real-time etch offset of the first alignment mark and the second alignment mark.

According to some embodiments, the second marking unit includes a third alignment mark located on the target layer and a fourth alignment mark located on the target layer, for determining the third alignment mark according to the asymmetry of the light intensity distribution of the zero-order diffracted light. Real-time etch offset of the third and fourth alignment marks.

According to some embodiments, any one of the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark includes at least one of a gap, a void, and a bump.

According to some embodiments, the real-time etching offset includes an offset direction and an offset distance in the offset direction.

According to some embodiments, a second aspect of the present disclosure provides a measurement pattern preparation method, including: providing a wafer; performing a preset first etching process to transfer a first etching pattern to a target layer on the wafer, and A first measurement mark pattern and a plurality of first auxiliary mark patterns are formed at different positions in the cutting lane of the layer; the first measurement mark pattern includes a plurality of first mark units distributed in an array, and the first mark unit has a first preset marking unit. the first preset parameter of the etching offset; execute the preset second etching process to transfer the second etching pattern to the target layer, and form a second measurement mark pattern and a plurality of second etching marks at different positions in the cutting lane of the target layer. The auxiliary mark pattern; the second measurement mark pattern includes a plurality of second mark units distributed in an array, and the second mark units have second preset parameters including a second preset etching offset.

According to some embodiments, the first auxiliary mark pattern, the second auxiliary mark pattern, the first measurement mark pattern and the second measurement mark pattern are located on the same layer; or the first auxiliary mark pattern and the first measurement mark pattern are located on the same layer. , the second auxiliary mark pattern and the second measurement mark pattern are located on the same layer, and the first auxiliary mark pattern and the second auxiliary mark pattern are located on different layers.

According to some embodiments, a third aspect of the present disclosure provides a measurement method, which is implemented after the measurement pattern preparation method in any of the above embodiments is executed to form a measurement pattern. The measurement method includes: a real measurement based on the first auxiliary mark pattern. The etching offset and its correlation with the first measurement mark pattern are used to calculate the first etching offset caused by etching the first etching pattern; the real-time etching offset based on the second auxiliary mark pattern and Its correlation with the second measurement mark pattern is used to calculate the second etching offset caused by etching the second etching pattern.

According to some embodiments, the first preset parameter includes a first etching calibration equation associated with a real-time etching offset of the first auxiliary mark pattern; based on the real-time etching offset of the first auxiliary mark pattern and its relationship with The correlation between the first measurement mark pattern and the calculation of the first etching offset caused by etching the first etching pattern include: obtaining the first etching calibration equation, and measuring based on the optical diffraction principle including the first auxiliary First spot offset data of the real-time etching offset of the mark pattern; calculate the first etching offset caused by etching the first etching pattern according to the first light spot offset data and the first etching calibration equation.

According to some embodiments, the second preset parameter includes a second etching calibration equation associated with the real-time etching offset of the second auxiliary mark pattern; based on the real-time etching offset of the second auxiliary mark pattern and its relationship with The second measurement relates to the mark pattern, and calculates the second etching offset caused by etching the second etching pattern, including: obtaining the second etching calibration equation, and measuring based on the optical diffraction principle including the second auxiliary Second light spot offset data of the real-time etching offset of the mark pattern; calculate the second etching offset caused by etching the second etching pattern according to the second light spot offset data and the second etching calibration equation.

According to some embodiments, obtaining the first etching calibration quantity equation includes: taking the actual spot offset data of the plurality of first mark units as input samples, and taking the corresponding first preset etching offset as the output sample, Perform data fitting to obtain the first etching calibration equation.

According to some embodiments, obtaining the second etching calibration quantity equation includes: using actual spot offset data of a plurality of second mark units as input samples, and using the corresponding second preset etching offset amounts as output samples, Perform data fitting.

Embodiments of the present disclosure may/at least have the following advantages:

In the measurement patterns, preparation methods, and measurement methods provided by embodiments of the present disclosure, the first etching pattern is transferred to the target layer on the wafer, and the first measurement marks are formed at different positions in the cutting lanes of the target layer. After the pattern and several first auxiliary mark patterns, the first auxiliary mark pattern can be measured based on the principle of optical diffraction to obtain the first spot offset data, and the first etching calibration equation of the first measurement mark pattern can be obtained; according to the second A spot offset data and a first etching calibration equation calculate the first etching offset caused by etching the first etching pattern; by transferring the second etching pattern to the target layer on the wafer, and on the target layer After the second measurement mark pattern and several second auxiliary mark patterns are formed at different positions in the cutting lane, the second auxiliary mark pattern is measured based on the principle of optical diffraction to obtain the second spot offset data, and the second measurement mark pattern is obtained. The second etching calibration amount equation; calculates the second etching offset amount caused by etching the second etching pattern according to the second spot offset data and the second etching calibration amount equation. Embodiments of the present disclosure can quickly and accurately measure the etching offset of a semiconductor structure caused by a single etching process after performing multiple etching processes, and can accurately feedback and adjust the etching machine and equipment based on the etching offset. / Or corresponding to the relevant parameters of the etching process, improve the etching accuracy and efficiency of the etching machine and / or the corresponding etching process, and improve the yield and reliability of the manufactured semiconductor products.

In summary, the measurement pattern, preparation method, and measurement method provided by the embodiments of the present disclosure can quickly and accurately measure the etching offset of the semiconductor structure caused by a single etching process after performing multiple etching processes. It can accurately feedback and adjust the relevant parameters of the etching machine and/or the corresponding etching process according to the etching offset, improve the etching accuracy and efficiency of the etching machine and/or the corresponding etching process, and improve the manufacturing process. Yield and reliability of semiconductor products.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly illustrate the technical solutions in the technology of the embodiments of the present disclosure, the drawings needed to be used in the technical description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some implementations of the disclosure. For example, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1a is a schematic top view of a semiconductor structure provided with an aperture layer with openings;

Figure 1b is a schematic top view of the alignment pattern generated using IBO measurement;

Figure 1c is a schematic diagram of using IBO measurement to obtain the recognition image including the alignment pattern image in Figure 1b;

Figure 1d is a schematic diagram of the center point offset image obtained based on the recognition image shown in Figure 1c;

Figure 1e is a schematic diagram of an SEM scanning image obtained by scanning the structure shown in Figure 1a;

Figure 2 is a schematic diagram of an application scenario of measurement graphics in an embodiment of the present disclosure;

Figure 3a is a schematic diagram of the first measurement mark pattern in Figure 2;

Figure 3b is a schematic diagram of the second measurement mark pattern in Figure 2;

Figure 4 is a schematic cross-sectional structural diagram of the first marking unit with the identification value "0.0" in Figure 3a;

Figure 5a is a schematic cross-sectional structural diagram of the first marking unit with the identification value "5.0" in Figure 3a;

Figure 5b is a schematic diagram of the light spot offset image in the first light spot offset data of the first marking unit in Figure 3a;

6 is a schematic top view of the real-time measurement map of the first measurement mark pattern in an embodiment of the present disclosure;

Figure 7 is a schematic diagram of the fitting curve corresponding to the first etching calibration quantity equation in an embodiment of the present disclosure;

Figure 8 is a schematic flow chart of a measurement pattern preparation method in an embodiment of the present disclosure;

FIG. 9 is a schematic flowchart of a measurement method according to an embodiment of the present disclosure.

Detailed ways

To facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the accompanying drawings. However, the present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough understanding of the disclosure will be provided.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Where "includes," "has," and "includes" are used herein, another component may also be added unless an explicit qualifying term is used, such as "only," "consisting of," etc. . Unless mentioned to the contrary, terms in the singular may include the plural and shall not be construed as being one in number.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the disclosure.

The development of semiconductor technology is usually limited to the development of photolithography technology. Photolithography technology is a process of transferring mask patterns to wafers through a series of steps such as alignment and exposure. The reduction of feature size poses challenges to the overlay accuracy. More stringent requirements. If the overlay error (Overlay) between different layers on the semiconductor structure does not meet the requirements of the design criteria, it will cause the failure of the front-end device function and the back-end wiring function, directly causing the loss of product yield.

Overlay errors can generally be measured through image recognition-based measurement technology (Image Based Overlay, IBO), scanning electron microscope (Scanning Electron Microscope, SEM), and new diffraction measurement technology (In Die Metrology, IDM). Generally, it can be divided into After Development Inspection (ADI) and After Etching Inspection (AEI). Post-development inspection is generally used to detect the performance indicators of exposure machines and developing machines. After exposure and development are completed, through ADI qualitatively checks the generated pattern to determine whether the pattern is normal. Since it cannot be measured by transmitted light, ADI generally measures it through electron beam or scanning electron microscope. Post-etching detection generally refers to the critical dimensions after etching. Dimension, CD) measurement, conduct full inspection or sampling inspection on the product before and after the photoresist removal in the etching process.

As shown in Figure 1a, for an aperture layer with openings in a semiconductor structure, an alignment pattern as shown in Figure 1b can be produced during the development process, and the IBO measurement is used to obtain an identification image as shown in Figure 1c. The alignment pattern includes a first grid pattern 301 arranged in a fan-like manner on the inside and a second grid pattern 302 arranged in a fan-like shape around the outside, wherein the first grid pattern can be provided The pattern 301 is located on the current layer, and the second grating pattern 302 is located on the front layer; according to the recognition image shown in Figure 1c, the offset between the center point p of the alignment pattern image of the front layer and the center point q of the alignment pattern image of the current layer is obtained. The moving direction and the offset distance in the offset direction (as shown in Figure 1d). Although IBO measurement technology can be used to roughly measure the overall overlay error of the aperture layer with openings, the measurement speed is slow and the accuracy is low. Generally, it takes 1.5 hours to detect a single wafer; For the hole layer obtained by the hole etching process, it is impossible to distinguish the overlay error caused by a single hole etching process. The SEM measurement technology is used to measure the semiconductor structure including the opening layer as shown in Figure 1a to obtain the SEM scan image as shown in Figure 1e. Based on the SEM scan image, no effective overlay error can be obtained. Therefore, the SEM measurement technology cannot measure the semiconductor structure. Measure the overlay error of the semiconductor structure including the opening layer.

The present disclosure aims to provide a measurement pattern and its preparation method, measurement method, device, equipment and medium, which can quickly and accurately measure the etching caused by a single etching process of a semiconductor structure after performing multiple etching processes. The offset can accurately feedback and adjust the relevant parameters of the etching machine and/or the corresponding etching process according to the etching offset, thereby improving the etching accuracy and efficiency of the etching machine and/or the corresponding etching process. And improve the yield and reliability of semiconductor products.

Please refer to Figures 2-3b. In some embodiments of the present disclosure, a measurement pattern is provided, including a target layer and a first measurement mark pattern 11 and a second measurement mark pattern located in different areas on the target layer. 21. A plurality of first auxiliary mark patterns 12 and a plurality of second auxiliary mark patterns 22; the first measurement mark pattern 11 includes a plurality of first mark units 111 distributed in an array, and the first mark unit 111 has a first preset The first preset parameter of the etching offset; the second measurement mark pattern 21 includes a plurality of second mark units 211 distributed in an array, and the second mark unit 211 has a second preset etching offset. Preset parameters.

As an example, please continue to refer to Figure 2. The first auxiliary mark pattern 12, the second auxiliary mark pattern 22, the first measurement mark pattern 11 and the second measurement mark pattern 21 are located in different areas of the same layer. The first auxiliary mark pattern 12. The orthographic projections of any two of the second auxiliary mark pattern 22, the first measurement mark pattern 11 and the second measurement mark pattern 21 on the upper surface of the target layer do not overlap. The first measurement mark graphics 11 and the second measurement mark graphics 21 can be set to be located in the middle cutting lane area of the target layer, and the first auxiliary mark graphics 12 and the second auxiliary mark graphics 22 are located in the edge cutting lane area of the target layer, And surround the first measurement mark pattern 11 and the second measurement mark pattern 21 to meet the actual needs of different application scenarios.

As an example, please continue to refer to Figure 2. The first auxiliary mark pattern 12 and the first measurement mark pattern 11 are located on the same layer; the second auxiliary mark pattern 22 and the second measurement mark pattern 21 are located on the same layer; wherein, the first auxiliary mark pattern 22 and the second measurement mark pattern 21 are located on the same layer. The mark pattern 12 and the second auxiliary mark pattern 22 are located on different layers.

As an example, please continue to refer to Figures 2 to 3b. The first auxiliary mark pattern 12 has a third preset etching offset, and the third preset etching offset is at least associated with part of the first preset parameters; the second The auxiliary mark pattern 22 has a fourth preset etching offset, and the fourth preset etching offset is associated with at least part of the second preset parameters.

As an example, please refer to FIG. 4 , the first marking unit 111 includes a first alignment mark 31 located on the target layer and a second alignment mark 32 located on the front layer of the target layer, for light intensity according to the zero-order diffracted light. The asymmetry of the distribution determines the real-time etching offset of the first alignment mark 31 and the second alignment mark 32 .

As an example, the second marking unit includes a third alignment mark located on the target layer and a fourth alignment mark located on the target layer, for determining the third pair according to the asymmetry of the light intensity distribution of the zero-order diffracted light. Real-time etching offset of the alignment mark and the fourth alignment mark.

As an example, any one of the first alignment mark, the second alignment mark, the third alignment mark and the fourth alignment mark includes at least one of a gap, a cavity and a bump.

As an example, please continue to refer to Figures 3a-3b. The number marked on each first mark unit 111 in the array area of the first measurement mark pattern 11 represents the offset data corresponding to the first preset etching offset. Each first marking unit 111 may also be marked with a corresponding offset direction (not shown). The number marked on each second mark unit 211 in the array area of the second measurement mark pattern 21 represents the offset data corresponding to the second preset etching offset. Each second mark unit 211 may also be marked with The corresponding offset direction (not shown).

As an example, please refer to FIG. 4 , each first marking unit 111 may include a first alignment mark 31 located on the target layer and a second alignment mark 32 located on the front layer of the target layer, which may be based on the zero-order diffracted light. The asymmetry of the light intensity distribution determines the real-time etching offset of the first alignment mark 31 and the second alignment mark 32 . The cross-sectional view of the first alignment mark 31 and the second alignment mark 32 in the mark unit marked with the number "0.0" in Figure 3a or Figure 3b can refer to Figure 4 to illustrate the first alignment mark 31 and the second alignment mark The first preset etching offset between 32 and 32 is 0. The cross-sectional view of the first alignment mark 31 and the second alignment mark 32 in the mark unit marked with the number "5.0" in Figure 3a or Figure 3b can be referred to Figure 5a to illustrate the first alignment mark 31 and the second alignment mark The offset distance of the first preset etching offset between 32 is 5.0. The arrow in Figure 5b indicates the offset direction of the second alignment mark 32 relative to the first alignment mark 31. Figure 5b illustrates the offset direction of the second alignment mark 32 relative to the first alignment mark 31. The spot shift image in the spot shift data acquired in 5a. Picture a in Figure 5b shows that the etching offset is zero, and picture b in Figure 5b shows that when the layer (strip-shaped vertical pattern) has an etching offset in the direction shown by the arrow relative to the previous layer (elliptical inclined pattern).

As an example, various forms of scatterometers in the field of lithography are used to guide a radiation beam onto a target and measure the spot shift data of the scattered radiation. For example, the intensity related to the wavelength, the intensity related to the reflection can be measured at a single reflection angle. One or more data such as the intensity associated with the angle and the polarization associated with the reflection angle. Thus, "spot offset data" is obtained, and based on the "spot offset data", the properties of interest of the target can be determined. Determination of the properties of interest can be performed by various techniques: for example by iterative methods to reconstruct the target structure, one or more of rigorous coupled wave analysis or finite element methods, library searches, and principal component analysis.

As an example, a scatterometer can be used to measure the beam to generate a larger light spot than the first alignment mark 31 and the second alignment mark 32 in FIGS. 4-5a, or the first alignment mark 31 and the second alignment mark 32 can be The size is set smaller than the measurement spot, which can block the specular reflection corresponding to the high-order diffracted light, and only the zero-order diffracted light is processed. The zeroth order (0th) diffracted light of each first mark unit on the etched wafer is obtained by changing the illumination mode and/or imaging mode, and is generated by using a coherent beam to illuminate the first alignment mark 31 and the second alignment mark 32 The diffraction signal is used to obtain an interference pattern based on the diffraction signal, and the real-time overlay error between the first alignment mark 31 and the second alignment mark 32 is determined based on the interference pattern.

Similarly, the second marking unit includes a third alignment mark located on the target layer and a fourth alignment mark located on the target layer, for determining the third pair according to the asymmetry of the light intensity distribution of the zero-order diffracted light. Real-time etching offset of the alignment mark and the fourth alignment mark.

As an example, any one of the first alignment mark, the second alignment mark, the third alignment mark and the fourth alignment mark includes at least one of a gap, a cavity and a bump to meet the actual needs of a variety of different application scenarios. need.

Those skilled in the art know that the embodiments of the present disclosure are intended to illustrate the implementation principle of the present disclosure, and the first alignment mark, the second alignment mark, the third alignment mark and the fourth alignment mark can be determined according to the actual needs of the specific application scenario. Align the shape and position of any of the marks.

As an example, please continue to refer to FIG. 2 , the first auxiliary mark pattern 12 can be set to have a third preset etching offset, such as a preset zero offset, so that the real-time offset obtained according to the measurement of the first auxiliary mark pattern 12 The displacement data has the same measurement standard as the actual displacement of each first mark unit in the first measurement mark pattern 11 . The second auxiliary mark pattern 22 can be set to have a fourth preset etching offset, such as a preset zero offset, so that the real-time offset data measured according to the second auxiliary mark pattern 22 is consistent with the second measurement mark. The actual offsets generated by each second marking unit in the graph 21 have the same measurement standard.

As an example, please refer to Figures 3a and 4-6 to perform real-time etching between the first alignment mark 31 and the second alignment mark 32 on each first mark unit in the pattern array area shown in Figure 3a Offset creates an offset map of the wafer. For example, a real-time measurement map of the wafer can be established based on the real-time etching offset between the first alignment mark 31 and the second alignment mark 32 (as shown in FIG. 6 ), and the wafer is displayed on the real-time measurement map. The offset vector in the real-time measurement data obtained through the first measurement mark pattern 11 at different positions on the screen. The offset vector includes the offset direction (shown by the arrow in Figure 6 ) and the offset distance in the offset direction (Figure 6 (not shown); in Figure 6, the ox direction can be set to represent the length direction of the wafer surface to be measured, the oy direction represents the width direction of the wafer surface to be measured, and different first measurement marks 11 on the first measurement mark pattern 11 can be set along the ox direction. The real-time etching offset at the corresponding position of the mark unit is displayed at the corresponding position on the surface of the wafer to be measured; similarly, the real-time etching offset at the corresponding position of the different first mark units on the first measurement mark pattern 11 is displayed along the oy direction. The displacement is displayed at the corresponding position on the surface of the wafer to be tested. You can use an optical diffraction IDM (In Device Measure) machine to measure the real-time etching offset after etching, accurately compensate for the real-time etching offset, and eliminate the influence of NZO (None Zero offset). The asymmetric signal of the 0th order diffracted light can be collected through the first measurement mark pattern to obtain the actual spot shift data of each area.

As an example, the second marking unit may be configured to include a third alignment mark located on the target layer and a fourth alignment mark located on the target layer, for determining the third alignment mark based on the asymmetry of the light intensity distribution of the zero-order diffracted light. Real-time etch offset of the third and fourth alignment marks. For specific implementation methods, please refer to the previous discussion on the first marking unit, and will not be described again here.

As an example, after transferring the first etching pattern to the target layer on the wafer to be measured, and forming the first measurement mark pattern and several first auxiliary mark patterns at different positions in the cutting lane of the target layer, based on optical The first auxiliary mark pattern is measured using the diffraction principle to obtain the first light spot offset data, and the first etching calibration quantity equation of the first measurement mark pattern is obtained; according to the first light spot offset data, the first etching calibration quantity The equation calculates the first etching offset caused by etching the first etching pattern; by transferring the second etching pattern to the target layer on the wafer, and forming a second measurement mark pattern at different positions within the dicing lanes of the target layer and several second auxiliary mark patterns, measure the second auxiliary mark pattern based on the principle of optical diffraction to obtain the second light spot offset data, and obtain the second etching calibration equation of the second measurement mark pattern; according to the second light spot The offset data and the second etching calibration equation calculate the second etching offset caused by etching the second etching pattern.

As an example, please refer to Figure 6, using the actual spot offset data of multiple first marking units as the input sample, and using the corresponding first preset etching offset as the output sample, perform data fitting, and obtain the first The first etching calibration quantity equation for measuring the mark pattern. For example, the actual spot offset data corresponding to a single data point in the input sample can be taken as m, and the first preset etching offset amount of the corresponding position data point in the output sample can be taken as n, to obtain the first measurement mark pattern. The data points (m, n) corresponding to each first marking unit are displayed in the omn coordinate system to obtain discrete points as shown in Figure 7. The figure is obtained through the fitting algorithm. The first etching calibration quantity equation corresponding to the discrete point in 7.

As an example, the actual spot offset data of multiple second marking units are used as input samples, and the corresponding second preset etching offsets are used as output samples. Data fitting is performed to obtain the second etching calibration equation. . For example, the actual spot offset data corresponding to a single data point in the input sample can be taken as m, and the first preset etching offset amount of the corresponding position data point in the output sample can be taken as n, to obtain the second measurement mark pattern. The data points (m, n) corresponding to each second marking unit are displayed in the omn coordinate system to obtain the corresponding discrete point distribution map, and the discrete point correspondence is obtained through the fitting algorithm. The second etching calibration quantity equation.

Although IDM is generally used for post-etching inspection and does not require setting specific measurement marks. Instead, it uses the original pattern of the semiconductor structure to measure the overlay error. However, IDM relies on the intensity of the zero-order diffracted light. Asymmetry is measured. For an aperture layer with openings in a semiconductor structure, there is no asymmetry in the light intensity distribution of the zero-order diffracted light after passing through the original pattern of the current layer and the original pattern of the previous layer. cannot be measured effectively. The embodiment of the present disclosure creatively proposes to measure the first auxiliary mark pattern located in the cutting lane based on the principle of optical diffraction to obtain the first spot offset data, and obtain the first etching calibration equation of the first measurement mark pattern. According to the first The light spot offset data and the first etching calibration equation calculate the first etching offset caused by etching the first etching pattern; the second auxiliary mark pattern is measured based on the principle of optical diffraction to obtain the second light spot offset data, and Obtain the second etching calibration quantity equation of the second measurement mark pattern; calculate the second etching offset caused by etching the second etching pattern according to the second spot offset data and the second etching calibration quantity equation. . The auxiliary mark pattern in the adjacent area within the opening layer cutting track is used to obtain the spot offset data, and the etching calibration equation of the measurement mark pattern of the layer is substituted to obtain the corresponding etching offset amount, which solves the problem that traditional technology cannot effectively measure Technical problem of measuring the etching offset of the hole layer. Embodiments of the present disclosure can also quickly and accurately measure the etching offset of the semiconductor structure caused by a single etching process after performing multiple etching processes, and can accurately feedback and adjust the etching machine based on the etching offset. and/or related parameters of the corresponding etching process, to improve the etching accuracy and efficiency of the etching machine and/or the corresponding etching process, and to improve the yield and reliability of the semiconductor products produced.

Referring to Figure 8, in some embodiments, a measurement pattern preparation method is provided, including the following steps:

Step S110: Provide a wafer; perform a preset first etching process to transfer a first etching pattern to the target layer on the wafer, and form a first measurement mark pattern and a plurality of first auxiliaries at different positions in the cutting lane of the target layer Mark pattern; the first measurement mark pattern includes a plurality of first mark units distributed in an array, and the first mark units have first preset parameters including a first preset etching offset;

Step S120: Execute a preset second etching process to transfer the second etching pattern to the target layer, and form a second measurement mark pattern and a plurality of second auxiliary mark patterns at different positions in the cutting lane of the target layer; second measurement The mark pattern includes a plurality of second mark units distributed in an array, and the second mark units have second preset parameters including a second preset etching offset.

As an example, the semiconductor structure shown in Figure 2 is obtained. The first auxiliary mark pattern 12 and the first measurement mark pattern 11 are located at different positions in the cutting lane 101 of the target layer of the wafer to be measured; the first measurement mark pattern 11 includes A plurality of first marking units 111 distributed in an array. The first marking units 111 have a first preset etching offset. Different first marking units can correspond to different areas on the target layer of the wafer to be tested; a second auxiliary marking pattern 22. When the layer measurement mark pattern 21 is located at different positions in the target layer cutting lane 101 of the wafer to be measured; the second measurement mark pattern 21 includes a plurality of second mark units 211 distributed in an array, and the second mark unit 211 has a third With two preset etching offsets, different second marking units can correspond to different areas on the target layer.

As an example, please continue to refer to FIG. 2 , the first auxiliary mark pattern 12 can be set to have a preset zero offset, so that the real-time offset data measured according to the first auxiliary mark pattern 12 is consistent with the first measurement mark pattern 11 The actual offsets generated by each first marking unit have the same measurement standard. The second auxiliary mark pattern 22 can be set to have a preset zero offset, so that the real-time offset data measured and obtained according to the second auxiliary mark pattern 22 is consistent with the actual offset generated by each second mark unit in the second measurement mark pattern 21. The offsets have the same measurement base.

By transferring the first etching pattern to the target layer on the wafer to be measured, and forming the first measurement mark pattern and several first auxiliary mark patterns at different positions in the cutting lane of the target layer, the measured result is measured based on the principle of optical diffraction. The first auxiliary mark pattern obtains the first light spot offset data, and obtains the first etching calibration quantity equation of the first measurement mark pattern; calculates the etching number based on the first light spot offset data and the first etching calibration quantity equation. The first etching offset caused by the etching pattern; by transferring the second etching pattern to the target layer on the wafer, and forming a second measurement mark pattern and several second measurement marks at different positions in the cutting lane of the target layer. After the auxiliary mark pattern, the second auxiliary mark pattern is measured based on the optical diffraction principle to obtain the second light spot offset data, and the second etching calibration equation of the second measurement mark pattern is obtained; according to the second light spot offset data, the second The second etching calibration quantity equation calculates the second etching offset caused by etching the second etching pattern. Embodiments of the present disclosure can quickly and accurately measure the etching offset of a semiconductor structure caused by a single etching process after performing multiple etching processes, and can accurately feedback and adjust the etching machine and equipment based on the etching offset. / Or corresponding to the relevant parameters of the etching process, improve the etching accuracy and efficiency of the etching machine and / or the corresponding etching process, and improve the yield and reliability of the manufactured semiconductor products.

Please refer to Figure 9. In some embodiments, a measurement method is provided, which is implemented after the measurement pattern preparation method in any of the above embodiments is performed to form a measurement pattern. The measurement method includes the following steps:

Step S210: Calculate the first etching offset caused by etching the first etching pattern based on the real-time etching offset of the first auxiliary mark pattern and its correlation with the first measurement mark pattern;

Step S220: Calculate the second etching offset caused by etching the second etching pattern based on the real-time etching offset of the second auxiliary mark pattern and its correlation with the second measurement mark pattern.

As an example, the first preset parameter includes a first etching calibration quantity equation associated with the real-time etching offset of the first auxiliary mark pattern; step S210 includes: obtaining the first etching calibration quantity equation, and based on optical diffraction The principle is to measure the first light spot offset data including the real-time etching offset of the first auxiliary mark pattern; calculate the first light spot offset data caused by etching the first etching pattern according to the first light spot offset data and the first etching calibration equation. An etch offset.

As an example, the second preset parameter includes a second etching calibration quantity equation associated with the real-time etching offset of the second auxiliary mark pattern; step S220 includes: obtaining the second etching calibration quantity equation, and based on optical diffraction The principle is to measure the second light spot offset data including the real-time etching offset of the second auxiliary mark pattern; calculate the second light spot offset data caused by etching the second etching pattern according to the second light spot offset data and the second etching calibration equation. 2. Etching offset.

As an example, obtaining the first etching calibration quantity equation includes: using the actual spot offset data of multiple first mark units as input samples, and using the corresponding first preset etching offset as the output sample, performing data Fitting, the first etching calibration quantity equation is obtained.

As an example, obtaining the second etching calibration quantity equation includes: using actual spot offset data of multiple second mark units as input samples, and using the corresponding second preset etching offset amounts as output samples, performing data fitting.

Although various steps in the flowcharts of FIGS. 8 and 9 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, the execution of these steps is not strictly limited and these steps can be executed in other orders. Moreover, although at least some of the steps in Figures 8 and 9 may include multiple sub-steps or multiple stages, these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. These sub-steps Or the execution of the stages does not necessarily need to be sequential, but may be performed in turn or alternately with other steps or sub-steps of other steps or at least part of the stages.

By using the measurement patterns, preparation methods, and measurement methods in the embodiments of the present disclosure, and obtaining monitoring values of semiconductor yield at preset sampling intervals, the average semiconductor yield can be reduced to 3 nm within 5 months. , and reduce the 3σ value of overlay accuracy to 1nm. Compared with the traditional use of SEM measurement technology for detection and correction, it can only reduce the average semiconductor yield to 4.5nm and the 3σ value of overlay accuracy to 2.5nm within 11 months; using IBO measurement technology for detection With correction, it is only possible to reduce the average semiconductor yield to 3.5nm and the 3σ value of overlay accuracy to 2.3nm within 8 months. The embodiments of the present disclosure are more efficient and effectively improve the manufacturing efficiency of semiconductor products. yield rate.

In some embodiments, a measurement device is provided, including a support, an optical system, and a processor. The support is used to support a substrate with multiple target structures thereon; the optical system is used to measure each target structure. ; The processor is configured to perform the steps of the measurement method in any embodiment of the present disclosure.

In some embodiments, a measurement device is provided, including a memory and a processor. The memory stores a computer program that can be run on the processor. When the processor executes the program, the measurement in any embodiment of the present disclosure is implemented. Method steps.

In some embodiments, a computer-readable storage medium is provided, with a computer program stored thereon. When the computer program is executed by a processor, the steps of the measurement method in any embodiment of the present disclosure are implemented.

The measurement patterns and their preparation methods, measurement methods, devices, equipment and media in the above embodiments are formed by transferring the first etching pattern to the target layer on the wafer and forming it at different positions in the cutting lanes of the target layer. After measuring the first mark pattern and several first auxiliary mark patterns, the first auxiliary mark pattern is measured based on the principle of optical diffraction to obtain the first spot offset data, and the first etching of the first measurement mark pattern is obtained. Calibration equation; calculate the first etching offset caused by etching the first etching pattern based on the first spot offset data and the first etching calibration equation; transfer the second etching to the target layer on the wafer pattern, and after forming a second measurement mark pattern and several second auxiliary mark patterns at different positions in the cutting lane of the target layer, measure the second auxiliary mark pattern based on the principle of optical diffraction to obtain the second light spot offset data, and obtain the second light spot offset data. 2. Measure the second etching calibration amount equation of the mark pattern; calculate the second etching offset amount caused by etching the second etching pattern according to the second spot offset data and the second etching calibration amount equation. Embodiments of the present disclosure can quickly and accurately measure the etching offset of a semiconductor structure caused by a single etching process after performing multiple etching processes, and can accurately feedback and adjust the etching machine and equipment based on the etching offset. / Or corresponding to the relevant parameters of the etching process, improve the etching accuracy and efficiency of the etching machine and / or the corresponding etching process, and improve the yield and reliability of the manufactured semiconductor products.

Although specific reference has been made above to the use of embodiments of the present disclosure in the context of optical lithography, it should be noted that the present disclosure may be used in other applications, such as imprint lithography, and where appropriate Allowed, not limited to optical lithography. In imprint lithography, the topography in the patterning device defines the pattern produced on the substrate. The topography of the patterning device may be printed into a resist layer provided to the substrate, upon which the resist is cured by application of electromagnetic radiation, heat, pressure, or a combination thereof. After the resist is cured, the patterning device is removed from the resist, leaving a pattern in the resist.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage. In the media, when executed, the computer program may include the processes of the above method embodiments. Any reference to memory, storage, database or other media used in the various embodiments provided by this disclosure may include non-volatile and/or volatile memory.

Please note that the above-described embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

The technical features of the above-described embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, All should be considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present disclosure, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the disclosed patent. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed should be determined by the appended claims.

Claims

A measurement pattern, including a target layer and a first measurement mark pattern, a second measurement mark pattern, a plurality of first auxiliary mark patterns and a plurality of second auxiliary mark patterns located in different areas on the target layer;

The first measurement mark pattern includes a plurality of first mark units distributed in an array, and the first mark units have first preset parameters including a first preset etching offset;

The second measurement mark pattern includes a plurality of second mark units distributed in an array, and the second mark units have second preset parameters including a second preset etching offset.
The measurement pattern according to claim 1, wherein the first auxiliary mark pattern, the second auxiliary mark pattern, the first measurement mark pattern and the second measurement mark pattern are located on the same layer.
The measurement pattern according to claim 2, wherein the first measurement mark pattern and the second measurement mark pattern are located in the middle cutting lane area of the target layer;

The first auxiliary mark pattern and the second auxiliary mark pattern are located in the edge cutting area of the target layer and surround the first measurement mark pattern and the second measurement mark pattern.
The measurement pattern according to claim 1, wherein the first auxiliary mark pattern and the first measurement mark pattern are located on the same layer;

The second auxiliary mark pattern and the second measurement mark pattern are located on the same layer;

Wherein, the first auxiliary mark pattern and the second auxiliary mark pattern are located on different layers.
The measurement pattern according to any one of claims 1 to 4, wherein the first auxiliary mark pattern has a third preset etching offset, and the third preset etching offset is at least associated with Part of the first preset parameters;

The second auxiliary mark pattern has a fourth preset etching offset, and the fourth preset etching offset is associated with at least part of the second preset parameter.
The measurement pattern according to any one of claims 1 to 4, wherein the first marking unit includes a first alignment mark located on the target layer and a second pair of alignment marks located on the front layer of the target layer. Alignment mark, used for determining the real-time etching offset of the first alignment mark and the second alignment mark based on the asymmetry of the light intensity distribution of the zero-order diffracted light.
The measurement pattern according to claim 6, wherein the second marking unit includes a third alignment mark located on the target layer and a fourth alignment mark located on the upper layer of the target layer, for measuring according to The asymmetry of the light intensity distribution of the zero-order diffracted light determines the real-time etching offset of the third alignment mark and the fourth alignment mark.
The measurement pattern according to claim 7, wherein any one of the first alignment mark, the second alignment mark, the third alignment mark and the fourth alignment mark includes a gap, At least one of cavities and bumps.
The measurement pattern according to claim 7, wherein the real-time etching offset includes an offset direction and an offset distance in the offset direction.
A method for preparing measurement patterns, including:

Provide a wafer; perform a preset first etching process to transfer a first etching pattern to a target layer on the wafer, and form a first measurement mark pattern and a plurality of first auxiliary marks at different positions in the cutting lane of the target layer Pattern; the first measurement mark pattern includes a plurality of first mark units distributed in an array, and the first mark unit has a first preset parameter including a first preset etching offset;

Execute a preset second etching process to transfer a second etching pattern to the target layer, and form a second measurement mark pattern and a plurality of second auxiliary mark patterns at different positions in the cutting lane of the target layer; the third The second measurement mark pattern includes a plurality of second mark units distributed in an array, and the second mark units have second preset parameters including a second preset etching offset.
The measurement pattern preparation method according to claim 10, wherein the first auxiliary mark pattern, the second auxiliary mark pattern, the first measurement mark pattern and the second measurement mark pattern are located on the same layer; or

The first auxiliary mark pattern and the first measurement mark pattern are located on the same layer, the second auxiliary mark pattern and the second measurement mark pattern are located on the same layer, and the first auxiliary mark pattern and the second measurement mark pattern are located on the same layer. The second auxiliary mark graphic is located on a different layer.
The measurement pattern preparation method according to claim 11, wherein the first auxiliary mark pattern has a third preset etching offset, and the third preset etching offset is associated with at least part of the The first preset parameter;

The second auxiliary mark pattern has a fourth preset etching offset, and the fourth preset etching offset is associated with at least part of the second preset parameter.
A measurement method, implemented after the measurement pattern preparation method according to any one of claims 10-12 is performed to form a measurement pattern, the measurement method includes:

Calculate the first etching offset caused by etching the first etching pattern based on the real-time etching offset of the first auxiliary mark pattern and its correlation with the first measurement mark pattern;

Based on the real-time etching offset of the second auxiliary mark pattern and its correlation with the second measurement mark pattern, a second etching offset caused by etching the second etching pattern is calculated.
The measurement method according to claim 13, wherein the first preset parameter includes a first etching calibration equation associated with a real-time etching offset of the first auxiliary mark pattern; The real-time etching offset of the first auxiliary mark pattern and its correlation with the first measurement mark pattern, calculating the first etching offset caused by etching the first etching pattern, includes:

Obtain the first etching calibration equation, and measure the first spot offset data including the real-time etching offset of the first auxiliary mark pattern based on the principle of optical diffraction;

The first etching offset caused by etching the first etching pattern is calculated according to the first spot offset data and the first etching calibration equation.
The measurement method according to claim 13, wherein the second preset parameter includes a second etching calibration equation associated with the real-time etching offset of the second auxiliary mark pattern; The real-time etching offset of the second auxiliary mark pattern and its correlation with the second measurement mark pattern, calculating the second etching offset caused by etching the second etching pattern, includes:

Obtain the second etching calibration equation, and measure the second spot offset data including the real-time etching offset of the second auxiliary mark pattern based on the principle of optical diffraction;

The second etching offset caused by etching the second etching pattern is calculated according to the second spot offset data and the second etching calibration equation.
The measurement method according to claim 14, wherein obtaining the first etching calibration quantity equation includes:

Using the actual spot offset data of multiple first marking units as input samples, and using the corresponding first preset etching offset as the output sample, perform data fitting to obtain the first etching calibration amount equation.
The measurement method according to claim 15, wherein obtaining the second etching calibration quantity equation includes:

The actual spot offset data of the plurality of second marking units are used as input samples, and the corresponding second preset etching offset amounts are used as output samples to perform data fitting.