JPS6324617A - Method for double sided exposure of wafer - Google Patents

Abstract

PURPOSE:To enable highly accurate double sided alignment by means of a simple construction by forming a plurality of square through-holes, one side of which is in a predetermined direction, in a wafer by means of an anisotropic etching process. CONSTITUTION:A silicon wafer 1, of which the crystal plane is (100) and the orientation flat 3 is (110), is anisotropically etched through a mask, forming two through-windows 7, one side of which is in a direction (110). By aligning using the windows 7 as the reference marks, high-precision double sided alignment can be accomplished with a simple construction of a standard semiconductor process, without using a complex double sided aligner, thereby enabling accurate double sided exposure to be performed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Application Field The present invention relates to a double-sided exposure method for precisely aligning both sides of a silicon wafer, for example, using a standard mask liner for semiconductor processing.

<Prior Art> Mask aligners generally used in semiconductor processes cannot perform double-sided exposure. Therefore, when exposing patterns on both sides of a wafer, a double-sided exposure apparatus having a special optical system is used.

<Problems to be Solved by the Invention> However, the nine-sided double-sided exposure apparatus has a problem in that it has a complicated structure and is expensive.

The present invention has been made in view of the above problems.

The purpose is to perform precise double-sided exposure using a commonly used standard mask aligner.

Means to solve problems〉 The structure of the present invention for solving the above problems is as follows.

At least two rectangular through holes having one side in the <110> direction are formed using an anisotropic etching method from one side of a wafer having a crystal plane of (IQO), and alignment is performed using the through holes as an exposure reference. It is characterized in that it performs the following.

<Example> Figures 1 and 2 show the process of making a hole for a mark in a silicon wafer, for example, in order to put the present invention into practice, (a) is a plan view, and (b) is a It is a sectional view taken along A-Δ.

In FIG. 1(a), thermal oxide films (SiO2) 2 are first formed on both sides of a (100) silicon wafer 1. As shown in FIG. A part of this S'fOz is removed to provide a square window whose -side is parallel to the <110> direction of the orientation flat 3. In the figure, windows 7 are formed at two locations near the outer periphery of the silicon wafer 1. This silicon wafer 1
dipped in an alkaline solution (KOH aqueous solution, hydrazine ethylenediamine pyrocatechol aqueous solution, NaOH aqueous solution, etc.) to etch the window portion. As a result, Figure 2(a)
, (b), a (111) plane appears on the wall surface of the window, and a pyramid-shaped hole 4 can be made. Since this hole follows the crystal structure, it can be formed extremely accurately.

FIG. 3(a) shows a circuit pattern mask 6 whose marker is a cross line pattern tilted by ±45 degrees with respect to the <110> direction of the silicon wafer 1, and FIG. FIG. 2 is an enlarged plan view of part A in FIG. 2A, showing a state in which the marker 5 is superimposed on the back surface of the silicon wafer prepared in FIG. 2. FIG. If the two sides of the marker 5 are positioned at the corners of the hole 4 as shown in the figure, the circuit pattern can be easily placed at the same position on both sides.

Although the wafer is described as silicon in this embodiment, it is not limited to silicon. 1. Although the shape of the marker is shown as a cross line in this embodiment, it is not limited to this embodiment. 2. For example, a pattern of the same shape as the hole etching pattern may be used, or a different shape may be used as long as it can function as a marker. It can also be a shape. Furthermore, it is also possible to process not only one circuit pattern but also the silicon wafer itself in accordance with the desired position of the circuit pattern on the back side.

<Effect of the invention> As specifically explained below along with the F embodiment.

According to the invention? ff It is possible to perform highly accurate alignment with a simple structure using a standard semiconductor process without using a complicated and expensive double-sided exposure device.

[Brief explanation of the drawing]

Figures 1 (a) and (b) and Figures 2 (a) and (b) are diagrams showing the process of drilling a hole for a mark in a silicon wafer in the implementation of the present invention, and Figure 3 (a) is a cross-sectional view. A diagram showing a circuit pattern mask using a line pattern as a marker, Figure 3 (
1)) is a diagram showing a state in which markers are superimposed on a silicon wafer. DESCRIPTION OF SYMBOLS 1... Silicon wafer, 4... Hole, 5... Marker, 6... Circuit pattern, 7... Window. Figure 1 Atsushi Figure 2 M3 (G) (b)

Claims (1)

[Claims] At least two rectangular through holes having one side in the <110> direction are formed from one surface of a wafer having a (100) crystal plane using an anisotropic etching method, and alignment is performed using the through holes as an exposure reference. A double-sided wafer exposure method characterized by performing the following steps.