JPS6170722A - Method of working semiconductor substrate - Google Patents
Method of working semiconductor substrateInfo
- Publication number
- JPS6170722A JPS6170722A JP59192272A JP19227284A JPS6170722A JP S6170722 A JPS6170722 A JP S6170722A JP 59192272 A JP59192272 A JP 59192272A JP 19227284 A JP19227284 A JP 19227284A JP S6170722 A JPS6170722 A JP S6170722A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- substrate
- etching
- main surfaces
- approx
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims description 19
- 238000005530 etching Methods 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000007864 aqueous solution Substances 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000003754 machining Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
本発明は、半導体基板の加工方法に関し、特に半導体基
板の両主面に加工する方法に関する。TECHNICAL FIELD The present invention relates to a method of processing a semiconductor substrate, and more particularly to a method of processing both main surfaces of a semiconductor substrate.
前頭技術
半導体基板に集積回路を形成するに際し、半導体基板の
主面に回路パターンの形成加工が施される。この回路パ
ターンの形成加工にはフォトマスクを用いた光露光法と
電子ビームによる直接露光法とがある。電子ビームによ
る直接露光法においては、半導体基板の主面に予めエツ
チング等によって位置決め用のレジストレーションマー
クが形成され、各層の回路パターンの露光時に電子ビー
ムで当該マークが走査されて位置決めが行なわれる。ま
た、フォトマスクを用いた光露光法では、フォトマスク
内に形成づ゛べき回路パターンと共に多層合せ用のター
ゲートマークが設りられてJ3す、このマークによって
フォトマスクのバクーンが複数のマスクに日って半導体
基板の主面上で合せられる。Frontal technology When forming an integrated circuit on a semiconductor substrate, a circuit pattern is formed on the main surface of the semiconductor substrate. There are two methods for forming this circuit pattern: a light exposure method using a photomask and a direct exposure method using an electron beam. In the direct exposure method using an electron beam, a registration mark for positioning is formed in advance on the main surface of the semiconductor substrate by etching or the like, and the mark is scanned with an electron beam to perform positioning when exposing the circuit pattern of each layer. In addition, in the light exposure method using a photomask, a target mark for multilayer alignment is provided along with the circuit pattern to be formed within the photomask. The two are aligned on the main surface of the semiconductor substrate.
従って、半導体基・板の両支部に回路パターンを形成し
て集積度の向上等を図りたい場合には、両支部にそれぞ
れ位置決め用のマークを形成する必要がある。このとぎ
、半導体基板の両支部に高精度に位置決め用のマークを
形成する方法として物理的手段によって半導体基板に貫
通孔を穿設し、この貫通孔を位置決め用のマークとして
用いるという方法が考えられる。しかしながらかかる方
法におい℃は半導体基板の切り屑が生じ、この切り屑が
半導体基板の加工面に付着した場合、この切り屑を加工
面から除去するときに生じる傷は10μm以下の粘度を
必要とする場合には無視できないものとなる。また、こ
の物理的手段によって10μl以下の精度で貫通孔を穿
設すること自体が困難である。Therefore, if it is desired to improve the degree of integration by forming circuit patterns on both branches of the semiconductor substrate, it is necessary to form positioning marks on both branches. At this point, a possible method for forming positioning marks with high precision on both branches of the semiconductor substrate is to physically drill through holes in the semiconductor substrate and use these through holes as positioning marks. . However, in such a method, chips of the semiconductor substrate are generated at a temperature of 10°C, and when these chips adhere to the processed surface of the semiconductor substrate, the scratches generated when the chips are removed from the processed surface require a viscosity of 10 μm or less. In some cases, it cannot be ignored. Furthermore, it is difficult to drill through holes with an accuracy of 10 μl or less by this physical means.
そこで、互いに異なる加工面の2枚のフォトマスクを重
ね合わせたのらフォトマスクの面に平行にこれら2枚の
フォトマスクのうちの一方を相対的に移動させて位置を
設定したのち当該一方をフォトマスクの而に垂直に移動
させることによって半導体基板を2枚のフォトマスクの
間に挾んで露光することによって位置決め用のマークを
両面に形成する方法が考えられる。しかしながらかかる
方法においては構成が複雑で効果な両面露光装置を必要
とするという欠点がある。Therefore, after superimposing two photomasks with different processed surfaces, one of these two photomasks is moved relatively parallel to the surface of the photomask to set the position, and then the one A possible method is to form positioning marks on both sides by exposing the semiconductor substrate to light while sandwiching the semiconductor substrate between the two photomasks by moving the photomasks vertically. However, such a method has the disadvantage that it requires a complicated and effective double-sided exposure device.
発明の概要
本発明の目的は、高価な装置を用いずに半0体基板の両
支部を高精度に加工することがでさ・る加工方法を提供
することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a processing method that allows high precision processing of both branches of a half-zero board without using expensive equipment.
本発明による半導体基板の加工り法は、半導体基板の両
支部にこの半導体基板に比して異方性エツチングの影響
を受けにくい膜を形成し、半導体基板の両支部のうちの
一方に形成された膜の少なくとも2箇所において開口部
が形成されるように膜の一部を除去して半導体基板の主
面を露出さけ次いで半導体基板に異方性エツチングを施
して貫通孔を形成し、半導体基板の両主面上にJ3ける
貫通孔の相対的な位置を加工基準位置として両支部を加
工することを特徴としている。The semiconductor substrate processing method according to the present invention forms a film on both branches of the semiconductor substrate that is less susceptible to anisotropic etching than the semiconductor substrate, and forms a film on one of the two branches of the semiconductor substrate. A portion of the film is removed to avoid exposing the main surface of the semiconductor substrate so that openings are formed in at least two locations in the film, and the semiconductor substrate is anisotropically etched to form through holes. It is characterized in that both branches are machined using the relative positions of the through holes J3 on both main surfaces as the machining reference positions.
実 施 例
以下、本発明の実施例につき添付図面を参照して詳細に
説明する。Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
第1図及び第2図は本発明の実施例における位置決め用
の加工基準マークを形成する各工程を経た半i3 f、
k O板の断面図であり、共通部分はすべて同一符号に
より示されている。第1図において、面方位(100)
、厚さ400μm程度のシリコン基板1の両支部1a、
lbにCV D (Chemical Vapour
Depoition)法等で形成された厚さ100
0人程度0シ、リコン窒化物の膜2a、2bが存在する
。膜2aの少なくとも2箇所が投影露光型切により多臣
露光されて異方性エツチングのための方形の開孔3が形
成されている。このシリコン基板1を濃度40%程度の
K Ol−1水溶液に浸漬することによりシリコン基板
1がエツチングされる。このとき、(100)而におけ
るエツチング速麿が(111)面にJ3けるものよりも
約400侶速いのでシリ−1ン基板1の主面に垂直な方
向へのエツチングが支配的となり、第2図に示ず如<
IjJ通孔4が形成される。このrlざ400μm程度
のシリコン基板1の主面に平行な方向へのエツチングf
ilは1ミクロン程度の精度の加工においては無祝し得
るほど小ざい。従って、シリコン基板1の主面1a、l
bに第3図(A)、(B)にそれぞれ承り如く形成され
る開口部5a 、5b及び5c、5d間の位置ずれは極
めて小さいものとなる。従って、これら開口部58〜5
dを位置決め用の加工基準マークとして用いて半導体基
板の主面1a、1bに回路パターンを形成qれば主面1
a、1bにそれぞれ形成された回路パターン間の相対的
な位置が?:S精度に設定されることとなる。FIG. 1 and FIG. 2 show half i3f,
FIG. 3 is a cross-sectional view of a kO plate, in which all common parts are designated by the same reference numerals. In Figure 1, plane orientation (100)
, both branches 1a of the silicon substrate 1 with a thickness of about 400 μm,
CV D (Chemical Vapor) to lb
A thickness of 100 mm formed by the Depoition method etc.
There are about 0 silicon nitride films 2a and 2b. At least two portions of the film 2a are subjected to multi-exposure by projection exposure type cutting to form rectangular openings 3 for anisotropic etching. The silicon substrate 1 is etched by immersing it in a KOl-1 aqueous solution having a concentration of about 40%. At this time, since the etching speed on the (100) plane is about 400 times faster than that on the (111) plane, etching in the direction perpendicular to the main surface of the silicon substrate 1 becomes dominant, and As shown in the figure
IjJ through holes 4 are formed. This etching f in the direction parallel to the main surface of the silicon substrate 1 with an rl radius of about 400 μm
il is so small that it can be ignored in machining with an accuracy of about 1 micron. Therefore, the main surfaces 1a, l of the silicon substrate 1
The positional deviation between the openings 5a, 5b and 5c, 5d formed as shown in FIGS. 3(A) and 3(B) is extremely small. Therefore, these openings 58-5
If a circuit pattern is formed on the main surfaces 1a and 1b of the semiconductor substrate using d as a processing reference mark for positioning, then the main surface 1
What is the relative position between the circuit patterns formed on a and 1b? :S accuracy will be set.
尚、上記実施例においては異方性エツチング液としU
IIJ度40%程度のKOH水溶液が用いられかつシリ
コン基板1は厚さが400μm程麿であ9て両支部に窒
化膜が形成されているとしたが、1ツチング液の溶秤、
溶濃度及びシリコン基板1の厚さ、両支部に形成されで
いる膜の質は、異方性エツチングによつ’CC1通孔が
形成されるのて゛あればいずれであってもJ、い。In addition, in the above example, U is used as an anisotropic etching liquid.
It was assumed that a KOH aqueous solution with a concentration of about 40% was used, and that the silicon substrate 1 had a thickness of about 400 μm and a nitride film was formed on both branches.
The concentration of the solution, the thickness of the silicon substrate 1, and the quality of the film formed on both branches may be any one of them, as long as the CC1 holes are formed by anisotropic etching.
発明の効果
以上詳述した如く本発明による半導体基板の加工方法に
おい又は、異方性エツチングによって半導体基板に口通
几を穿設し、こ量適孔を加工l準位置として半導体基板
の両主面を加工するようにしたので、高価な装首を用い
ることなく半導体基板の両主面に対づる加工位置の精度
を向上させて両主面を高Mlflに加工1゛ることがで
きるのである。Effects of the Invention As detailed above, in the method of processing a semiconductor substrate according to the present invention, a through hole is formed in the semiconductor substrate by anisotropic etching, and the holes of the appropriate amount are used as semi-positions to process both main parts of the semiconductor substrate. Since the surface is machined, it is possible to improve the precision of the processing position on both main surfaces of the semiconductor substrate and process both main surfaces to a high Mlfl without using an expensive headpiece. .
第1図及び第2図は、本発明による位置決め用の加工基
準マークの形成工程における各工程を経た半シ9fホ基
板の断面図、第3図は、本発明によって形成された位置
決め用の加工JJ ’l”マークを有する半導体基板の
平面図である。1 and 2 are cross-sectional views of a half-circular 9F board that has gone through each step in the process of forming processing reference marks for positioning according to the present invention, and FIG. FIG. 2 is a plan view of a semiconductor substrate having a JJ 'l'' mark.
Claims (2)
方性エッチングの影響を受けにくい膜を形成し、前記半
導体基板の両主面のうちの一方に形成された膜の少なく
とも2箇所において開口部が形成されるように前記膜の
一部を除去して前記半導体基板の主面を露出させ、次い
で前記半導体基板に前記主面に垂直な方向においてエッ
チング速度の大なる異方性エッチングを施して貫通孔を
形成し、前記半導体基板の両主面上における前記貫通孔
の相対的な位置を加工基準点として前記両主面をそれぞ
れ加工することを特徴とする半導体基板の加工方法。(1) A film that is less susceptible to anisotropic etching than the semiconductor substrate is formed on both main surfaces of the semiconductor substrate, and at least two of the films formed on one of the two main surfaces of the semiconductor substrate A portion of the film is removed to expose the main surface of the semiconductor substrate so that an opening is formed at a location, and then the semiconductor substrate is etched with a large anisotropy of etching rate in a direction perpendicular to the main surface. A method of processing a semiconductor substrate, comprising forming a through hole by etching, and processing both main surfaces of the semiconductor substrate using the relative positions of the through holes on both main surfaces as a processing reference point. .
なすことを特徴とする特許請求の範囲第1項記載の半導
体基板の加工方法。(2) The method of processing a semiconductor substrate according to claim 1, wherein the step of removing a portion of the film is performed by multiple exposure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59192272A JPS6170722A (en) | 1984-09-13 | 1984-09-13 | Method of working semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59192272A JPS6170722A (en) | 1984-09-13 | 1984-09-13 | Method of working semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6170722A true JPS6170722A (en) | 1986-04-11 |
Family
ID=16288511
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59192272A Pending JPS6170722A (en) | 1984-09-13 | 1984-09-13 | Method of working semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6170722A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01214040A (en) * | 1988-02-22 | 1989-08-28 | Nec Corp | Manufacture of semiconductor integrated circuit |
-
1984
- 1984-09-13 JP JP59192272A patent/JPS6170722A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01214040A (en) * | 1988-02-22 | 1989-08-28 | Nec Corp | Manufacture of semiconductor integrated circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3963489A (en) | Method of precisely aligning pattern-defining masks | |
US6820525B2 (en) | Precision Fiducial | |
CN105182681B (en) | A kind of mask plate and the method that a variety of depth structures are processed on same silicon wafer | |
JPS6170722A (en) | Method of working semiconductor substrate | |
JP4039036B2 (en) | Alignment mark manufacturing method | |
JPS62106625A (en) | Exposure mask | |
JPH03226392A (en) | Laser beam machining method | |
JP3212368B2 (en) | Automatic reference drilling machine for printed circuit boards | |
US20070003128A1 (en) | A Method Of Aligning A Pattern On A Workpiece | |
JPS5839015A (en) | Manufacture of semiconductor device | |
JPS6324617A (en) | Method for double sided exposure of wafer | |
JPS60177982A (en) | Double-side marking method | |
CN108658036B (en) | A kind of synchronization wet etching processing method of differentiation micro-structure | |
JPH021106A (en) | Formation of pattern | |
JPS607120A (en) | Method for positioning semiconductor wafer | |
JPS63175422A (en) | Manufacture of x-ray mask | |
JPS6111461B2 (en) | ||
US6077449A (en) | Method of checking the accuracy of the result of a multistep etching process | |
JPH02244663A (en) | Manufacture of lead frame | |
JPS61256635A (en) | Manufacture of semiconductor device | |
JPS60224224A (en) | Mask aligning method | |
JPS6011654Y2 (en) | alignment device | |
JPS62143054A (en) | Mask | |
JPS61270823A (en) | Manufacture of semiconductor device | |
JPH01126651A (en) | Photomask |