JPS61256635A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61256635A JPS61256635A JP60098414A JP9841485A JPS61256635A JP S61256635 A JPS61256635 A JP S61256635A JP 60098414 A JP60098414 A JP 60098414A JP 9841485 A JP9841485 A JP 9841485A JP S61256635 A JPS61256635 A JP S61256635A
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- alignment marks
- resist
- semiconductor substrate
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 239000003960 organic solvent Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法で、特に、金属膜形成
後のホトレジスト工程で、高精度の重ね合わせ精度でパ
ターンを形成することを可能とする、半導体装置の製造
方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for forming a pattern with high overlay accuracy in a photoresist process after forming a metal film. The present invention relates to a method of manufacturing a semiconductor device.
半導体回路の集積化が進むにつれて、パターンは筐すま
す微細になり、設計マージンも少なくなっている。その
ため、解像度がよく、高精度の重ね合わせ精度をもつ縮
小投影型露光装置がよく使われている。すなわち、縮小
投影型露光装置では、第２図（ａ）の断面図に示すよう
に、ポリシリコンのアライメントマーク４が形成された
半導体基板ｌの上に、配線用金属膜、例えば、アルミニ
ウム膜２を形成後、ホトレジスト１０を塗布し、対物レ
ンズ６を通して照射するレーザ光７でスキャンし、アラ
イメントマーク４のエツジから出る散乱光でアライメン
トマーク４を検出し、それにつぎのパターンを形成する
ためのマスクを重ね合せている。As semiconductor circuits become more integrated, patterns become increasingly finer and design margins become smaller. For this reason, reduction projection type exposure apparatuses with good resolution and high overlay accuracy are often used. That is, in the reduction projection type exposure apparatus, as shown in the cross-sectional view of FIG. After forming a photoresist 10, a photoresist 10 is applied and scanned with a laser beam 7 irradiated through an objective lens 6, the alignment mark 4 is detected by scattered light emitted from the edge of the alignment mark 4, and a mask is applied to form the next pattern. are superimposed.
上記従来方法によるアライメントマーク検出では、アル
ミ形成時にできる粒状性の凹凸のため、アライメントマ
ークのエツジがくずれたり、また、第２図（ｂ）の断面
図に示すように、アライメントマーク４のエツジにおけ
るアルミニウム膜２の段差部１３の方向依存性のために
、アライメントマークの位置検出精度が上らないという
欠点があった。In alignment mark detection using the conventional method described above, the edge of the alignment mark may be distorted due to the granular irregularities created during aluminum formation, and as shown in the cross-sectional view of FIG. 2(b), the edge of the alignment mark 4 may be Due to the direction dependence of the stepped portion 13 of the aluminum film 2, there is a drawback that the accuracy of detecting the position of the alignment mark cannot be improved.
上記間組に対して本発明では、半導体基板上に金属膜形
成後、レジストを塗布し、マスクパターンを用いて、紫
外線あるいは遠紫外線で違択蕗元してパターンを形成し
、アライメントマーク上の金属膜をリン酸系の１１１．
ｔＲで除去して、レジストを有機溶済で剥離した後に、
レジストを塗布し、所望のパターンを形成する。In the present invention, after forming a metal film on a semiconductor substrate, a resist is applied to the semiconductor substrate, and a pattern is formed by selectively applying ultraviolet rays or far ultraviolet rays using a mask pattern. The membrane was coated with phosphoric acid-based 111.
After removing with tR and peeling off the resist with organic solution,
Apply resist and form the desired pattern.
次に本発明について、図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図＜ａ） 、 （ｂ） 、 （Ｃ）は本発明の一実
施例に係るレジストパターンを形成する工程順の基板断
面図である。まず、第１図（ａ）のように、アライメン
トマーク４が形成されている半導体基板１上に、金属膜
２を形成後、ネガ系のレジスト５塗布し、マスク１２の
暗部１２ａＫより遮蔽してアライメントマーク４および
その周辺に、紫外線、または遠紫外線１１を当てないこ
とにより、アライメントマーク４の上およびその周辺の
レジスト５を現像により除去する。つぎに、第１図（ｂ
）のように、残りのレジスト５をマスクにして、リン酸
系の混ばてアライメントマーク上およびその同辺の金属
膜を除去し、さらに残りのレジスト５を有機溶剤で剥離
する。つぎに第１図ｔｃ）のように、ポジ糸しジス）１
０ｔ−ｆｉ布し、アライメントマーク４にレーザビーム
７を用いて、半導体基板に所望のパターンを重ね合わせ
る際、金属膜が７２イメントマーク上にないため正確な
重ね合わせができる。FIGS. 1A, 1B, and 1C are cross-sectional views of a substrate in the order of steps for forming a resist pattern according to an embodiment of the present invention. First, as shown in FIG. 1(a), a metal film 2 is formed on a semiconductor substrate 1 on which an alignment mark 4 is formed, and then a negative resist 5 is applied and shielded from a dark part 12aK of a mask 12. By not applying ultraviolet rays or deep ultraviolet rays 11 to the alignment mark 4 and its surroundings, the resist 5 above and around the alignment mark 4 is removed by development. Next, in Figure 1 (b
), using the remaining resist 5 as a mask, the metal film on and around the alignment mark mixed with phosphoric acid is removed, and then the remaining resist 5 is peeled off with an organic solvent. Next, as shown in Figure 1 tc), make positive threads 1)
When a desired pattern is superimposed on a semiconductor substrate using a 0t-fi cloth and a laser beam 7 is applied to the alignment mark 4, accurate superposition can be achieved because the metal film is not on the 72 alignment mark.
以上説明したように本発ｉは、所望の微細パターンを金
属薄膜に転写する前に、半導体基板上にあるアライメン
トマーク上の金属薄膜を除去することにより、重ね合わ
せ精度を上げ、ＩＣ，ＬＳＩ製造工程の歩留りを上げる
ことができる。As explained above, the present invention improves overlay accuracy by removing the metal thin film on the alignment marks on the semiconductor substrate before transferring the desired fine pattern onto the metal thin film, thereby improving IC and LSI manufacturing. It is possible to increase the yield of the process.
第１図ｔａ） 、 （ｂ） 、 （Ｃ）は本発明の一実
施例に係る工程順の基板断面図、第２図（ａ） 、 ｔ
ｂ）は従来の方法によるアライメントマークの検出を説
明するための断面図である。
１・・・・・・半導体基板、２・・・・・・金属薄膜、
４・・・・・・アライメントマーク、５・・・・・・ネ
ガレジスト、６・・・・・・対物レンズ、７・・・・・
・レーザビーム、１０・・・・・・ポジレジスト、１１
・・・・・・線光用光、１２・・・・・・マスク、１２
ａ・・・・・・マスク暗部。
（。
／ｌτ外線
第１図Figures 1 (ta), (b) and (C) are cross-sectional views of a substrate in the order of steps according to an embodiment of the present invention, and Figures 2 (a) and (t) are
b) is a cross-sectional view for explaining detection of alignment marks by a conventional method. 1... Semiconductor substrate, 2... Metal thin film,
4... Alignment mark, 5... Negative resist, 6... Objective lens, 7...
・Laser beam, 10...Positive resist, 11
...Line light, 12...Mask, 12
a... Dark part of the mask. (. /lτ external line Figure 1
Claims (1)
装置の製造方法において、マスクの位置合せに用いるア
ライメントマークが形成された前記半導体基板上に金属
膜を形成後、前記アライメントマーク上の前記金属膜を
除去し、つぎに所望のパターンの位置合せをし、前記金
属膜配線を形成することを特徴とする半導体装置の製造
方法。In a method for manufacturing a semiconductor device including forming a metal film wiring on a semiconductor substrate, after forming a metal film on the semiconductor substrate on which an alignment mark used for alignment of a mask is formed, the metal film on the alignment mark is A method for manufacturing a semiconductor device, comprising removing a film, then aligning a desired pattern, and forming the metal film wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60098414A JPS61256635A (en) | 1985-05-09 | 1985-05-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60098414A JPS61256635A (en) | 1985-05-09 | 1985-05-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61256635A true JPS61256635A (en) | 1986-11-14 |
Family
ID=14219164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60098414A Pending JPS61256635A (en) | 1985-05-09 | 1985-05-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61256635A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5100834A (en) * | 1990-03-20 | 1992-03-31 | Fujitsu Limited | Method of planarizing metal layer |
| JP2019101357A (en) * | 2017-12-07 | 2019-06-24 | エイブリック株式会社 | Semiconductor device, position detection method of semiconductor device, and manufacturing method of semiconductor device |
-
1985
- 1985-05-09 JP JP60098414A patent/JPS61256635A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5100834A (en) * | 1990-03-20 | 1992-03-31 | Fujitsu Limited | Method of planarizing metal layer |
| JP2019101357A (en) * | 2017-12-07 | 2019-06-24 | エイブリック株式会社 | Semiconductor device, position detection method of semiconductor device, and manufacturing method of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2000331928A (en) | Lithographic method | |
| US4610948A (en) | Electron beam peripheral patterning of integrated circuits | |
| JPS61256635A (en) | Manufacture of semiconductor device | |
| JPH02262319A (en) | Pattern forming method | |
| JPH0664337B2 (en) | Photomask for semiconductor integrated circuit | |
| JPS63275115A (en) | Pattern forming method for semiconductor device | |
| JP3120345B2 (en) | Phase shift mask and semiconductor device | |
| US6228661B1 (en) | Method to determine the dark-to-clear exposure dose for the swing curve | |
| JPH0544169B2 (en) | ||
| JPH0787174B2 (en) | Pattern formation method | |
| JP2603935B2 (en) | Method of forming resist pattern | |
| JPH0355815B2 (en) | ||
| JPS61102738A (en) | Method of forming pattern for resist film | |
| JP3529967B2 (en) | Manufacturing method of photomask blanks with alignment marks | |
| JPH07181686A (en) | Forming method of resist pattern | |
| JP2014232809A (en) | Method for correcting wafer defect and device for manufacturing semiconductor | |
| KR100277490B1 (en) | Method for patterning of semiconductor device | |
| JPS62190839A (en) | Exposing method | |
| JPH04164313A (en) | Manufacture of semiconductor device | |
| KR100244765B1 (en) | Method for patterning of semiconductor device | |
| JPS6188525A (en) | Manufacture of integrated circuit | |
| JPS5848919A (en) | Preparation of semiconductor device | |
| KR20050032871A (en) | Apparatus and method for fabricating semiconductor device | |
| JPH033373B2 (en) | ||
| JPH0360008A (en) | Manufacture of semiconductor device |