JPS5848919A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5848919A
JPS5848919A JP56147410A JP14741081A JPS5848919A JP S5848919 A JPS5848919 A JP S5848919A JP 56147410 A JP56147410 A JP 56147410A JP 14741081 A JP14741081 A JP 14741081A JP S5848919 A JPS5848919 A JP S5848919A
Authority
JP
Japan
Prior art keywords
pattern
electron beam
resist
irradiated
miniature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56147410A
Other languages
Japanese (ja)
Inventor
Isamu Takashima
勇 高島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56147410A priority Critical patent/JPS5848919A/en
Publication of JPS5848919A publication Critical patent/JPS5848919A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/7045Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To quickly obtain ultra-minute pattern by employing the high resolution electron beam patterning system with low processing capability for miniature part of specified pattern and the ordinary exposure for the rough area. CONSTITUTION:The negative electron beam resist is coated to the material 8 to be processed on the semiconductor substrate 7. After the position alignment 10, the electron beam is irradiated 11 in accordance with a miniature minute pattern. Then, after mask alignment 10 of the window, the light including the wavelength of 180-300mm. is irradiated to the large pattern region. The pattern 9' is obtained by evelopment and the material 8 is etched using the mask 9'. Since the electron beam is irradiated only to the miniature pattern region, the scanning time is curtailed as compared with that for entire part and the ultra-miniature pattern which has not been obtained by the existing method can be formed. In case this method is applied to the positive resist, since the scanning area is narrow, the scanning time is not elongated and high speed patterning can be realized as in the case of negative resist, making high the degree of freedom of selecting resist material.

Description

【発明の詳細な説明】 本発明は、半導体基板上に微細パターンを、有する半導
体装置の製造方法に関し、特に寸法1μm以下の微細パ
ターンを形成するリングラフィ技術に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a fine pattern on a semiconductor substrate, and particularly to a phosphorography technique for forming a fine pattern with a size of 1 μm or less.

IC%LSI等の半導体素子の周波数特性や集積度を向
上するためには、素子寸法を小さくしてその加工精度を
高める必要がある。そして、その最小寸法は1#1以下
のものが必要となっている。
In order to improve the frequency characteristics and degree of integration of semiconductor devices such as IC%LSI, it is necessary to reduce the device dimensions and improve the processing accuracy. The minimum size must be 1#1 or less.

従来の半導装置では、素子寸法は2μ以上であシ、その
加工にはフォトリング2フイ技術が用いられている。こ
れは半導体基板上に7オトレジストを、塗布し、所定の
パターンが描かれているフォトマスクをマスクとして紫
外線を、照射することによシ、所定のパターンをフォト
レジストに転写する技術である。しかし、光を使った転
写方法では解像度が低い丸め、1趨よシ小さいパターン
を形成することは困難であり、それに代れるものとして
光よシ更に波長の短い電子線やX線を照射する方法が取
られる様になった。
In conventional semiconductor devices, the element size is 2μ or more, and photoring 2-fi technology is used for processing. This is a technique in which a photoresist is coated on a semiconductor substrate, and a predetermined pattern is transferred to the photoresist by irradiating it with ultraviolet light using a photomask on which a predetermined pattern is drawn as a mask. However, with transfer methods that use light, it is difficult to form patterns that are smaller than rounded or one-line patterns with low resolution.An alternative method is to use electron beams or X-rays that have shorter wavelengths than light. started to be taken.

電子線を用いた転写方法は通称電子線リングラフィと呼
ばれ、その方式の1つとしてマスクを用いずに直接ウェ
ハー基板上に電子線を走査しながら照射する方法が、あ
る。一方、電子線に反応しパターンを形成出来るレジス
トは電子線レジストと呼ばれ、フォトレジストと同様に
電子線を照射し友部分が溶解するポジ型レジストと電子
線を照射した部分が残るネガ型レジストがある。ポジ型
レジストにはPMMA (ポリメチルメタクリレート)
やPMIPK (ポリメチルイソプロペニルケトン)等
があシ、ネガ型レジストにもCM、、PGMA等がある
。電子線リングラフィの解像度は前記電子線レジストに
よって左右されるが、0.2μm程度まで解像出来る。
A transfer method using an electron beam is commonly called electron beam phosphorography, and one of the methods is to directly irradiate a wafer substrate with an electron beam while scanning it without using a mask. On the other hand, resists that can form patterns by reacting with electron beams are called electron beam resists, and like photoresists, there are positive resists whose friendly parts dissolve when exposed to electron beams, and negative resists where the electron beam irradiated parts remain. There is. PMMA (polymethyl methacrylate) for positive resist
and PMIPK (polymethyl isopropenyl ketone), and negative resists include CM, PGMA, etc. The resolution of electron beam phosphorography depends on the electron beam resist, but it can resolve down to about 0.2 μm.

しかしながら、前記電子線レジストは電子線に対する感
度が低いためウェハー全面のパターンを形成するために
非常に長時間を要し、その処理能力は従来のフォトリソ
グラフィに比べて極めて劣ってしまう。
However, since the electron beam resist has low sensitivity to electron beams, it takes a very long time to form a pattern on the entire surface of a wafer, and its throughput is extremely inferior to that of conventional photolithography.

本発明は電子線リングラフィの高解像度である長所を生
かしながら、処理能力が低い欠点を補う方法を提供する
ことを目的とするものである。
An object of the present invention is to provide a method that takes advantage of the high resolution of electron beam phosphorography while compensating for the drawback of low processing power.

すなわち、所定のパターンを比較的微細パターン領域と
これよシも大きなパターン領域とに分割し、この微細パ
ターン領域は電子線リソグラフィで描画し、大きなパタ
ーン領域は波長180〜300■の含んだ光を用いたフ
ォトリソグラフィで形成することを特徴とする。前記の
電子線レジストのほとんどは180〜300mの遠紫外
光でも反応するので、遠紫外光を使ったフォトリソグラ
フィにも使用できる。
That is, a predetermined pattern is divided into a relatively fine pattern area and a much larger pattern area, the fine pattern area is drawn using electron beam lithography, and the large pattern area is drawn using light containing wavelengths of 180 to 300 cm. It is characterized by being formed using photolithography. Since most of the electron beam resists mentioned above react even with deep ultraviolet light of 180 to 300 m, they can also be used in photolithography using deep ultraviolet light.

以下、図面を用いて本発明の一実施例を詳細に説明する
Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

第1図は、半導体ウェハー全面に形成しようとする所定
のチップパターン図である。第2図は第1図のパターン
を微細領域2.3.4と大きなパターン領域5とに分割
した状態を示す。ここで6は両者の重なシ部である。
FIG. 1 is a diagram of a predetermined chip pattern to be formed on the entire surface of a semiconductor wafer. FIG. 2 shows a state in which the pattern of FIG. 1 is divided into a fine area 2.3.4 and a large pattern area 5. In FIG. Here, 6 is the overlapping part of both.

第1図の所定のパターン1にレジストを残す場合につい
ての一実施例を以下に示す。第3図(a)に示すsK表
面に被加工材8を有する半導体基板7の上にネガ型電子
線レジスト9を全面に塗布する。
An example in which the resist is left in the predetermined pattern 1 shown in FIG. 1 will be described below. A negative electron beam resist 9 is applied over the entire surface of the semiconductor substrate 7 having the workpiece 8 on the sK surface shown in FIG. 3(a).

10は電子線リングl)フイおよびフォトグラフィに用
いられる位置合わせパターンである。この位置合わせパ
ターンを用いて位置合わせた後、レジストに対して第2
図のパターン2.3.4に従って電子線を照射する。こ
の照射された部分が第3図(b)の11である。しかる
後、第2図の大きなパターン領域5が明部であるフォト
マスクを用意し、半導体基板に位、置合わせパターン1
oで位置合わせした後、180〜300簡の波長を含ん
だ光を照射してレジストを光重合させる。この光を照射
した部分が第3図(C)の12である。そして所定の現
像液で現像すると、第3図(d)K示す様に、電子線及
び光の照射された部分は現像液に不溶化し、その他の領
域は溶解し、レジストパターン9′が半導体基板上に残
る。しかる後、レジストパターン9′をマスクに被加工
材8をエツチングすれば良い。
Reference numeral 10 denotes an electron beam ring l) and a positioning pattern used for photography. After alignment using this alignment pattern, a second
Electron beam irradiation is performed according to pattern 2.3.4 in the figure. This irradiated part is 11 in FIG. 3(b). After that, prepare a photomask in which the large pattern area 5 shown in FIG.
After alignment at 0, the resist is photopolymerized by irradiation with light containing a wavelength of 180 to 300 nm. The part irradiated with this light is 12 in FIG. 3(C). When the resist pattern 9' is developed with a predetermined developer, as shown in FIG. remain on top. Thereafter, the workpiece 8 may be etched using the resist pattern 9' as a mask.

一方同一パターンをポジ型レジストを用いて形成する第
2の実施例を第4図に示す。第4図2′、3’、 4’
は電子線リングラフィによって電子線を照射する部分を
示す。5′は180〜300簡の波長を含んだ光をフォ
トマスクを用いて照射する部分を示す。電子線および光
が照射された領域は現像で溶解するので、第1の実施例
と同様に所定のパター  4゜ンのレジストが半導体基
板上に残る。
On the other hand, a second embodiment in which the same pattern is formed using a positive resist is shown in FIG. Figure 4 2', 3', 4'
indicates a part irradiated with an electron beam by electron beam phosphorography. Reference numeral 5' indicates a portion to which light containing wavelengths of 180 to 300 wavelengths is irradiated using a photomask. Since the area irradiated with the electron beam and light is dissolved by development, a resist with a predetermined pattern of 4° remains on the semiconductor substrate as in the first embodiment.

以上述べたように本発明では1μ簿以下の微細パターン
の領域にだけ電子線を照射し、その他の露光面積の広い
領域には光照射を行なうので、全て電子線のみでレジス
トパターンを形成する時よシも電子線の走査時間が短く
なり、電子線露光装置の処理能力が大きく向上する。一
方、従来のフォトリソグラフィでは不可能であった微細
パターンの形成も可能となる。
As described above, in the present invention, the electron beam is irradiated only to the area of the fine pattern of 1 μm or less, and the other areas with a large exposed area are irradiated with light. Furthermore, the scanning time of the electron beam is shortened, and the throughput of the electron beam exposure apparatus is greatly improved. On the other hand, it also becomes possible to form fine patterns that were impossible with conventional photolithography.

さらに微細加工のためKはレジスト材の選択が重要であ
るが、本実施例で示した様にレジストを残す面積が少な
い場合には従来の電子線リングラフィでは照射面積が多
いのでポジレジストの使用はさらに処理能力が低くなっ
て不利であったが、本発明によれdポジ、ネガ両型共さ
#1ど電子線走査時間は異ならず、すなわちネガ型と同
様に高速でパターン化でき、レジスト材の選拓の自由度
も高くなる。
Furthermore, the selection of the resist material for K is important for microfabrication, but when there is only a small area to leave resist as shown in this example, a positive resist is used because the irradiation area is large in conventional electron beam phosphorography. However, according to the present invention, the electron beam scanning time is the same for both d-positive and negative types, which means that patterning can be performed at the same high speed as the negative type, and resist The degree of freedom in material selection also increases.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半導体装置の一素子パターンの例を示す平面囚
、第2図、第4図は本発明の実施例を示すパターン構成
図、第3図(a)〜(d)は本発明の一実施例を工程順
に示す半導体の断面図を示す。 1・・・・・・チップパターン、2.3.4.5・・・
・・・チップパターンの分割パターン、6・・・・・・
分割パターンの重なシ部、7・・・・・・半導体基板、
8−・・・・・被加工材、9.9’・・・・・・電子線
レジス)、10・・・・・・位置合わせ領域、11・・
・・・・電子線照射領域、12・・・・・・光照射領域
FIG. 1 is a plan view showing an example of one element pattern of a semiconductor device, FIGS. 2 and 4 are pattern configuration diagrams showing an embodiment of the present invention, and FIGS. 1A and 1B are cross-sectional views of a semiconductor illustrating an example in the order of steps. 1... Chip pattern, 2.3.4.5...
...Chip pattern division pattern, 6...
Overlapping part of the division pattern, 7... semiconductor substrate,
8-... Work material, 9.9'... Electron beam register), 10... Positioning area, 11...
...Electron beam irradiation area, 12...Light irradiation area.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に所定のレジストパターンを形成するにあ
たシ、該半導体基板上にレジストを塗布する工程と、該
レジストの一部の微細領域に電子線を照射する工程と、
前記レジストの前記微細領域よシ大きい領域に光を照射
する工程と、しかる後前記レジストを現儂する工程とを
含むことを特徴とする半導体装置の製造方法。
To form a predetermined resist pattern on a semiconductor substrate, a step of applying a resist on the semiconductor substrate, a step of irradiating a part of a fine region of the resist with an electron beam,
A method of manufacturing a semiconductor device, comprising the steps of: irradiating a region of the resist with light that is larger than the fine region; and then applying the resist.
JP56147410A 1981-09-18 1981-09-18 Preparation of semiconductor device Pending JPS5848919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56147410A JPS5848919A (en) 1981-09-18 1981-09-18 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56147410A JPS5848919A (en) 1981-09-18 1981-09-18 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5848919A true JPS5848919A (en) 1983-03-23

Family

ID=15429663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56147410A Pending JPS5848919A (en) 1981-09-18 1981-09-18 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5848919A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117214A (en) * 1982-12-20 1984-07-06 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Method of forming exposure pattern by electron beam and light
JPH02260726A (en) * 1988-12-06 1990-10-23 General Instr Corp Digital sound supply method in fm broadcasting band, its receiver, and audio signal broadcasting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117214A (en) * 1982-12-20 1984-07-06 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Method of forming exposure pattern by electron beam and light
JPH02260726A (en) * 1988-12-06 1990-10-23 General Instr Corp Digital sound supply method in fm broadcasting band, its receiver, and audio signal broadcasting device

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