JPS59141230A - Formation of pattern - Google Patents
Formation of patternInfo
- Publication number
- JPS59141230A JPS59141230A JP58016588A JP1658883A JPS59141230A JP S59141230 A JPS59141230 A JP S59141230A JP 58016588 A JP58016588 A JP 58016588A JP 1658883 A JP1658883 A JP 1658883A JP S59141230 A JPS59141230 A JP S59141230A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- resist
- ultraviolet rays
- exposure
- electron beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/7045—Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
- H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
- H01J37/3175—Projection methods, i.e. transfer substantially complete pattern to substrate
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Analytical Chemistry (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electron Beam Exposure (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体素子などを製造する為の基板Ｅの薄
膜面上に施されたレジスト膜に、微細なパターンを形成
する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming fine patterns on a resist film applied on a thin film surface of a substrate E for manufacturing semiconductor devices and the like.
半導体素子などを製造する際には、極めて微細なパター
ンを所定の位置に高精度に形成する必要があり、これら
のパターンは一般−こフォトリソグラフィー技術によっ
て形成される。When manufacturing semiconductor devices and the like, it is necessary to form extremely fine patterns at predetermined positions with high precision, and these patterns are generally formed by photolithography technology.
従来のこの種のパターン形成方法を第１図を用いて説明
する。図において、（１）は半導体ウェハーなどからな
る基板で％Ｌ面に酸化膜などの下地薄膜（２）が施され
ている。（３）は下地薄膜（２）面に施されたレジスト
である。次に（４）はフォトマスクであり亀ガラス基板
（５）の下面に所要のパターン（６１が形成されている
。このマスク（４）の形成は次のようにして行なわれる
。即ち、先ずガラス基板（５）−ヒ１こ付着された金属
薄膜にレジスト嵯布後、所要のレジストパターンを形成
し・ついで、エツチングレジスト剥離後パターン（６１
を形成する。A conventional pattern forming method of this type will be explained with reference to FIG. In the figure, (1) is a substrate made of a semiconductor wafer or the like, and a base thin film (2) such as an oxide film is formed on the %L surface. (3) is a resist applied to the surface of the base thin film (2). Next, (4) is a photomask, and a required pattern (61) is formed on the bottom surface of the turtle glass substrate (5).The formation of this mask (4) is performed as follows. After coating the metal thin film on the substrate (5) - 1, a desired resist pattern is formed.Then, the pattern (61) is formed after removing the etching resist.
form.
このよう番こして形成したフォトマスク（４）を％第１
図（ａ）のように基板（１）のＦ部に位ｌｊ＆決めして
配置し、上方から矢印Ｐのように紫外線を照射する。The photomask (4) thus prepared was
As shown in Figure (a), it is placed at the F section of the substrate (1), and ultraviolet rays are irradiated from above in the direction of arrow P.
透過した紫外線番こよりレジスト（３）が感光する。次
に、所定の現像液により４像し、同図（ｂ）のように、
レジストパターン（７）を得る。そしてこのレジストパ
ターン（７）をマスクにして下地薄膜（２）をエツチン
グし、同図（Ｃ）のよう番こ、パターン（８１が残って
形成される。つおいて、レジストパターン（７）を剥離
除去すること４こより、所望のパターン（８）が露出し
て得られる。The resist (3) is exposed to the transmitted ultraviolet light. Next, four images are taken using a prescribed developer, as shown in the same figure (b).
A resist pattern (7) is obtained. Then, using this resist pattern (7) as a mask, the underlying thin film (2) is etched, leaving a pattern (81) as shown in Figure (C).Then, the resist pattern (7) is etched. By peeling and removing, the desired pattern (8) is exposed and obtained.
上記のような従来のパターン形成方法を用いて。using conventional patterning methods as described above.
例えば、スフＲＯＭあるいはマスタスライスなどのパタ
ーンを得たい場合番こは、毎回紫外線露光用マスクを作
成する必要があった。この紫外線マスクは作成工程が複
雑であり、多大の時間を要していた。したがって、工期
が長くかかり、費用が高くなっていた。さらに、微細パ
ターンの場合、これをフォトマスクで作成するには非常
に困難であったり、シャープなパターンが得られないと
いう欠点があった。For example, if you want to obtain a pattern for a flash ROM or a master slice, it is necessary to create a mask for ultraviolet exposure each time. The manufacturing process for this ultraviolet mask was complicated and took a lot of time. Therefore, the construction period was long and the cost was high. Furthermore, in the case of fine patterns, it is very difficult to create them using a photomask, and there are disadvantages in that a sharp pattern cannot be obtained.
この発明は、Ｆ記のような従来方法の欠点を除去するた
めになされたもので、基板のレジストの露光をその一部
を紫外線露光により、他部を電子ビーム露光により行う
ことにより、微細パターンが短期間に、しかも精度よく
得られるパターン形成方法を提供することを目的として
いる。This invention was made in order to eliminate the drawbacks of the conventional method as described in F. By exposing part of the resist on the substrate to ultraviolet light and the other part to electron beam exposure, fine patterns can be formed. The purpose of the present invention is to provide a pattern forming method that can obtain patterns with high accuracy in a short period of time.
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例によるパターン形成方法を示
し１図１こおいて、第１図と同一符号は同一のものを示
し、（９）はフォトマスクであり、これは次のような構
成である。即ち、ｕｌは所要のパターンで、曲は遮光用
パターンであり、これらは共にガラス基板層（５）の下
面に形成されている。なおこのフォトマスク（９）は覧
上記従来のフォトマスク（４）と同様にして形成する。FIG. 2 shows a pattern forming method according to an embodiment of the present invention. In FIG. 1, the same reference numerals as in FIG. It is a composition. That is, ul is a required pattern, and curve is a light-shielding pattern, both of which are formed on the lower surface of the glass substrate layer (5). Note that this photomask (9) is formed in the same manner as the conventional photomask (4) shown above.
次に第２図を用いて本発明の一実施例によるパターン形
成方法について説明する。Next, a pattern forming method according to an embodiment of the present invention will be explained using FIG.
半導体ウェハーからなる基板（１）Ｌ面には、酸化膜な
どの下地薄膜（２）を施し、その七にレジスト（３）。A thin base film (2) such as an oxide film is applied to the L side of the substrate (1) made of a semiconductor wafer, and a resist (3) is applied to the base film (2).
例えばＡ Ｚ ｌ ４７ Ｑ （ＳＨＩＰＬＥＹ社製）
、を約４．００ＯＡの厚さ−と塗布する。For example, A Z l 47 Q (manufactured by SHIPLEY)
, to a thickness of about 4.00 OA.
そして第２図（ａ）に示すよう番こ、基板（１）の上部
にフォトマスク（９）を位置決めして配置し、上方から
矢印Ｐのように紫外線を照射する。紫外線はＨ）ランプ
光源からの平行光線を使用し、約３秒の照射を行う。こ
の時遮光用パターンｆｉｌ＋の部分では紫外線は遮へい
され、所要のパターン（ＩＱ）のみがレジスト（３）に
転写される。露光完了後所定の現像液、例えば５Ｆ−１
１ＰＬＥＹ社製ＭＦ３１２で現像、洗浄し。Then, as shown in FIG. 2(a), a photomask (9) is positioned and placed on top of the substrate (1), and ultraviolet rays are irradiated from above in the direction of arrow P. For ultraviolet rays, use parallel light from a lamp light source and irradiate for about 3 seconds. At this time, ultraviolet rays are blocked in the portion of the light-shielding pattern fil+, and only the required pattern (IQ) is transferred to the resist (3). After completion of exposure, apply a prescribed developer, e.g. 5F-1.
1Developed with MF312 manufactured by PLEY and washed.
乾燥するとレジストパターン（７）および露光位置決め
のためのターゲットパターンであるレジスタマーク（１
２１が得られる（同図（ｂｌ参照）。When dried, a resist pattern (7) and a register mark (1), which is a target pattern for exposure positioning, are formed.
21 is obtained (see the same figure (bl)).
次憂こＥ述の過程で形成されたレジスタマーク（１２１
により正ｍイこ位置決めされた電子ビームにより同図（
Ｃ）に矢印Ｑで示すようにレジスト（３）に露光を行う
。電子ビームの露光強度は例えば４Ｘ１０−４Ｃ／ｃｒ
ｎ２とする。この電子ビームによりレジスト（３）に露
光する部分は１例えばマスクＲＯＭのＲＯＭの部分、あ
るいは微細パターン、又はマスタースライスの部分とす
る。Register mark (121) formed in the process described below
(
The resist (3) is exposed to light as shown by arrow Q in C). The exposure intensity of the electron beam is, for example, 4X10-4C/cr.
Let it be n2. The portion of the resist (3) exposed by this electron beam is, for example, a ROM portion of a mask ROM, a fine pattern, or a master slice portion.
屓子ビーム露光完了後、所定の現像液１例えば間Ｆ
ＳＨＩＰＬＥＹ社！！Ｌ１！３１２で現像し、洗浄を行
えば、同図（ｄｉで示すように微細なネガ型レジストパ
ターン＋１ｍが得られる。ノボラック系樹脂に過度な重
子ビームを照射するとネガ型パターンが得られることが
知られている。この得られたレジストパターン（ｔｉｌ
ｌをマスクにして、下地薄膜（２）のエツチングを行な
う（同図ｔｅｌ参照）。この時のエツチング条件は、例
えばプラズマ装置により７レオンガス中で出力２００Ｗ
、ガス／ｆ ０． Ｉ Ｔｏｒｒ テ行なった。つおい
て、レジストパターン（１３１を剥離除去すれば、同図
（ｆｌ ｉこ示すよう番こ、所要のパターン（１４１が
得られる。After completing the beam exposure, use a prescribed developer solution, for example FSHIPLEY! ! If developed with L1!312 and washed, a fine negative resist pattern +1 m can be obtained as shown in the same figure (di).It is possible to obtain a negative resist pattern by irradiating the novolak resin with an excessive amount of deuteron beam. This obtained resist pattern (til
Using 1 as a mask, the underlying thin film (2) is etched (see tel in the figure). The etching conditions at this time are, for example, a plasma device with an output of 200 W in 7 Leon gas.
, gas/f 0. I Torr was done. Then, by peeling and removing the resist pattern (131), the desired pattern (141) is obtained as shown in the same figure.
このようにして得られたパターンｆ１４１は、角部の切
れがよく、非常に鋭くてシャープであった。The pattern f141 thus obtained had sharp corners and was very sharp.
前記従来の紫外、線露光のみによるパターン形成方法で
は全品種、全店范工程について、それぞれフォトマスク
を作成する必要があったが１本発明の方法によれば特定
部分は電子ビームの露光番こより形成できるので、複雑
で面倒なフォトマスクの数を減少することができ、工期
が短剣され、生産性が四トする。また、得られたパター
ンは鋭くて精度のよいものとなる。In the conventional pattern forming method using only ultraviolet and line exposure, it was necessary to create a photomask for every product type and every process, but according to the method of the present invention, specific parts can be formed by electron beam exposure. As a result, the number of complicated and troublesome photomasks can be reduced, the construction period can be shortened, and productivity can be increased by four points. Furthermore, the resulting pattern is sharp and accurate.
また、従来のレジスト（３）は、紫外、腺に対しては高
感度、高解像度であっても、電子線に対しては感Ｉｆ、
解像度に問題があるものか多かった。しかし、本発明で
は、上記のようにノボラック樹脂をレジスト（３）に用
いたので、電子線に対しても高解像度となり、容易に高
精度に微細パターンが得られる。さらに、このレジスト
は耐プラズマ性を有しているので、下地薄膜（２）も容
易にドライエツチングでき、微細パターンを形成しやす
い利点がある。In addition, although the conventional resist (3) has high sensitivity and high resolution for ultraviolet light and glands, it has sensitivity If and high resolution for electron beams.
There were many problems with resolution. However, in the present invention, since the novolac resin is used for the resist (3) as described above, the resist has high resolution even with respect to electron beams, and a fine pattern can be easily obtained with high precision. Furthermore, since this resist has plasma resistance, the base thin film (2) can also be easily dry etched, which has the advantage of making it easy to form fine patterns.
第３図は、この発明の他の実施例によるパターン形成方
法を示し、基板のレジストに電子線及び電子ビームの露
光を同時にしている状態の断面図である。フォトマスク
（１励には紫外線露光用の共通パターン部のみが形成さ
れた所要のパターンｔ１６１が設けられている。基板（
１）のレジスト（３）のＬ部にマスク叫を位置決めして
配置し、矢印Ｐのように紫外線照射すると同時に、特定
部分のみを矢印Ｑのように電子ビームで照射する。この
よう（こすれば紫外線と電子ビームとの露光が同時にで
きる。FIG. 3 shows a pattern forming method according to another embodiment of the present invention, and is a sectional view showing a state in which a resist on a substrate is exposed to an electron beam and an electron beam at the same time. Photomask (1 excitation is provided with a required pattern t161 in which only a common pattern portion for ultraviolet exposure is formed. Substrate (
A mask is positioned and placed on the L portion of the resist (3) in step 1), and at the same time ultraviolet rays are irradiated as shown by arrow P, only a specific portion is irradiated with an electron beam as shown by arrow Q. By rubbing like this, you can simultaneously expose to ultraviolet rays and electron beams.
なお、上記実施例では、紫外線を照射後、電子ビームを
照射したが、その工程順序を逆にしてもよい。In the above embodiment, the electron beam was irradiated after the ultraviolet ray irradiation, but the order of the steps may be reversed.
また、Ｊ：、記他の実施例では、紫外線と′電子ビーム
との同時露光をしたが、さらにこの工程の前又は後に′
電子ビーム４こよる部分露光をする混合工程を行っても
よい。In addition, in the other examples described in J:, simultaneous exposure with ultraviolet rays and electron beams was carried out, but furthermore, before or after this step,
A mixing step in which partial exposure is performed using the electron beam 4 may also be performed.
なおまた、Ｌ記実施例ではフォトマスク（９目こ紫外線
を制御覗するのに遮へいパターン山１を設けたが。Furthermore, in Example L, a photomask (9th mask) was provided with shielding pattern peaks 1 to control ultraviolet rays.
この代りに、アパチャなどの絞りにより紫外線の透過を
制限するよう１こしてもよい。またｈ Ｍｃ！Ｗ施例で
は紫外線による方法について述べたが、遠紫外線による
方法でもよく、同様の効果を奏する。Alternatively, a diaphragm such as an aperture may be used to limit the transmission of ultraviolet rays. Also h Mc! In the W example, a method using ultraviolet rays has been described, but a method using far ultraviolet rays may also be used and the same effect can be achieved.
またさらに、上記実施例では、基板（１）面の下地薄膜
として酸化膜の例を示したか、導体膜の場合にも適用で
き、この場合、基板としては石英やガラス材などであっ
ても本発明を適用できるものである。Furthermore, in the above embodiments, an example of an oxide film was shown as the underlying thin film on the substrate (1) surface, but it can also be applied to the case of a conductor film, and in this case, even if the substrate is made of quartz or glass material, It is something to which the invention can be applied.
以上のように、この発明によれば、−４，板のレジスト
の露光を、一部は紫外線あるいは遠紫外線の照射により
、他部は″電子ビームの照射により行なうようにしたの
で、フォトマスクの枚数が減少でき、しかも微細パター
ンが短期間に精度よく得られ、生産性が向上する効果が
ある。As described above, according to the present invention, the resist on the -4 plate is exposed in part by irradiation with ultraviolet rays or far ultraviolet rays, and in other parts by irradiation with electron beams. The number of sheets can be reduced, fine patterns can be obtained with high precision in a short period of time, and productivity can be improved.
第１図は従来のパターン形成方法を工程順に示す基板部
とマスク部の断面図、第２図はこの発明の一実施例４こ
よるパターン形成方法を工程順に示す基板部とマスク部
の断面図％第３図はこの発明の他の実施例によるパター
ン形成方法を示す露光工程の基板部とマスク部の断面図
である。
図において、１は半導体ウェハ（基板）％２は下地薄膜
・３はレジスト、７．１３はレジストパターン、１２は
レジスタマーク（ターゲットパターン）、９，１５はフ
ォトマスク、１４ａ、１４ｂは所要のパターンである。
なお図中同一符号は同−又は相当部分を示す。
代 理 人 葛 野 信 −第
１図
第２図FIG. 1 is a sectional view of a substrate part and a mask part showing a conventional pattern forming method in the order of steps, and FIG. 2 is a sectional view of a substrate part and a mask part showing a pattern forming method according to Embodiment 4 of the present invention in the order of steps. 3 is a sectional view of a substrate portion and a mask portion in an exposure step showing a pattern forming method according to another embodiment of the present invention. In the figure, 1 is the semiconductor wafer (substrate), 2 is the base thin film, 3 is the resist, 7.13 is the resist pattern, 12 is the register mark (target pattern), 9 and 15 are the photomasks, and 14a and 14b are the required patterns. It is. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Makoto Kuzuno - Figure 1 Figure 2
Claims (5)
のレジストの一部にＥ方からフォトマスクを介して紫外
線あるいは遠紫外線を照射して露光するとともにこのレ
ジストの他部に電子ビームを照射して露光することによ
り上記下地γＷ膜トにレジストパターンを形成し、この
レジストパターンをマスクとしてｔ記下地薄膜に所要の
パターンを形成することを特徴とするパターン形成方法
。(1) A resist is applied to the base thin film applied to the substrate surface, and a part of this resist is exposed by irradiating ultraviolet rays or far ultraviolet rays from the E direction through a photomask, and other parts of this resist are exposed to electron beams. A pattern forming method characterized by forming a resist pattern on the base γW film by irradiating and exposing it to light, and using this resist pattern as a mask to form a desired pattern on the base thin film.
の照射とを同時に行なうことを特徴とする特許請求の範
囲第１項記載Ｑパターン形成方法。(2) The method for forming a Q pattern according to claim 1, characterized in that the irradiation with the ultraviolet rays or far ultraviolet rays and the irradiation with the electron beam are carried out simultaneously.
の照射とを前後して行うことを特徴とする特許請求の範
囲第１項記載のパターン形成方法。(3) The pattern forming method according to claim 1, characterized in that the irradiation with the ultraviolet rays or far ultraviolet rays and the irradiation with the electron beam are performed one after the other.
ムの照射とを同時に行ない、かつこの照射の前あるいは
後に電子ビームの照射を行なうことを特徴とする特許請
求の範囲第１項記載のパターン形成方法。(4) Pattern formation according to claim 1, characterized in that the irradiation with the ultraviolet rays or far ultraviolet rays and the irradiation with an electron beam are performed simultaneously, and the irradiation with the electron beam is performed before or after this irradiation. Method.
ターンを形成する工程において該レジストパターン中に
ターゲットパターンを形成し、上記電子ビームの照射に
より露光する際上記ターゲットパターンを用いて露光の
位置合せを行なうことを特徴とする特許請求の範囲第３
項記載のパターン形成方法。(5) In the step of forming a resist pattern by irradiation with ultraviolet rays or deep ultraviolet rays, a target pattern is formed in the resist pattern, and when exposure is performed by irradiation with the electron beam, alignment of exposure is performed using the target pattern. Claim 3 characterized by
The pattern forming method described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58016588A JPS59141230A (en) | 1983-02-02 | 1983-02-02 | Formation of pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58016588A JPS59141230A (en) | 1983-02-02 | 1983-02-02 | Formation of pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59141230A true JPS59141230A (en) | 1984-08-13 |
| JPH0544169B2 JPH0544169B2 (en) | 1993-07-05 |
Family
ID=11920429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58016588A Granted JPS59141230A (en) | 1983-02-02 | 1983-02-02 | Formation of pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59141230A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6373518A (en) * | 1986-09-16 | 1988-04-04 | Matsushita Electronics Corp | Formation of pattern |
| JPH0348253A (en) * | 1989-07-17 | 1991-03-01 | Nippon Telegr & Teleph Corp <Ntt> | Formation of pattern |
| JPH05152199A (en) * | 1991-11-27 | 1993-06-18 | Nec Kansai Ltd | Method for forming resist pattern |
| CN1078741C (en) * | 1995-08-16 | 2002-01-30 | 日本电气株式会社 | Method of forming metal wirings on semiconductor substrate by dry etching |
| CN1080929C (en) * | 1995-06-26 | 2002-03-13 | 现代电子产业株式会社 | Method for forming fine patterns of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51110974A (en) * | 1975-03-25 | 1976-09-30 | Sanyo Electric Co | |
| JPS5655943A (en) * | 1979-10-12 | 1981-05-16 | Fujitsu Ltd | Pattern forming method |
| JPS5676530A (en) * | 1979-11-27 | 1981-06-24 | Fujitsu Ltd | Exposure of resist |
| JPS5712522A (en) * | 1980-06-27 | 1982-01-22 | Hitachi Ltd | Forming method of pattern |
-
1983
- 1983-02-02 JP JP58016588A patent/JPS59141230A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51110974A (en) * | 1975-03-25 | 1976-09-30 | Sanyo Electric Co | |
| JPS5655943A (en) * | 1979-10-12 | 1981-05-16 | Fujitsu Ltd | Pattern forming method |
| JPS5676530A (en) * | 1979-11-27 | 1981-06-24 | Fujitsu Ltd | Exposure of resist |
| JPS5712522A (en) * | 1980-06-27 | 1982-01-22 | Hitachi Ltd | Forming method of pattern |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6373518A (en) * | 1986-09-16 | 1988-04-04 | Matsushita Electronics Corp | Formation of pattern |
| JPH0348253A (en) * | 1989-07-17 | 1991-03-01 | Nippon Telegr & Teleph Corp <Ntt> | Formation of pattern |
| JPH05152199A (en) * | 1991-11-27 | 1993-06-18 | Nec Kansai Ltd | Method for forming resist pattern |
| CN1080929C (en) * | 1995-06-26 | 2002-03-13 | 现代电子产业株式会社 | Method for forming fine patterns of semiconductor device |
| CN1078741C (en) * | 1995-08-16 | 2002-01-30 | 日本电气株式会社 | Method of forming metal wirings on semiconductor substrate by dry etching |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0544169B2 (en) | 1993-07-05 |
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