JPH0544169B2 - - Google Patents

Info

Publication number
JPH0544169B2
JPH0544169B2 JP58016588A JP1658883A JPH0544169B2 JP H0544169 B2 JPH0544169 B2 JP H0544169B2 JP 58016588 A JP58016588 A JP 58016588A JP 1658883 A JP1658883 A JP 1658883A JP H0544169 B2 JPH0544169 B2 JP H0544169B2
Authority
JP
Japan
Prior art keywords
pattern
resist
substrate
thin film
ultraviolet rays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58016588A
Other languages
Japanese (ja)
Other versions
JPS59141230A (en
Inventor
Kazuhiro Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58016588A priority Critical patent/JPS59141230A/en
Publication of JPS59141230A publication Critical patent/JPS59141230A/en
Publication of JPH0544169B2 publication Critical patent/JPH0544169B2/ja
Granted legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/7045Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3174Particle-beam lithography, e.g. electron beam lithography
    • H01J37/3175Projection methods, i.e. transfer substantially complete pattern to substrate

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体素子などを製造する為の基
板上の薄膜面上に施されレジスト膜に、微細なパ
ターンを形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming fine patterns in a resist film applied on a thin film surface of a substrate for manufacturing semiconductor devices and the like.

〔従来技術〕[Prior art]

半導体素子などを製造する際には、極めて微細
なパターンを所定の位置に高精度に形成する必要
があり、これらのパターンは一般にフオトリング
ラフイー技術によつて形成される。
When manufacturing semiconductor devices and the like, it is necessary to form extremely fine patterns at predetermined positions with high precision, and these patterns are generally formed by photolithography technology.

従来のこの種のパターン形成方法を第1図を用
いて説明する。図において、1は半導体ウエハー
などからなる基板で、上面に酸化膜などの下地薄
膜2が施されている。3は下地薄膜2面に施され
たレジストである。次に4はフオトマスクであ
り、ガラス基板5の下面に所要のパターン6が形
成されている。このマスク4の形成は次のように
して行なわれる。即ち、先ずガラス基板5上に付
着された金属薄膜にレジスト塗布後、所要のレジ
ストパターンを形成し、ついで、エツチングレジ
スト剥離後パターン6を形成する。
A conventional pattern forming method of this type will be explained with reference to FIG. In the figure, reference numeral 1 denotes a substrate made of a semiconductor wafer or the like, on which a base thin film 2 such as an oxide film is applied. 3 is a resist applied to two surfaces of the underlying thin film. Next, 4 is a photomask, and a required pattern 6 is formed on the lower surface of the glass substrate 5. Formation of this mask 4 is performed as follows. That is, first, a resist is applied to the metal thin film deposited on the glass substrate 5, a desired resist pattern is formed, and then a pattern 6 is formed after the etching resist is removed.

このようにして形成したフオトマスク4を、第
1図aのように基板1の上部に位置決めして配置
し、上方から矢印Pのように紫外線を照射する。
透過した紫外線によりレジスト3が感光する。次
に、所定の現像液により現像し、同図bのよう
に、レジストパターン7を得る。そしてこのレジ
ストパターン7をマスクにして下地薄膜2をエツ
チングし、同図cのように、パターン8が残つて
形成される。つづいて、レジストパターン7を剥
離除去することにより、所望のパターン8が露出
して得られる。
The photomask 4 thus formed is positioned and placed on the top of the substrate 1 as shown in FIG.
The resist 3 is exposed to the transmitted ultraviolet rays. Next, it is developed with a predetermined developer to obtain a resist pattern 7 as shown in FIG. Using this resist pattern 7 as a mask, the underlying thin film 2 is etched, leaving a pattern 8 as shown in FIG. Subsequently, by peeling and removing the resist pattern 7, a desired pattern 8 is exposed and obtained.

上記のような従来のパターン形成方法を用い
て、例えばマスクROMあるいはマスタスライス
などのパターンを得たい場合には、毎回紫外線露
光用マスクを作成する必要があつた。この紫外線
マスクは作成工程が複雑であり、多大の時間を要
していた。したがつて、工期が長くかかり、費用
が高くなつていた。さらに、微細パターンの場
合、これをフオトマスクで作成するには非常に困
難であつたり、シヤープなパターンが得られない
という欠点があつた。
When it is desired to obtain a pattern such as a mask ROM or a master slice using the conventional pattern forming method as described above, it has been necessary to create a mask for ultraviolet exposure each time. The manufacturing process for this ultraviolet mask was complicated and took a lot of time. Therefore, the construction period was long and the cost was high. Furthermore, in the case of fine patterns, it is very difficult to create them using a photomask, and there are disadvantages in that a sharp pattern cannot be obtained.

〔発明の概要〕[Summary of the invention]

この発明は、上記のような従来方法の欠点を除
去するためになされたもので、基板のレジストの
露光をその一部を紫外線によつて露光し、レジス
トパターンを形成するとともにこのレジストパタ
ーン中にダーゲツトパターンを形成し、このター
ゲツトパターンで位置合わせをした後、他部を電
子ビームで露光しレジストパターンを形成するこ
とにより、微細パターンが短期間に、しかも精度
よく得られるパターン形成方法を提供することを
目的としている。
This invention was made to eliminate the drawbacks of the conventional method as described above, and involves exposing a portion of the resist on a substrate to ultraviolet rays to form a resist pattern. Provides a pattern forming method that allows fine patterns to be obtained in a short period of time and with high precision by forming a target pattern, aligning with this target pattern, and then exposing other parts with an electron beam to form a resist pattern. It is intended to.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の実施例を図について説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

第2図は本発明の一実施例によるパターン形成
方法を示し、図において、第1図と同一符号は同
一のものを示し、9はフオトマスクであり、これ
は次のような構成である。即ち、10は所要のパ
ターンで、11は遮光用パターンであり、これら
は共にガラス基板層5の下面に形成されている。
なおこのフオトマスク9は、上記従来のフオトマ
スク4と同様にして形成する。
FIG. 2 shows a pattern forming method according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. That is, 10 is a required pattern and 11 is a light shielding pattern, both of which are formed on the lower surface of the glass substrate layer 5.
Note that this photomask 9 is formed in the same manner as the conventional photomask 4 described above.

次に第2図を用いて本発明の一実施例によるパ
ターン形成方法について説明する。
Next, a pattern forming method according to an embodiment of the present invention will be explained using FIG.

半導体ウエハーからなる基板1上面には、酸化
膜などの下地薄膜2を施し、その上にレジスト
3、例えばAZ1470(SHIPLEY社製)、を約4000
Åの厚さに塗布する。
A thin base film 2 such as an oxide film is applied to the upper surface of a substrate 1 made of a semiconductor wafer, and a resist 3 such as AZ1470 (manufactured by SHIPLEY) is applied thereon to a thickness of about 4,000 yen.
Apply to a thickness of Å.

そして第2図aに示すように、基板1の上部に
フオトマスク9を位置決めして配置し、上方から
矢印Pのように紫外線を照射する。紫外線はHg
ランプ光源からの平行光線を使用し、約3秒の照
射を行う。この時遮光用パターン11の部分では
紫外線は遮へいされ、所要のパターン10のみが
レジスト3に転写される。露光完了後所定の現像
液、例えばSHIPLEY社製MF312で現像、洗浄
し、乾燥するとレジストパターン7および露光位
置決めのためのターゲツトパターンであるレジス
タマーク12が得られる(同図b参照)。
Then, as shown in FIG. 2a, a photomask 9 is positioned and placed on the top of the substrate 1, and ultraviolet rays are irradiated from above in the direction of arrow P. Ultraviolet light is Hg
Irradiation is performed for about 3 seconds using parallel light from a lamp light source. At this time, ultraviolet rays are blocked in the light-shielding pattern 11, and only the desired pattern 10 is transferred onto the resist 3. After the exposure is completed, it is developed with a predetermined developer, for example MF312 manufactured by SHIPLEY, washed, and dried to obtain a resist pattern 7 and a register mark 12 which is a target pattern for positioning the exposure (see FIG. 5B).

次に上述の過程で形成されたレジスタマーク1
2により正確に位置決めされた電子ビームにより
同図Cに矢印Qで示すようにレジスト3に露光を
行う。電子ビームの露光強度は例えば4×10-4
C/cm2とする。この電子ビームによりレジスト3
に露光する部分は、例えばマスクROMのROM
の部分、あるいは微細パターン、又はマスタース
ライスの部分とする。
Next, register mark 1 formed in the above process
The resist 3 is exposed to light by the accurately positioned electron beam 2 as shown by the arrow Q in FIG. The exposure intensity of the electron beam is, for example, 4×10 -4
C/ cm2 . With this electron beam, the resist 3
The part exposed to light is, for example, the ROM of the mask ROM.
, a fine pattern, or a master slice.

電子ビーム露光完了後、所定の現像液、例えば
SHIPLEY社製MF312で現像し、洗浄を行えば、
同図dで示すように微細なネガ型レジズトパター
ン13が得られる。ノボラツク系樹脂に過度な電
子ビームを照射するとネガ型パターンが得られる
ことが知られている。この得られたレジストパタ
ーン13をマスクにして、下地薄膜2のエツチン
グを行なう(同図e参照)。この時のエツチング
条件は、例えばプラズマ装置によりフレオンガス
中で出力200W、ガス圧0.1Torrで行なつた。つ
づいて、レジストパターン13を剥離除去すれ
ば、同図fに示すように、所要のパターン14が
得られる。
After completing the electron beam exposure, a prescribed developer, e.g.
If you develop it with SHIPLEY MF312 and wash it,
A fine negative resist pattern 13 is obtained as shown by d in the same figure. It is known that a negative pattern can be obtained by irradiating a novolac resin with an excessive electron beam. Using the obtained resist pattern 13 as a mask, the underlying thin film 2 is etched (see e in the same figure). The etching conditions at this time were, for example, a plasma device in Freon gas with an output of 200 W and a gas pressure of 0.1 Torr. Subsequently, by peeling and removing the resist pattern 13, a desired pattern 14 is obtained, as shown in FIG.

このようにして得られたパターン14は、角部
の切れがよく、非常に鋭くてシヤープであつた。
The pattern 14 thus obtained had well-cut corners and was very sharp.

前記従来の紫外線露光のみによるパターン形成
方法では全品種、全露光工程について、それぞれ
フオトマスクを作成する必要があつたが、本発明
の方法によれば特定部分は電子ビームの露光によ
り形成できるので、複雑で面倒なフオトマスクの
数を減少することができ、工期が短縮され、生産
性が向上する。また、得られたパターンは鋭くて
精度のよいものとなる。
In the conventional pattern forming method using only ultraviolet ray exposure, it was necessary to create photomasks for all types of products and for all exposure steps, but according to the method of the present invention, specific parts can be formed by electron beam exposure, making it less complicated. This reduces the number of troublesome photomasks, shortens production time, and improves productivity. Furthermore, the resulting pattern is sharp and accurate.

また、従来のレジスト3は、紫外線に対しては
高感度、高解像度であつても、電子線に対しては
感度、解像度に問題があるものが多かつた。しか
し、本発明では、上記のようにノボラツク樹脂を
レジスト3に用いたので、電子線に対しても高解
像度となり、容易に高精度に微細パターンが得ら
れる。さらに、このレジストは耐プラズマ性を有
しているので、下地薄膜2も容易にドライエツチ
ングでき、微細パターンを形成しやすい利点があ
る。
Further, even though the conventional resist 3 has high sensitivity and high resolution to ultraviolet rays, many of them have problems in sensitivity and resolution to electron beams. However, in the present invention, since novolak resin is used for the resist 3 as described above, the resolution is high even with respect to electron beams, and a fine pattern can be easily obtained with high precision. Furthermore, since this resist has plasma resistance, the base thin film 2 can also be easily dry etched, which has the advantage of making it easy to form fine patterns.

なおまた、上記実施例ではフオトマスク9に紫
外線を制限するのに遮へいパターン11を設けた
が、この代りに、アパチヤなどの絞りにより紫外
線の透過を制限するようにしてもよい。また上記
実施例では紫外線による方法について述べたが、
紫外線による方法でもよく、同様の効果を奏す
る。
Furthermore, in the above embodiment, the photomask 9 is provided with the shielding pattern 11 to limit ultraviolet rays, but instead of this, a diaphragm such as an aperture may be used to limit the transmission of ultraviolet rays. Furthermore, in the above embodiment, the method using ultraviolet rays was described, but
A method using ultraviolet rays may also be used, and the same effect can be achieved.

またさらに、上記実施例では、基板1面の下地
膜として酸化膜の例を示したが、導体膜の場合に
も適用でき、この場合、基板としては石英やガラ
ス材などであつても本発明を適用できるものであ
る。
Furthermore, in the above embodiments, an oxide film is used as the base film on one substrate, but it can also be applied to a conductor film, and in this case, even if the substrate is made of quartz or glass, the present invention can be applied.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、基板のレジ
ストの露光を、一部において紫外線の照射により
行い、レジストパターンを形成するとともにこの
レジストパターン中にターゲツトパターンを形成
し、このターゲツトパターンで位置合わせをし
て、他部を電子ビームで照射してレジストパター
ンを形成するようにしたので、フオトマスクの枚
数が減少でき、しかも微細パターンが短期間に精
度よく得られ、生産性が向上する効果がある。
As described above, according to the present invention, a part of the resist on the substrate is exposed to ultraviolet rays to form a resist pattern, a target pattern is formed in this resist pattern, and alignment is performed using this target pattern. Since the resist pattern is formed by irradiating other parts with an electron beam, the number of photomasks can be reduced, and fine patterns can be obtained with high accuracy in a short period of time, which has the effect of improving productivity. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のパターン形成方法を工程順に示
す基板部とマスク部の断面図、第2図はこの発明
の一実施例によるパターン形成方法を工程順に示
す基板部とマスク部の断面図である。 図において、1は半導体ウエハ(基板)、2は
下地薄膜、3はレジスト、7,13はレジストパ
ターン、12はレジスタマーク(ターゲツトパタ
ーン)、9はフオトマスク、14は所要のパター
ンである。なお図中同一符号は同一又は相当部分
を示す。
FIG. 1 is a sectional view of a substrate part and a mask part showing a conventional pattern forming method in order of process, and FIG. 2 is a sectional view of a substrate part and a mask part showing a pattern forming method according to an embodiment of the present invention in order of steps. . In the figure, 1 is a semiconductor wafer (substrate), 2 is a base thin film, 3 is a resist, 7 and 13 are resist patterns, 12 is a register mark (target pattern), 9 is a photomask, and 14 is a required pattern. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】 1 次の工程を有することを特徴とするパターン
形成方法 (1) 基板上面に設けられた下地薄膜上にレジスト
を塗布する工程、 (2) 上記レジストの一部に紫外線を照射、露光
し、レジストパターンおよびターゲツトパター
ンを形成する工程、 (3) 上記ターゲツトパターンを用いて位置合せ
後、上記レジストパターンの他部に電子ビーム
を照射、露光し、レジストパターンを形成する
工程、 (4) 上記レジストパターンをマスクとして、上記
下地薄膜にパターンを形成する工程。
[Claims] 1. A pattern forming method characterized by comprising the following steps: (1) applying a resist onto a base thin film provided on the upper surface of a substrate; (2) irradiating a portion of the resist with ultraviolet rays; (3) After alignment using the target pattern, irradiating and exposing other parts of the resist pattern with an electron beam to form a resist pattern; (4) A step of forming a pattern on the base thin film using the resist pattern as a mask.
JP58016588A 1983-02-02 1983-02-02 Formation of pattern Granted JPS59141230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58016588A JPS59141230A (en) 1983-02-02 1983-02-02 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58016588A JPS59141230A (en) 1983-02-02 1983-02-02 Formation of pattern

Publications (2)

Publication Number Publication Date
JPS59141230A JPS59141230A (en) 1984-08-13
JPH0544169B2 true JPH0544169B2 (en) 1993-07-05

Family

ID=11920429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58016588A Granted JPS59141230A (en) 1983-02-02 1983-02-02 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS59141230A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2617923B2 (en) * 1986-09-16 1997-06-11 松下電子工業株式会社 Pattern formation method
JPH0348253A (en) * 1989-07-17 1991-03-01 Nippon Telegr & Teleph Corp <Ntt> Formation of pattern
JPH05152199A (en) * 1991-11-27 1993-06-18 Nec Kansai Ltd Method for forming resist pattern
KR0172237B1 (en) * 1995-06-26 1999-03-30 김주용 Method of manufacturing micropattern of semiconductor device
JP2924723B2 (en) * 1995-08-16 1999-07-26 日本電気株式会社 Dry etching method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51110974A (en) * 1975-03-25 1976-09-30 Sanyo Electric Co
JPS5655943A (en) * 1979-10-12 1981-05-16 Fujitsu Ltd Pattern forming method
JPS5676530A (en) * 1979-11-27 1981-06-24 Fujitsu Ltd Exposure of resist
JPS5712522A (en) * 1980-06-27 1982-01-22 Hitachi Ltd Forming method of pattern

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51110974A (en) * 1975-03-25 1976-09-30 Sanyo Electric Co
JPS5655943A (en) * 1979-10-12 1981-05-16 Fujitsu Ltd Pattern forming method
JPS5676530A (en) * 1979-11-27 1981-06-24 Fujitsu Ltd Exposure of resist
JPS5712522A (en) * 1980-06-27 1982-01-22 Hitachi Ltd Forming method of pattern

Also Published As

Publication number Publication date
JPS59141230A (en) 1984-08-13

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