JPH0471331B2 - - Google Patents

Info

Publication number
JPH0471331B2
JPH0471331B2 JP59226361A JP22636184A JPH0471331B2 JP H0471331 B2 JPH0471331 B2 JP H0471331B2 JP 59226361 A JP59226361 A JP 59226361A JP 22636184 A JP22636184 A JP 22636184A JP H0471331 B2 JPH0471331 B2 JP H0471331B2
Authority
JP
Japan
Prior art keywords
electron beam
positive
pattern
positive photoresist
beam exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59226361A
Other languages
Japanese (ja)
Other versions
JPS61102739A (en
Inventor
Hiroshi Yamashita
Yoshihiro Todokoro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP59226361A priority Critical patent/JPS61102739A/en
Publication of JPS61102739A publication Critical patent/JPS61102739A/en
Publication of JPH0471331B2 publication Critical patent/JPH0471331B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/7045Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電子ビーム露光を用いた微細パター
ン形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming fine patterns using electron beam exposure.

従来例の構成とその問題点 半導体素子の微細化が進むにつれて、微細なパ
ターンを形成するために電子ビーム露光が用いら
れるようになつた。電子ビーム露光は微細なパタ
ーンを描画できるという長所を持つているが、反
面、その処理に長時間を要し、生産性が低いとい
う欠点を持つ。そこで、この欠点を解決するため
に光露光と電子ビーム露光とを併用するプロセス
が提案されている。たとえば、ポジ形ホトレジス
トを用いてあらかじめ、紫外光露光で比較的大き
なパターンを露光し、ついで、微細パターンは電
子ビーム露光で形成する方法がある。しかし、ポ
ジ形ホトレジスト単層を電子ビーム露光に用いる
場合には、解像度が低いために、微細化が難かし
いという問題がある。
Conventional Structures and Their Problems As the miniaturization of semiconductor devices progresses, electron beam exposure has come to be used to form fine patterns. Electron beam exposure has the advantage of being able to draw fine patterns, but has the disadvantage of requiring a long processing time and low productivity. Therefore, in order to solve this drawback, a process has been proposed that uses both light exposure and electron beam exposure. For example, there is a method in which a relatively large pattern is first exposed to ultraviolet light using a positive photoresist, and then a fine pattern is formed by electron beam exposure. However, when using a positive photoresist single layer for electron beam exposure, there is a problem in that miniaturization is difficult due to low resolution.

発明の目的 本発明は上記の問題を解決するものであり、本
発明の目的は紫外光露光と電子ビーム露光を併用
することにより、生産性の向上を図り、しかも微
細なパターンを形成することである。
Purpose of the Invention The present invention solves the above problems, and the purpose of the present invention is to improve productivity by using ultraviolet light exposure and electron beam exposure in combination, and to form fine patterns. be.

発明の構成 本発明は基板上に、ポジ形電子ビーム露光用レ
ジストを形成し、その上にポジ形ホトレジストを
形成する工程、前記ポジ形ホトレジストを選択紫
外光露光し、現像する工程、前記ポジ形ホトレジ
ストの現像パターンをマスクとして全面遠紫外光
露光する工程、前記ポジ形ホトレジストの現像パ
ターンを除去する工程、および前記ポジ形ホトレ
ジストを電子ビーム露光し、現像する工程を備え
たパターン形成方法であり、これにより、サブミ
クロン単位の微細パターンの形成が容易に可能で
ある。
Structure of the Invention The present invention provides a step of forming a positive electron beam exposure resist on a substrate and forming a positive photoresist thereon, a step of selectively exposing the positive photoresist to ultraviolet light, and developing the positive photoresist. A pattern forming method comprising the steps of exposing the entire surface to deep ultraviolet light using a developed pattern of photoresist as a mask, removing the developed pattern of the positive photoresist, and exposing the positive photoresist to an electron beam and developing it, Thereby, it is possible to easily form a fine pattern on a submicron scale.

実施例の説明 以下にGaAsFETのパターンを描画する場合を
例として本発明の実施例を第1図〜第6図の工程
順図に従つて説明する。
DESCRIPTION OF THE EMBODIMENTS Examples of the present invention will be described below with reference to the process diagrams of FIGS. 1 to 6, taking as an example the case of drawing a GaAsFET pattern.

まず、第1図のように、Si基板1上にポジ形電
子ビーム露光用レジストのポリメチルメタクリレ
ート(PMMA)2を05μmの厚さに塗布した後、
170℃で30分間プリベークを行なう。ついで、こ
のPMMA2の上に、東京応化製の製品名OFPR
800で知られるノボラツク型ポジ形ホトレジス
ト3を1μm塗布し、85℃で30分間プリベークす
る。次に第2図のように、ゲートパツド等の比較
的大きな開口パターン4を紫外光露光し、有機ア
ルカリ系現像液、たとえば、東京応化製の製品名
NMD−3で知られる専用現像液を用いて1分間
現像する。その後、第3図のように、このノボラ
ツク型ポジ形レジスト3をマスクとして遠紫外光
(波長250nm,17mW/cm2)を5分間全面照射す
る。その結果、ゲートパツド部のPMMA2がノ
ボラツク型ポジ形レジスト3の開口パターン4の
形状に露光される。次に、再び、専用現像液
(NMD−3)中に浸して、ノボラツク型ポジ形
レジスト3を除去すると、第4図のように、遠紫
外光露光された開口用露光部5をもつPMMA2
が露出する。なお、紫外光露光後のノボラツク型
ポジ形レジスト3は、専用現像液のNMD−3に
10分以上浸せば容易に除去される。ついで、第5
図のように、PMMA2を64μc/cm2で開口用露光
部5に接する微細開口用露光部6を電子ビーム露
光した後、メチルイソブチルケトン(MIBK)で
4分間現像を行ない、第6図のように、ゲートパ
ツド部および微細パターンの開口7を有する所定
の回路パターンを得ることができる。
First, as shown in Fig. 1, polymethyl methacrylate (PMMA) 2, which is a resist for positive electron beam exposure, is applied to a thickness of 0.5 μm on a Si substrate 1.
Pre-bake at 170℃ for 30 minutes. Next, on top of this PMMA2, apply the product name OFPR manufactured by Tokyo Ohka Co., Ltd.
A novolak type positive photoresist 3 known as 800 is applied to a thickness of 1 μm and prebaked at 85° C. for 30 minutes. Next, as shown in FIG. 2, a relatively large opening pattern 4 such as a gate pad is exposed to ultraviolet light, and an organic alkaline developer, for example, manufactured by Tokyo Ohka Co., Ltd.
Develop for 1 minute using a special developer known as NMD-3. Thereafter, as shown in FIG. 3, the entire surface is irradiated with deep ultraviolet light (wavelength 250 nm, 17 mW/cm 2 ) for 5 minutes using this novolak positive resist 3 as a mask. As a result, the PMMA 2 in the gate pad portion is exposed in the shape of the opening pattern 4 of the novolak positive resist 3. Next, the novolak type positive resist 3 is removed by immersing it in a special developer (NMD-3) again, and as shown in FIG.
is exposed. In addition, after exposure to ultraviolet light, the novolak type positive resist 3 is treated with the special developer NMD-3.
It is easily removed if soaked for 10 minutes or more. Then, the fifth
As shown in the figure, the fine aperture exposure area 6 in contact with the aperture exposure area 5 of PMMA2 was exposed to electron beam at 64 μc/cm 2 , and then developed with methyl isobutyl ketone (MIBK) for 4 minutes, as shown in Figure 6. In addition, a predetermined circuit pattern having a gate pad portion and a finely patterned opening 7 can be obtained.

発明の効果 本発明は、連続形成した2層からなるポジ形レ
ジストを用い、しかも紫外光露光と電子ビーム露
光とを併用することにより、高い生産性でサブミ
クロンの微細パターンを形成することが可能であ
る。
Effects of the Invention The present invention makes it possible to form submicron fine patterns with high productivity by using a positive resist consisting of two consecutively formed layers and by using UV light exposure and electron beam exposure in combination. It is.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第6図は、本発明の実施例を説明する
ための工程順図である。 1……Si基板、2……ポジ形電子ビームレジス
ト(PMMA)、3……ノボラツク型ポジ形ホトレ
ジスト、4……開口パターン、5,6……開口用
露光部、7……開口。
FIGS. 1 to 6 are process diagrams for explaining an embodiment of the present invention. 1...Si substrate, 2...Positive electron beam resist (PMMA), 3...Novolak positive photoresist, 4...Aperture pattern, 5, 6...Exposure section for opening, 7...Aperture.

Claims (1)

【特許請求の範囲】[Claims] 1 基板上に、ポジ形電子ビーム露光用レジスト
を形成し、その上にポジ形ホトレジストを形成す
る工程、前記ポジ形ホトレジストを選択紫外光露
光し、現像する工程、前記ポジ形ホトレジストの
現像パターンをマスクとして全面遠紫外光露光す
る工程、前記ポジ形ホトレジストの現像パターン
を除去する工程、および前記ポジ形電子ビーム露
光用レジストを電子ビーム露光し、現像する工程
を備えたパターン形成方法。
1. A step of forming a positive electron beam exposure resist on a substrate and forming a positive photoresist thereon, a step of selectively exposing the positive photoresist to ultraviolet light and developing it, and developing a developed pattern of the positive photoresist. A pattern forming method comprising the steps of exposing the entire surface to deep ultraviolet light as a mask, removing the developed pattern of the positive photoresist, and exposing and developing the positive electron beam exposure resist.
JP59226361A 1984-10-26 1984-10-26 Method of forming pattern Granted JPS61102739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59226361A JPS61102739A (en) 1984-10-26 1984-10-26 Method of forming pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59226361A JPS61102739A (en) 1984-10-26 1984-10-26 Method of forming pattern

Publications (2)

Publication Number Publication Date
JPS61102739A JPS61102739A (en) 1986-05-21
JPH0471331B2 true JPH0471331B2 (en) 1992-11-13

Family

ID=16843942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59226361A Granted JPS61102739A (en) 1984-10-26 1984-10-26 Method of forming pattern

Country Status (1)

Country Link
JP (1) JPS61102739A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2617923B2 (en) * 1986-09-16 1997-06-11 松下電子工業株式会社 Pattern formation method
JP2659203B2 (en) * 1988-01-27 1997-09-30 日本電気株式会社 Pattern formation method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145125A (en) * 1982-02-24 1983-08-29 Nec Corp Formation of resist mask

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145125A (en) * 1982-02-24 1983-08-29 Nec Corp Formation of resist mask

Also Published As

Publication number Publication date
JPS61102739A (en) 1986-05-21

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