JP2659203B2 - Pattern formation method - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element pattern.

[Conventional technology]

In recent years, semiconductor elements have been highly integrated and miniaturized, and a charged beam drawing apparatus or an optical reduction projection exposure apparatus having a high-precision transfer performance when forming an element pattern on a semiconductor wafer has been used. FIG. 3 is a schematic configuration diagram of a charged beam drawing apparatus, in which the surface of a wafer 1 placed on a stage 11 is irradiated with an electron or ion beam from an electron gun 12 converged and deflected by an electron lens 13. To form a pattern. FIG. 4 is a schematic view of the configuration of a light reduction projection exposure apparatus, in which a pattern formed on a mask 14 is imaged on the surface of a wafer 1 by an optical lens 17 while limiting an irradiation area of a light source 16 with a shielding plate 15. Then, the pattern is formed.

[Problems to be solved by the invention]

In the conventional package forming method described above, the charged beam drawing apparatus shown in FIG. 3 can form a very fine pattern of about 0.3 μm, but not only consumes a lot of time for drawing but also is very expensive. Since it is an apparatus, there is a problem in terms of productivity.

Further, the optical reduction projection exposure apparatus shown in FIG. 4 has high accuracy and high productivity, but has a problem that a fine pattern of about 0.3 μm cannot be formed.

In order to compensate for the disadvantages of each other, a so-called hybrid exposure apparatus combining a charged beam drawing apparatus and a light reduction projection exposure apparatus has been proposed. That is, in this apparatus, as shown in FIG. 5 (a), the pattern formation is performed by using the alignment mark 2A provided for each unit chip of the wafer for the drawing of the charged beam and the exposure for the light reduction projection.

However, in this device, as shown in FIG.
Exposure distortion A present in the charged beam writing system (shown by broken lines)
And the exposure distortion B (shown by a solid line) existing in the light reduction projection exposure apparatus usually do not coincide with each other, and conversely, errors tend to occur between the two patterns, resulting in a problem that the pattern formation accuracy is reduced. .

An object of the present invention is to provide a pattern forming method capable of improving pattern forming accuracy in the above-described hybrid exposure apparatus and obtaining high accuracy and high productivity.

[Means for solving the problem]

The pattern forming method according to the present invention is directed to a semiconductor device using a light reduction projection exposure apparatus for reducing and transferring a mask pattern onto a semiconductor wafer and a charged beam drawing apparatus for drawing a pattern by scanning a charged beam on the semiconductor wafer. In a pattern forming method for forming a pattern on a wafer, a predetermined pattern is transferred to a first region on the substrate by one-time exposure of the optical reduction projection device, and the first region is divided into a plurality of second regions. Forming an alignment mark for each of the second areas by subdividing the area into a plurality of areas, and using the alignment mark provided for each of the second areas to form a pattern by the charged beam drawing apparatus for each of the second areas. And a step of drawing.

[Action]

In the above-described method, drawing by the charged beam drawing apparatus is performed for each fine region in the pattern formed by the light reduction projection exposure apparatus, and the charged beam having the exposure distortion that follows the exposure distortion of the light reduction projection exposure apparatus. A beam drawing pattern is formed.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a view for explaining a method of one embodiment of the present invention, wherein FIG. 1 (a) is an overall plan view of a wafer, and FIG.
FIG. 3 is a plan view of the unit chip after the completion of the light reduction projection exposure, and FIG. 3C is a plan view of the unit chip after drawing the charged beam.

In this pattern forming method, first, as shown in FIG. 1 (a), a pattern 3 having a relatively large size is exposed on a wafer 1 for each unit chip using an optical reduction projection device. At this time,
As shown in FIG. 1B, a plurality of alignment marks 2 for drawing a charged beam are formed for each exposure field obtained by further subdividing each unit chip. The alignment mark 2 for drawing a charged beam is 0.5 mm to 2
It is good to arrange at intervals of mm. Of course, the optimum spacing needs to be varied depending on the size of the exposure field (typically 6mm to 14mm).

Then, as shown in FIG. 1 (c), a charged beam drawing 4
To form a fine pattern.

Therefore, according to this pattern forming method, there is a need for the method shown in FIG. 5B between the optical reduction projection exposure apparatus and the charged beam drawing apparatus.
Even if there is a difference in exposure distortion as shown in the above, since the exposure by the charged beam lithography system is performed by changing the alignment mark for each fine area in the unit chip, the influence of both exposure distortions is extremely small. Therefore, there is no occurrence of a pattern error which is a problem in practical use.

Thereby, it is possible to realize a preferable pattern formation utilizing the high productivity of the light reduction projection exposure apparatus and the high accuracy of the charged beam drawing apparatus.

FIG. 2 is a diagram for explaining another embodiment of the present invention, and FIGS. 2 (a) to 2 (c) are diagrams similar to FIGS. 1 (a) to 1 (c), respectively.

In this embodiment, as shown in FIG. 2 (a), a wafer is exposed by an optical reduction projection exposure apparatus, and at the same time, a plurality of alignments are performed for each unit chip 3 as shown in FIG. 2 (b). The mark 2 is formed. Here, the alignment mark 2 is formed only at a necessary place in the unit chip. At other locations, charged beam drawing 4 is performed as shown in FIG. 2 (c) by using data of a designated alignment mark conventionally prepared on the basis of alignment on a wafer or chip basis.

By doing so, only the places where the exposure distortion between the light reduction projection exposure and the charged beam writing is likely to be a problem are corrected, and the others are drawn using typical mark data, so that the drawing time is reduced. There is an advantage that the conversion is achieved.

〔The invention's effect〕

As described above, the present invention first forms a plurality of fine charged beam positioning marks at the time of pattern transfer by an optical reduction projection exposure apparatus, and thereafter uses the positioning marks to form a desired charged beam drawing apparatus. Since the pattern is drawn, drawing by the charged beam drawing apparatus is performed for each fine area in the pattern formed by the light reduction projection exposure apparatus. And the exposure distortion of both is automatically corrected to be as small as possible, and the effect of significantly improving the pattern transfer accuracy can be obtained.

[Brief description of the drawings]

FIG. 1 is a view for explaining a pattern forming method according to an embodiment of the present invention. FIG. 1 (a) is a plan view of a wafer, and FIG. 1 (b) is a unit when light reduction projection exposure is completed. FIG. 2 (c) is an enlarged plan view of the chip, FIG. 2 (c) is an enlarged plan view of the unit chip at the time of completion of the drawing of the charged beam, and FIG. 2 is a view for explaining another method of the present invention. ) To (c) are the same as FIGS. 1 (a) to (c), respectively, FIG. 3 is a schematic diagram of a general charged beam drawing apparatus, and FIG. FIG. 5 is a schematic diagram for explaining the problem of the conventional method. FIG. 5A is a plan view of a wafer, and FIG. 5B is a plan view of exposure distortion in a unit chip. 1 wafer 2 alignment mark 3 light reduction exposure pattern 4 charged beam drawing pattern 11
... stage, 12 ... electron gun, 13 ... electron lens, 14 ...
Mask, 15 Shield plate, 16 Light source, 17 Optical lens.

Claims (1)

(57) [Claims] An optical reduction projection exposure apparatus for reducing and transferring a mask pattern onto a semiconductor wafer, and a charged beam writing apparatus for writing a pattern by scanning a charged beam on the semiconductor wafer are used on a semiconductor wafer. In a pattern forming method for forming a pattern, a predetermined pattern is transferred to a first region on the substrate by a single exposure of the optical reduction projection device, and the first region is transferred to a plurality of second regions. Subdividing and forming an alignment mark for each of the second areas, and drawing a pattern by the charged beam writing apparatus for each of the second areas using an alignment mark provided for each of the second areas And a step of forming a pattern.