JPH01191416A - Pattern forming method - Google Patents
Pattern forming methodInfo
- Publication number
- JPH01191416A JPH01191416A JP63014737A JP1473788A JPH01191416A JP H01191416 A JPH01191416 A JP H01191416A JP 63014737 A JP63014737 A JP 63014737A JP 1473788 A JP1473788 A JP 1473788A JP H01191416 A JPH01191416 A JP H01191416A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- charged beam
- exposure
- optical reduction
- reduction projection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 13
- 230000003287 optical effect Effects 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000001459 lithography Methods 0.000 abstract description 15
- 238000006722 reduction reaction Methods 0.000 description 18
- 235000012431 wafers Nutrition 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 230000007261 regionalization Effects 0.000 description 4
- 238000007540 photo-reduction reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/7045—Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electron Beam Exposure (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係り、特に素子パター
ンの形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an element pattern.
近年、半導体素子の高集積化、微細化が進められ、半導
体ウェハ上に素子パターンを形成する際に高精度な転写
性能を有する荷電ビーム描画装置、或いは光縮小投影露
光装置が用いられている。第3図は荷電ビーム描画装置
の概略構成図であり、ステージ11上に載置されたウェ
ハ1の表面に、電子レンズ13で収束されかつ偏向され
た電子銃12からの電子又はイオンビームを照射してパ
ターン形成を行っている。また、第4図は光縮小投影露
光装置の概略構成図であり、マスク14に形成したパタ
ーンを、遮蔽Fi15で光源16の照射領域を限定しな
がら光学レンズ17によりウェハ1の表面に結像させて
パターン形成を行っている。2. Description of the Related Art In recent years, semiconductor devices have become highly integrated and miniaturized, and charged beam lithography devices or optical reduction projection exposure devices that have highly accurate transfer performance are used to form device patterns on semiconductor wafers. FIG. 3 is a schematic configuration diagram of a charged beam lithography apparatus, in which the surface of a wafer 1 placed on a stage 11 is irradiated with an electron or ion beam from an electron gun 12 that is focused and deflected by an electron lens 13. The pattern is formed by FIG. 4 is a schematic configuration diagram of an optical reduction projection exposure apparatus, in which a pattern formed on a mask 14 is imaged on the surface of the wafer 1 by an optical lens 17 while limiting the irradiation area of the light source 16 with a shielding Fi 15. Pattern formation is performed using
上述した従来のパッケージ形成方法において、第3図の
荷電ビーム描画装置では、0.3μm前後の非常に微細
なパターンの形成が可能であるが描画に多大な時間を費
やすだけでなく、非常に高価な装置であるため、生産性
の点で問題がある。In the conventional package forming method described above, the charged beam lithography system shown in Fig. 3 can form very fine patterns of around 0.3 μm, but it not only takes a lot of time for lithography but is also very expensive. Since it is a simple device, there is a problem in terms of productivity.
また、第4図の光縮小投影露光装置では、高精度、高生
産性を有しているが、0.3μm前後の微細パターンを
形成することができないという問題がある。Further, although the optical reduction projection exposure apparatus shown in FIG. 4 has high precision and high productivity, it has a problem in that it cannot form fine patterns of around 0.3 μm.
そこで、互いの短所を補うために、荷電ビーム描画装置
と光縮小投影露光装置を組み合わせた、いわゆるハイブ
リッド露光装置が提案されてきている。即ち、この装置
では、第5図(a)に示すように、荷電ビーム描画と光
縮小投影露光を夫々ウェハの単位チップ毎に設けたアラ
イメントマーク2Aを共用してパターン形成を行ってい
る。Therefore, in order to compensate for each other's shortcomings, a so-called hybrid exposure apparatus, which combines a charged beam lithography apparatus and an optical reduction projection exposure apparatus, has been proposed. That is, in this apparatus, as shown in FIG. 5(a), pattern formation is performed by using an alignment mark 2A provided for each unit chip of the wafer for both charged beam writing and optical reduction projection exposure.
しかしながらこの装置では、第5図(b)のように、荷
電ビーム描画装置に存在する露光歪A(破線で示す)と
、光縮小投影露光装置に存在する露光歪B(実線で示す
)が通常では一致しないため、逆に両者のパターン間に
誤差が生じ易く、パターンの形成精度が低下してしまう
という問題がある。However, in this apparatus, as shown in FIG. 5(b), the exposure distortion A (shown by the broken line) present in the charged beam lithography system and the exposure distortion B (shown by the solid line) present in the optical reduction projection exposure system are normal. Since they do not match, there is a problem in that errors tend to occur between the two patterns, resulting in a decrease in pattern formation accuracy.
本発明は上述したハイブリッド露光装置におけるパター
ンの形成精度を向上して、高精度かつ高生産性を得るこ
とができるパターン形成方法を提供することを目的とし
ている。An object of the present invention is to provide a pattern forming method that can improve the pattern forming accuracy in the above-mentioned hybrid exposure apparatus and achieve high accuracy and high productivity.
[課題を解決するための手段]
本発明のパターン形成方法は、先に光縮小投影露光装置
によりパターン転写すると同時に、各露光フィールド内
に複数個の荷電ビーム用位置決めマークを形成し、その
後この位置決めマークを利用して荷電ビーム描画装置に
より所望パターンを描画して所要のパターンを得ている
。[Means for Solving the Problems] In the pattern forming method of the present invention, a pattern is first transferred using an optical reduction projection exposure device, and at the same time, a plurality of positioning marks for a charged beam are formed in each exposure field, and then the positioning marks are A desired pattern is drawn by a charged beam drawing device using the mark to obtain a desired pattern.
〔作用]
上述した方法では、光縮小投影露光装置により形成され
たパターン内で微細領域毎に荷電ビーム描画装置での描
画を行うことになり、光縮小投影露光装置の露光歪に追
従した露光歪を有する荷電ビーム描画パターンを形成す
る。[Function] In the above-mentioned method, the pattern formed by the optical reduction projection exposure device is subjected to writing using a charged beam drawing device for each fine region, so that exposure distortion that follows the exposure distortion of the optical reduction projection exposure device is generated. A charged beam writing pattern is formed.
[実施例] 次に、本発明を図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.
第1図は、本発明の一実施例方法を説明するための図で
あり、同図(a)はウェハΦ全体平面図。FIG. 1 is a diagram for explaining a method according to an embodiment of the present invention, and FIG. 1(a) is a plan view of the entire wafer Φ.
同図(b)は光縮小投影露光終了後の単位チップの平面
図、同図(c)は荷電ビーム描画後の単位チップの平面
図である。FIG. 5B is a plan view of the unit chip after optical reduction projection exposure, and FIG. 1C is a plan view of the unit chip after charged beam drawing.
このパターン形成方法では、先ず第1図(a)のように
、光縮小投影装置を用いてウェハ1に比較的大きな寸法
のパターン3を単位チップ毎に露光する。このとき、第
1図(b)に示すように、各単位チップを更に細分した
露光フィールド毎にitビーム描画用のアライメントマ
ーク2を複数個ずつ形成しておく。この荷電ビーム描画
用のアライメントマーク2は、縦、横共に、0.5 m
m〜2胴の間隔で配列させるのが良い。もちろん、最適
間隔は露光フィールドのサイズ(通常は6 mm−14
mm)によって変えられる必要がある。In this pattern forming method, first, as shown in FIG. 1(a), a relatively large pattern 3 is exposed on a wafer 1 for each unit chip using an optical reduction projection device. At this time, as shown in FIG. 1(b), a plurality of alignment marks 2 for IT beam drawing are formed for each exposure field obtained by further subdividing each unit chip. This alignment mark 2 for charged beam drawing is 0.5 m both vertically and horizontally.
It is preferable to arrange them at intervals of m to 2 cylinders. Of course, the optimum spacing is the size of the exposure field (typically 6 mm-14
mm).
しかる上で、第1図(C)に示すように上記荷電ビーム
用アライメントマーク2を用いて、荷電ビーム描画4を
行ない、微細なパターンを形成する。Then, as shown in FIG. 1C, charged beam writing 4 is performed using the charged beam alignment mark 2 to form a fine pattern.
したがって、このパターン形成方法では、光縮小投影露
光装置と荷電ビーム描画装置との間に、第5図(b)に
示したような露光歪の相違が生じるとしても、荷電ビー
ム描画装置による露光は、単位チップ内の微細領域毎に
アライメントマークを変えて行っているので、両者の露
光歪の影響は極めて小さくなり、実用上問題となるよう
なパターン誤差が生じることない。Therefore, in this pattern forming method, even if a difference in exposure distortion as shown in FIG. 5(b) occurs between the optical reduction projection exposure device and the charged beam lithography device, the exposure by the charged beam lithography device Since the alignment marks are changed for each fine region within a unit chip, the influence of exposure distortion on both is extremely small, and pattern errors that pose a practical problem do not occur.
これにより、光縮小投影露光装置の高生産性と、荷電ビ
ーム描画装置の高精度を夫々生かした好適なパターン形
成が実現できる。This makes it possible to realize suitable pattern formation that takes advantage of both the high productivity of the optical reduction projection exposure apparatus and the high precision of the charged beam lithography apparatus.
第2図は、本発明の他の実施例を説明するための図であ
り、同図(a)乃至(C)は夫々第1図(a)乃至(c
)と同様の図である。FIG. 2 is a diagram for explaining another embodiment of the present invention, and FIGS.
) is a similar figure.
この実施例では、第2図(a)のように、ウェハに光縮
小投影露光装置での露光を行ない、このとき同時に第2
図(b)のように各単位チップ3毎に複数個のアライメ
ントマーク2を形成するが、ここではアライメントマー
ク2を単位チップ内の必要な場所のみに形成している。In this embodiment, as shown in FIG.
As shown in FIG. 3B, a plurality of alignment marks 2 are formed for each unit chip 3, but here the alignment marks 2 are formed only at necessary locations within the unit chip.
その他の場所については、ウェハ単位或いはチップ単位
のアライメント基準として従来から用意されている指定
のアライメントマークのデータを用いて、第2図(c)
のように荷電ビーム描画4を行う。For other locations, data on designated alignment marks that have been prepared as alignment standards for each wafer or chip are used to align the data as shown in Figure 2(c).
Charged beam writing 4 is performed as shown below.
このようにすることにより、光縮小投影露光と荷電ビー
ム描画との露光歪が問題になりそうな場所のみを補正し
、その他は代表的なマークのデータを利用して描画する
ため描画時間の短縮化がはかれるという利点がある。By doing this, only the areas where exposure distortion between optical reduction projection exposure and charged beam writing is likely to be a problem are corrected, and data for other marks is drawn using representative mark data, reducing drawing time. It has the advantage that it can be quantified.
以上説明したように本発明は、先に光縮小投影露光装置
によりパターン転写する際に複数個の荷電ビーム用位置
決めマークを形成し、その後この位置決めマークを利用
して荷電ビーム描画装置により所望パターンを描画して
いるので、光縮小投影露光装置により形成したパターン
内で微細領域毎に荷電ビーム描画装置での描画を行うこ
とになり、荷電ビーム描画による露光歪を光縮小投影露
光による露光歪に追従させて両者の露光歪を極力小さく
なるように自動補正し、パターン転写精度を著しく向上
させることができる効果が得られる。As explained above, the present invention first forms a plurality of positioning marks for a charged beam when transferring a pattern using an optical reduction projection exposure device, and then uses the positioning marks to draw a desired pattern using a charged beam drawing device. Since the pattern is drawn using a photoreduction projection exposure device, the charged beam lithography device is used to write each minute area within the pattern formed by the photoreduction projection exposure device, and the exposure distortion caused by the charged beam drawing follows the exposure distortion caused by the photoreduction projection exposure. In this way, both exposure distortions are automatically corrected to be as small as possible, resulting in the effect that pattern transfer accuracy can be significantly improved.
第1図は本発明の一実施例のパターン形成方法を説明す
るための図で、同図(a)はウェハの平面図、同図(b
)は光縮小投影露光が終了した時点での単位チップの拡
大平面図、同図(C)は荷電ビーム描画が終了した時点
での単位チップの拡大平面図、第2図は本発明の他の方
法を説明するための図で、同図(a)乃至(C)は夫々
第1図(a)乃至(C)と同様の図、第3図は一般的な
荷電ビーム描画装置の概略図、第°4図は一般的な光縮
小投影露光装置の概略図、第5図は従来方法の問題を説
明するための図であり、同図(a)はウェハの平面図、
同図(b)は単位チップにおける露光歪の平面図である
。
1・・・ウェハ、2・・・アライメントマーク、3・・
・光縮小露光パターン、4・・・荷電ビーム描画パター
ン、11・・・ステージ、12・・・電子銃、13・・
・電子レンズ、14・・・マスク、15・・・遮蔽板、
16・・・光源、17・・・光学レンズ。
第1図
(a)
(b) (C)
第2図
(a)
(b) (C)FIG. 1 is a diagram for explaining a pattern forming method according to an embodiment of the present invention; FIG. 1(a) is a plan view of a wafer, and FIG.
) is an enlarged plan view of the unit chip at the time when optical reduction projection exposure is completed, FIG. The diagrams are for explaining the method, and the figures (a) to (C) are similar to Figures 1 (a) to (C), respectively, and Figure 3 is a schematic diagram of a general charged beam drawing device. Fig. 4 is a schematic diagram of a general optical reduction projection exposure apparatus, Fig. 5 is a diagram for explaining the problems of the conventional method, and Fig. 4 (a) is a plan view of a wafer;
FIG. 2B is a plan view of exposure distortion in a unit chip. 1... Wafer, 2... Alignment mark, 3...
- Optical reduction exposure pattern, 4... Charged beam drawing pattern, 11... Stage, 12... Electron gun, 13...
・Electronic lens, 14... mask, 15... shielding plate,
16...Light source, 17...Optical lens. Figure 1 (a) (b) (C) Figure 2 (a) (b) (C)
Claims (1)
描画する荷電ビーム描画装置と、光学レンズを用いてマ
スクパターンを半導体ウェハ上に縮小転写する光縮小投
影露光装置とを併用して半導体ウェハー上にパターンを
形成する方法において、先に光縮小投影露光装置により
パターン転写すると同時に、各露光フィールド内に複数
個の荷電ビーム用位置決めマークを形成し、その後この
位置決めマークを利用して荷電ビーム描画装置により所
望パターンを描画して所要のパターンを得ることを特徴
とするパターン形成方法。1. A charged beam writing device that scans a charged beam to draw a pattern on a semiconductor wafer and an optical reduction projection exposure device that uses an optical lens to reduce and transfer a mask pattern onto the semiconductor wafer are used in combination to write a pattern on a semiconductor wafer. In this method, a pattern is first transferred using an optical reduction projection exposure device, and at the same time, a plurality of positioning marks for a charged beam are formed in each exposure field, and then the positioning marks are used to transfer a pattern to a charged beam writing device. A pattern forming method characterized in that a desired pattern is obtained by drawing a desired pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63014737A JP2659203B2 (en) | 1988-01-27 | 1988-01-27 | Pattern formation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63014737A JP2659203B2 (en) | 1988-01-27 | 1988-01-27 | Pattern formation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01191416A true JPH01191416A (en) | 1989-08-01 |
JP2659203B2 JP2659203B2 (en) | 1997-09-30 |
Family
ID=11869434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63014737A Expired - Lifetime JP2659203B2 (en) | 1988-01-27 | 1988-01-27 | Pattern formation method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2659203B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997034319A1 (en) * | 1996-03-06 | 1997-09-18 | Hitachi, Ltd. | Manufacture of semiconductor device |
JPH1079339A (en) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | Method and apparatus for electron beam lithography |
JP2001203162A (en) * | 2000-12-18 | 2001-07-27 | Hitachi Ltd | Method and system for electron beam lithography |
JP2002110516A (en) * | 2000-09-28 | 2002-04-12 | Advantest Corp | Electron beam aligner, exposure method and semiconductor-manufacturing method |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101846878B (en) * | 2010-06-21 | 2012-07-04 | 四川虹欧显示器件有限公司 | Large-size film master mask design and combination method thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61102739A (en) * | 1984-10-26 | 1986-05-21 | Matsushita Electronics Corp | Method of forming pattern |
-
1988
- 1988-01-27 JP JP63014737A patent/JP2659203B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61102739A (en) * | 1984-10-26 | 1986-05-21 | Matsushita Electronics Corp | Method of forming pattern |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997034319A1 (en) * | 1996-03-06 | 1997-09-18 | Hitachi, Ltd. | Manufacture of semiconductor device |
US6159644A (en) * | 1996-03-06 | 2000-12-12 | Hitachi, Ltd. | Method of fabricating semiconductor circuit devices utilizing multiple exposures |
JPH1079339A (en) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | Method and apparatus for electron beam lithography |
JP2002110516A (en) * | 2000-09-28 | 2002-04-12 | Advantest Corp | Electron beam aligner, exposure method and semiconductor-manufacturing method |
JP2001203162A (en) * | 2000-12-18 | 2001-07-27 | Hitachi Ltd | Method and system for electron beam lithography |
Also Published As
Publication number | Publication date |
---|---|
JP2659203B2 (en) | 1997-09-30 |
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