JP2004071767A - Mask, exposing method, and process for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mask, an exposing method and a process for fabricating a semiconductor device in which variation in the line width of a resist pattern can be suppressed at the joint with a complementary split pattern. <P>SOLUTION: The method for exposing a pattern having a constant line width and split into first and second patterns by a split line comprises a step for exposing the first pattern through a first thin film provided with a hole having a partially thinned shape of the first pattern and a first dummy hole, and a step for exposing the second pattern through a second thin film provided with a hole having a partially thinned shape of the second pattern and a second dummy hole. In the exposing method, the quantity of exposing light is regulated such that the incident positions of charged particle beams transmitted the first and second dummy holes overlap on the exposing surface when the positional shift of the first and second patterns being transferred onto the exposing surface has a specified magnitude and thereby the pattern is reproduced on the exposing surface with a constant line width. The mask employs it and the process for fabricating a semiconductor device includes that exposing method. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an exposure method in a lithography step of manufacturing a semiconductor device, a mask used for exposure, and a method for manufacturing a semiconductor device including the exposure method of the present invention.
[0002]
[Prior art]
The demand for miniaturization in semiconductor integrated circuit devices has become increasingly severe in recent years, and design rules have reached half or less of the exposure wavelength of photolithography. Electron beam lithography has been attracting attention as a lithography technology that can meet the demands for device miniaturization that will become more severe in the future.
[0003]
In the electron beam lithography technology applied to mass production of devices, a mask that can transfer a pattern onto a resist at a time occupies an important position. For example, "High Throughput Submicron Lithography with Electron Beam Proximity Printing" (1984, Solid State Technology, p. 210) is a high-energy lithography method using a high-energy electron beam.
[0004]
On the other hand, low-energy electron beam lithography with an acceleration voltage of about 2 kV (“Low voltage alternative for electron beam lithography”) J. Vac. Sci. Technology B10 (6) p.3094 has a thickness of, for example, 0.5 μm. A stencil mask is used. These stencil masks are formed by forming holes in a thin film (membrane) to form a pattern.
[0005]
The low-energy electron beam lithography described above is an equal magnification projection system in which holes are formed in a 0.5 μm thick membrane in a pattern having a width of, for example, 0.1 μm or less. Therefore, the aspect ratio of etching becomes high. In addition, since the stencil mask bends to cause pattern distortion and misalignment, the stencil mask membrane is made of a material having high hardness, such as single crystal silicon or diamond, and relatively weak to external and internal stresses.
[0006]
For these reasons, cracks are generated at the corners of the pattern at the time of processing the membrane, and the mask is likely to be damaged, or the mask is likely to be damaged at the time of cleaning or transporting the mask. Conventionally, a mask used for photolithography has a structure in which a light-shielding film is formed on a quartz substrate, and a stencil mask for electron beam lithography has lower mechanical strength than such a mask for photolithography. .
[0007]
Therefore, for the purpose of preventing the stencil mask from being damaged, the membrane is supported using, for example, a silicon wafer. On one surface of the membrane, for example, a silicon wafer having openings formed in a lattice shape is arranged as a beam, thereby reinforcing the membrane. Holes are formed in a predetermined pattern on the portion of the membrane where no beams are formed.
[0008]
FIG. 6 shows an example of a cross-sectional view of a stencil mask having a beam. As shown in FIG. 6, a silicon wafer 2 is formed on one side of a membrane 1. The silicon wafer 2 is etched at regular intervals in a lattice shape, and the remaining portion is a beam 3. Holes 4 are formed in a predetermined pattern on the portion of the membrane 1 where the beams 3 are not formed. The layer between the membrane 1 and the silicon wafer 2 is, for example, a silicon oxide film 5 and is used as an etching stopper layer when the silicon wafer 2 is etched.
[0009]
Since the electron beam does not pass through the portion where the beam is formed, a pattern cannot be formed. When a beam is provided on the membrane, the pattern of the beam portion is transferred to another stencil mask or another area on the same stencil mask in order to transfer the pattern of the portion overlapping with the beam. It is necessary to expose the overlapped pattern (complementary division pattern) on the wafer.
[0010]
Further, the membrane of the stencil mask needs to be continuous in all parts except the holes. For example, a pattern including a discontinuous portion such as a donut-shaped pattern cannot be formed on one stencil mask. Even if there is no discontinuous portion in the membrane, there are some patterns, such as leaf-shaped patterns, which are difficult to actually form on a mask due to mechanical strength problems. The leaf-shaped pattern is a pattern in which the central portion is separated from the surroundings like the donut-shaped pattern, and the outer portion and the central portion are connected at only one of the ring portions of the donut-shaped pattern.
[0011]
In a pattern that is long in one direction or a line and space (L / S) pattern in which such line-shaped patterns are arranged in parallel, anisotropic distortion occurs around the hole, and the line width is likely to be non-uniform. Leaf-shaped patterns, fine L / S patterns, and the like are easily damaged when the mask is washed.
Such a pattern that is impossible or difficult to form on the stencil mask is also transferred by overlapping exposure of the complementary divided pattern.
[0012]
[Problems to be solved by the invention]
When the complementary division pattern is exposed as described above, misalignment may occur at the pattern division position. If a resist pattern is formed in an unnecessary portion or a resist pattern is not formed in a necessary portion due to pattern misalignment, a short circuit or poor connection may be caused. Therefore, the yield of the manufactured semiconductor device is reduced.
[0013]
The pattern a and the pattern b shown in FIG. 7 are examples of complementary division patterns, and the patterns are connected by overlapping exposure. FIG. 8A shows an example of a case where misalignment occurs in the direction in which the pattern a and the pattern b overlap in the complementary division pattern shown in FIG. 8, the pattern a in FIG. 7 is indicated by a solid line, and the pattern b is indicated by a dotted line.
[0014]
For simplicity, the overlap between the solid line and the dotted line is shown slightly shifted, but in practice there is no shift in the direction perpendicular to the longitudinal direction of the pattern. When the misregistration shown in FIG. 8A occurs, the resist pattern actually formed by exposure has a line width that increases at the overlapping portion of the pattern a and the pattern b, as shown by the thick line in FIG. 8B. Pattern.
[0015]
When the patterns a and b are optimized in consideration of the multiple exposure due to the misalignment in the overlapping direction shown in FIG. 8B so that the transferred pattern is not locally thickened, the patterns c and d shown in FIG. It becomes. The pattern c in FIG. 9 is obtained by optimizing the pattern a in FIG. 7, and the pattern d in FIG. 9 is obtained by optimizing the pattern b in FIG.
[0016]
FIG. 10A shows an example of the complementary division pattern shown in FIG. 9 in which misalignment occurs in the direction in which the pattern c and the pattern d overlap. In FIG. 10, the pattern c in FIG. 9 is indicated by a solid line, and the pattern d is indicated by a dotted line. As in FIG. 8, it is assumed that there is no misalignment in the direction orthogonal to the pattern longitudinal direction. In this case, the resist pattern actually formed by the exposure has a uniform line width including the overlapping portion of the pattern c and the pattern d as shown by the thick line in FIG.
[0017]
However, as shown in FIG. 9, when the pattern is optimized by narrowing the line width at the tip of the pattern, as shown in FIG. Is locally thin. In FIG. 11, the pattern c in FIG. 9 is indicated by a solid line, and the pattern d is indicated by a dotted line. As in FIG. 8, it is assumed that there is no misalignment in the direction orthogonal to the pattern longitudinal direction. In this case, the resist pattern actually formed by the exposure becomes thinner at the joint portion of the patterns c and d, as shown by the thick line in FIG.
[0018]
As described above, when performing the overlapping exposure of the complementary division pattern, the line width of the resist pattern locally varies due to misalignment of the pattern. As a result, the positional accuracy of processes such as etching and ion implantation performed using the resist as a mask is reduced, and the yield of the device is reduced.
[0019]
The present invention has been made in view of the above-described problems, and accordingly, an object of the present invention is to provide a mask and an exposure method that can suppress line width fluctuation of a resist pattern at a joint portion of a complementary division pattern. I do.
Another object of the present invention is to provide a method of manufacturing a semiconductor device that can accurately form a desired pattern even at a joint of complementary division patterns.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, the mask of the present invention includes a plurality of thin films that block charged particle beams irradiated to an exposure surface, and holes provided in each thin film that allow the charged particle beams to pass therethrough. A hole provided in a complementary divided pattern including a first pattern and a second pattern, each of which is a different part of the pattern and is formed by dividing a pattern having a fixed line width by one dividing line; A first pattern formed in the first thin film in the form of a thinned shape of the first pattern in the vicinity of the dividing line, and a first thin film in the vicinity of the dividing line in the first thin film. The second pattern is formed in at least one first dummy hole that is a hole formed separately from the hole of the pattern and a second thin film that is another one of the plurality of thin films in the vicinity of the dividing line. A second pattern of holes formed in a slender shape; The second thin film in the vicinity has at least one second dummy hole which is a hole formed separately from the hole of the second pattern, and the first pattern is transferred onto the exposure surface. When the misalignment between the position to be transferred and the position where the second pattern is transferred onto the exposure surface has a specific size, the charged particle beam passing through the first dummy hole is incident on the exposure surface. And the position where the charged particle beam passing through the second dummy hole enters the exposure surface overlaps, and the line width of the first pattern and the second pattern transferred to the exposure surface is constant. The first dummy hole and the second dummy hole are arranged so that
[0021]
The plurality of thin films may be different regions on the same mask, or may be respective thin films of different masks.
Thereby, it is possible to suppress the line width variation of the resist pattern at the joint portion of the complementary division pattern.
[0022]
In order to achieve the above object, the exposure method of the present invention provides a method in which a first pattern and a second pattern obtained by dividing a pattern having a constant line width by one dividing line are separately formed on an exposure surface by a charged particle beam. An exposure method for reproducing a pattern before division on an exposure surface, wherein at least one of a hole formed by narrowing a first pattern near the division line and a hole formed near the division line is provided. Exposing a first pattern through a first thin film having two first dummy holes; forming a hole in which a second pattern is narrowed in the vicinity of the division line; Exposing a second pattern via a second thin film having at least one second dummy hole that is a formed hole, wherein the first pattern is formed on the exposed surface. A transfer position and the second pattern on the exposure surface. When the misalignment with the transfer position is a specific size, the position where the charged particle beam passing through the first dummy hole is incident on the exposure surface and the charged particle passing through the second dummy hole The exposure amount is adjusted so that the positions where the lines enter the exposure surface overlap and the line width of the pattern reproduced on the exposure surface becomes constant.
[0023]
As the first thin film and the second thin film, different regions on the same mask may be used, or respective thin films of different masks may be used.
Thereby, it is possible to suppress the line width variation of the resist pattern at the joint portion of the complementary division pattern.
[0024]
In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device, comprising: dividing a first pattern and a second pattern obtained by dividing a pattern having a fixed line width by one dividing line into charged wafers; A method of manufacturing a semiconductor device, comprising separately exposing the upper resist to reproduce a pattern before division on the resist, comprising: a hole having a shape obtained by narrowing a first pattern in the vicinity of the division line; Exposing a first pattern through a first thin film having at least one first dummy hole, which is a hole formed in the vicinity, and reducing the second pattern in the vicinity of the division line. Exposing a second pattern through a second thin film having a shaped hole and at least one second dummy hole which is a hole formed in the vicinity of the dividing line; and developing the resist. And a step of When the misalignment between the position where the first pattern is transferred on the resist and the position where the second pattern is transferred on the resist has a specific size, the light passes through the first dummy hole. The position where the charged particle beam enters the resist overlaps with the position where the charged particle beam passing through the second dummy hole enters the resist, so that the line width of the pattern reproduced in the resist is constant. The exposure amount is adjusted.
As a result, a desired pattern can be accurately formed even at a joint portion of the complementary divided patterns.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a mask, an exposure method, and a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
The mask of the present embodiment is, for example, a stencil mask used for electron beam lithography, and a complementary division pattern is formed on the mask.
[0026]
The mask of the present embodiment may be a plurality of complementary masks in which complementary division patterns different from each other are formed, but one stencil mask may be formed of a plurality of regions (hereinafter referred to as complementary blocks) as shown in FIG. It may be divided into I to IV and a complementary division pattern is formed in these complementary blocks. When a plurality of complementary blocks are provided on one stencil mask, an increase in the number of masks can be suppressed, and each complementary division pattern can be simultaneously processed on the mask by a common process.
[0027]
FIG. 2 is a diagram showing a joint portion of a complementary division pattern formed on the mask of the present embodiment. As shown in FIG. 2, one pattern A is corrected so that the tip becomes thinner, and dummy patterns Ad1 and Ad2 are formed at both ends near the tip. The other pattern B is also corrected so that the tip becomes thin, and dummy patterns Bd1 and Bd2 are formed at both ends near the tip.
[0028]
When electron beam lithography is performed using a stencil mask on which a pattern as described above is formed, first, a resist is exposed using a complementary mask or a complementary block on which a pattern including pattern A and dummy patterns Ad1 and Ad2 is formed. . Next, the resist is exposed using a complementary mask or a complementary block on which the pattern B and the dummy patterns Bd1 and Bd2 are formed.
[0029]
However, the exposure using the complementary mask or the complementary block on which the pattern B and the dummy patterns Bd1 and Bd2 are formed may be performed first. After exposing the patterns A and B and their dummy patterns, the resist is developed. Thereby, as shown in FIG. 3, a resist pattern is formed with a uniform line width.
[0030]
According to the above-described exposure method of the present embodiment, as shown in FIG. 4, even when misalignment occurs in the direction in which pattern A and pattern B overlap, as shown in FIG. In the case where misalignment occurs in the direction in which the resist lines are separated, local fluctuation of the resist line width is prevented.
[0031]
In FIG. 4, the pattern A of FIG. 2 and its dummy patterns Ad1 and Ad2 are indicated by solid lines, and the pattern B and its dummy patterns Bd1 and Bd2 are indicated by dotted lines. For simplicity, the overlap between the solid line and the dotted line is shown slightly shifted, but in practice there is no shift in the direction perpendicular to the longitudinal direction of the pattern.
[0032]
The resist pattern actually formed by exposure of the pattern shown in FIG. 4A is shown by a thick line in FIG. In this case, since the line width of the pattern is corrected so as to be thin near the leading end of the pattern A and the pattern B, even if the overlapping portion of the pattern A and the pattern B becomes large, the transferred resist pattern does not become thick. .
[0033]
Further, when misalignment occurs in the direction in which the pattern A and the pattern B overlap, the dummy pattern Ad1 and the dummy pattern Bd1 do not overlap. If the dummy pattern Ad1 and the dummy pattern Bd1 are formed in such a size that a resist pattern is not formed by one exposure, the dummy patterns Ad1 and Bd1 do not appear in the developed resist.
[0034]
Similarly, when misalignment occurs in the direction in which the pattern A and the pattern B overlap, the dummy pattern Ad2 and the dummy pattern Bd2 do not overlap. Similarly to the dummy patterns Ad1 and Bd1, if the sizes of the dummy patterns Ad2 and Bd2 are controlled, the dummy patterns Ad2 and Bd2 do not appear in the developed resist.
[0035]
On the other hand, in FIG. 5 showing a case where misalignment occurs in the direction in which patterns A and B are separated from each other, pattern A in FIG. 2 and its dummy patterns Ad1 and Ad2 are indicated by solid lines, and pattern B and their dummy patterns Bd1 and Bd2 are indicated by dotted lines. Indicated by The resist pattern actually formed by exposure of the pattern shown in FIG. 5A is shown by a thick line in FIG.
[0036]
In this case, as shown in FIG. 5, the dummy pattern Ad1 and the dummy pattern Bd1 overlap, and this portion is double-exposed. Similarly, the dummy pattern Ad2 and the dummy pattern Bd2 overlap, and this portion is also double-exposed. Since the overlapping portion of the pattern A and the pattern B is small, and the line width is small near the leading ends of the patterns A and B, the distribution of the portion where the exposure amount sufficient for forming the resist pattern is given is: It becomes thinner at the joint portion of the patterns A and B (the portion indicated by C in FIG. 5A).
[0037]
However, since the overlapping portion of the dummy patterns Ad1 and Bd1 and the overlapping portion of the dummy patterns Ad2 and Bd2 are each double-exposed, the distribution of the exposure amount changes. This makes it possible to prevent the resist pattern from becoming thin at the joint portion C of the pattern after the development of the resist.
[0038]
The optimization of the pattern at the joint portion of the complementary divided patterns as described above can be performed based on a light intensity simulation using a lithography simulation microscope, for example. According to the lithography simulation microscope, a projected image obtained by transferring the mask pattern can be simulated using an actual stencil mask.
[0039]
The lithography simulation microscope has a mercury lamp and a halogen lamp as light sources, and can measure at wavelengths of 248 nm and 365 nm. The stencil mask is irradiated with light by an optical system including a condenser lens and an objective lens, and light transmitted through the stencil mask is detected by a CCD camera.
Alternatively, the resist may be actually exposed to an electron beam through a stencil mask, and the result may be used for pattern optimization.
[0040]
The method for manufacturing a semiconductor device of the present embodiment includes an electron beam lithography step of forming a resist pattern by the above-described exposure method. According to the method for manufacturing a semiconductor device of the present embodiment, since the fluctuation of the resist line width at the joint portion of the complementary division pattern is suppressed, the positional accuracy of processes such as etching and ion implantation using the resist as a mask is improved. it can. Thereby, for example, a short circuit or a connection failure of the conductive layer is avoided, and the yield of the semiconductor device can be increased.
[0041]
According to the mask and the exposure method of the embodiment of the present invention described above, it is possible to suppress a local variation in the line width of the transfer pattern at the joint portion of the complementary divided patterns. Embodiments of the mask, the exposure method, and the method for manufacturing a semiconductor device of the present invention are not limited to the above description.
[0042]
For example, depending on the arrangement and density of the surrounding patterns, as shown in FIG. 2, instead of forming dummy patterns on both sides of the ends of the patterns A and B to be joined, a dummy pattern on one side (for example, a dummy pattern) may be used. Only the patterns Ad1 and Bd1) can be formed.
[0043]
If necessary, a plurality of dummy patterns may be arranged on both sides of the patterns A and B instead of one dummy pattern on both sides of the patterns A and B. The present invention can be applied not only to high energy electron beam lithography and low energy electron beam lithography using a stencil mask, but also to other lithography using a stencil mask, such as ion beam lithography. In addition, various changes can be made without departing from the spirit of the present invention.
[0044]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to the mask of this invention, it becomes possible to suppress the line width variation of the resist pattern in the joint part of a complementary division pattern. ADVANTAGE OF THE INVENTION According to the exposure method of this invention, it becomes possible to suppress the line width fluctuation of a resist pattern in the joint part of a complementary division pattern. According to the method of manufacturing a semiconductor device of the present invention, it is possible to accurately form a desired pattern even at a joint of complementary division patterns.
[Brief description of the drawings]
FIG. 1 is a plan view showing an example of a mask of the present invention, showing a mask having a plurality of complementary blocks.
FIG. 2 is a diagram showing a part of a pattern formed on a mask of the present invention, and shows a joint portion of a complementary division pattern.
FIG. 3 is a diagram showing a joint portion of a complementary division pattern transferred by the mask or the exposure method of the present invention.
FIG. 4A is a diagram showing a state where misalignment occurs in a direction in which patterns are overlapped at a joint portion of a complementary divided pattern in the exposure method of the present invention, and FIG. It is a figure which shows the pattern transferred in the case of 4 (a).
FIG. 5A is a diagram showing a state where misalignment occurs in a direction in which patterns are separated at a joint portion of complementary division patterns in the exposure method of the present invention, and FIG. It is a figure which shows the pattern transferred in the case of 5 (a).
FIG. 6 is a sectional view showing an example of a stencil mask.
FIG. 7 is a diagram showing a joint portion of a complementary division pattern.
8A is a diagram showing a state in which misalignment has occurred in a direction in which the patterns overlap each other in the pattern shown in FIG. 7, and FIG. FIG. 3 is a diagram showing a pattern transferred to the image.
FIG. 9 is a diagram illustrating an example in which a joint portion of a complementary division pattern is corrected.
10A is a diagram showing a state in which misalignment has occurred in a direction in which the patterns overlap each other in the pattern shown in FIG. 9; FIG. FIG. 3 is a diagram showing a pattern transferred to the image.
11A is a diagram showing a state in which misalignment has occurred in a direction in which the patterns are separated from each other in the pattern shown in FIG. 9; FIG. It is a figure showing a pattern to be transferred.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... membrane, 2 ... silicon wafer, 3 ... beam, 4 ... hole, 5 ... silicon oxide film.

Claims (10)

A plurality of thin films for blocking charged particle beams irradiated on the exposure surface,
A hole provided in each thin film for transmitting a charged particle beam, which is a part different from each other in a predetermined pattern, and a first pattern and a second pattern obtained by dividing a pattern having a constant line width by one dividing line. A hole provided in a complementary division pattern including the pattern of
A first pattern hole formed in the first thin film, which is one of the plurality of thin films, in a shape obtained by narrowing the first pattern near the dividing line;
At least one first dummy hole, which is a hole formed in the first thin film near the division line and separated from the hole of the first pattern;
A second pattern hole formed in a second thin film, which is another one of the plurality of thin films, in a shape obtained by narrowing the second pattern near the division line;
The second thin film in the vicinity of the dividing line has at least one second dummy hole that is a hole formed separately from the hole of the second pattern,
When a misalignment between a position where the first pattern is transferred onto the exposure surface and a position where the second pattern is transferred onto the exposure surface has a specific size, the first dummy hole is formed. The position where the charged particle beam transmitting through the second dummy hole is incident on the exposure surface and the position where the charged particle beam transmitting through the second dummy hole is incident on the exposure surface are overlapped, and the first position which is transferred to the exposure surface is overlapped. A mask in which the first dummy holes and the second dummy holes are arranged such that the line width of the pattern and the second pattern is constant. 2. The mask according to claim 1, wherein the first dummy holes are formed on both sides of the holes of the first pattern, and the second dummy holes are formed on both sides of the holes of the second pattern. The mask according to claim 1, wherein the plurality of thin films are different regions on the same mask. The mask according to claim 1, wherein the plurality of thin films are respective thin films of different masks. An exposure method for separately exposing a first pattern and a second pattern obtained by dividing a pattern having a constant line width by one dividing line to an exposure surface by a charged particle beam and reproducing the pattern before division on the exposure surface. So,
Through a first thin film having a hole in which a first pattern is thinned in the vicinity of the division line and at least one first dummy hole which is a hole formed in the vicinity of the division line, Exposing the pattern;
Through a second thin film having a hole in which a second pattern is thinned in the vicinity of the division line and at least one second dummy hole which is a hole formed in the vicinity of the division line, Exposing the pattern,
When a misalignment between a position where the first pattern is transferred onto the exposure surface and a position where the second pattern is transferred onto the exposure surface has a specific size, the first dummy hole is formed. The position where the charged particle beam transmitting through the second dummy hole is incident on the exposure surface overlaps with the position where the charged particle beam transmitting through the second dummy hole is incident on the exposure surface, and the line width of the pattern reproduced on the exposure surface Exposure method in which the exposure amount is adjusted so that is constant. 6. The exposure method according to claim 5, wherein the first dummy hole and the second dummy hole are formed in a size that is not transferred to the exposure surface. 6. The exposure method according to claim 5, wherein the first dummy holes are formed on both sides of the holes of the first pattern, and the second dummy holes are formed on both sides of the holes of the second pattern. The exposure method according to claim 5, wherein different regions on the same mask are used as the first thin film and the second thin film. 6. The exposure method according to claim 5, wherein each of the first thin film and the second thin film is a thin film of a different mask. A method of separately exposing a first pattern and a second pattern obtained by dividing a pattern having a constant line width by one dividing line to a resist on a wafer by using a charged particle beam and reproducing the pattern before division on the resist. A method of manufacturing a semiconductor device, comprising:
Through a first thin film having a hole in which a first pattern is thinned in the vicinity of the division line and at least one first dummy hole which is a hole formed in the vicinity of the division line, Exposing the pattern;
Through a second thin film having a hole in which a second pattern is thinned in the vicinity of the division line and at least one second dummy hole which is a hole formed in the vicinity of the division line, Exposing the pattern;
Developing the resist,
When the misalignment between the position where the first pattern is transferred onto the resist and the position where the second pattern is transferred onto the resist has a specific size, the light passes through the first dummy hole. The position where the charged particle beam to be incident on the resist overlaps the position where the charged particle beam passing through the second dummy hole is incident on the resist, so that the line width of the pattern reproduced on the resist is constant. A method of manufacturing a semiconductor device in which an exposure amount is adjusted in a predetermined manner.

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