JPS61102739A - Method of forming pattern - Google Patents
Method of forming patternInfo
- Publication number
- JPS61102739A JPS61102739A JP59226361A JP22636184A JPS61102739A JP S61102739 A JPS61102739 A JP S61102739A JP 59226361 A JP59226361 A JP 59226361A JP 22636184 A JP22636184 A JP 22636184A JP S61102739 A JPS61102739 A JP S61102739A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- exposed
- resist
- exposure
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/7045—Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子ビーム露光を用いた微細パターン形成方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of forming fine patterns using electron beam exposure.
従来例の構成とその問題点
半心体素子の微細化が進むにつれて、微細なパターンを
形成するために電子ビーム露光が用いられるようになっ
た。電子ビーム露光は微細なパターンを描画できるとい
う長所を持っているが、反面、その処理に長時間を要し
、生産性が低いという欠点を持つ。そこで、この欠点を
解決するために光露光と電子ビーム露光とを併用するプ
ロセスが提案されている。たとえば、ポジ形ホトレジス
トを用いてあらかじめ、紫外光露光で比較的大きなパタ
ーンを露光し、ついで、微細パターンは電子ビーム露光
で形成する方法がある。しかいポジ形ホトレジストを電
子ビーム露光に用いる場合には、微細化が難かしいとい
う問題がある。Conventional Structures and Problems As the miniaturization of semi-concentric elements progresses, electron beam exposure has come to be used to form fine patterns. Electron beam exposure has the advantage of being able to draw fine patterns, but has the disadvantage of requiring long processing times and low productivity. Therefore, in order to solve this drawback, a process has been proposed that uses both light exposure and electron beam exposure. For example, there is a method in which a relatively large pattern is first exposed to ultraviolet light using a positive photoresist, and then a fine pattern is formed by electron beam exposure. However, when a positive photoresist is used for electron beam exposure, there is a problem in that it is difficult to miniaturize it.
発明の目的
本発明は上記の問題を解決するものであり、本発明の目
的は紫外光露光と電子ビーム露光を併用することにより
、生産性の同上を図り、しかも微細なパター／を形成す
ることである。Purpose of the Invention The present invention solves the above problems, and the purpose of the present invention is to use ultraviolet light exposure and electron beam exposure in combination to achieve the same productivity and to form a fine pattern. It is.
発明の構成
本発明は基板上に第１のポジ形レジストを形成し、その
上に第２のポジ形ホトレジストを形成する工程、前記第
２のポジ形ホトレジストを紫外光露光し、現（家する工
程、前記第２のポジ形ホトレフストの現１１（パターン
をマスクとして全面遠紫外露光する工程、前記ノボラッ
ク型ポジ形ホトレジストの現像パターンを除去する工程
、および前記第１のポン形し／ストを電子ビーム露光し
、現像する工程をそなえたパターン形成方法であり、と
１１により、サブミクロ／弔位の微細パターンの形１戊
が容易に可能である。Structure of the Invention The present invention includes a step of forming a first positive photoresist on a substrate and forming a second positive photoresist thereon, exposing the second positive photoresist to ultraviolet light, and exposing the second positive photoresist to ultraviolet light. a step of developing the second positive photoresist (a step of exposing the entire surface to deep ultraviolet light using the pattern as a mask; a step of removing the developed pattern of the novolac type positive photoresist; and a step of exposing the first photoresist to an electron beam). This is a pattern forming method that includes the steps of beam exposure and development, and by means of steps 11 and 11, it is possible to easily form submicro/microscopic patterns.
実施例の説明
以下にＧａＡｓＦＥＴ のパターンを描画する場合を
１９１として本発明の実施例を第１図〜第６図の工程順
図に従って説明する。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to step 191 in which a GaAsFET pattern is drawn, with reference to the process diagrams of FIGS. 1 to 6.
１ず、第１図のように、Ｓ工基板１上にポジ形電子ビー
ム露光用レジストのポリメチルメタクリレート（ＰＭＭ
Ａ ）２を０．５μｍの厚さに塗布した後、１７０°Ｃ
で３Ｑ分間プリベークを行なう。ついで、このＰＭＭＡ
２の上に、東京応化製の製品名０ＦＰＲｓｏＯで知られ
るノボラック型ポジ形ホトレジスト３を１μｍ塗布し、
８５℃で３０分間プリベークする。次に第２図のように
、ゲートパッド等の比較的大きな開ロバターン４を紫外
光露光し有機アルカリ系現像液、たとえば、東京応化製
の製品名ＮＭＤ−３で知られる専用現像液を用いて１分
間現像する。その後、第３図のように、このノボラック
型ポジ形しンスト３をマスクとして遠紫外光（波長２ｓ
ｏｎｍ 、 １７ｍＷ／Ｃ１１Ｉ）を５分間全面照射す
る。その結果、ゲート・づド部のＰＭＭＡ２がノボラッ
ク型ポジ形しンスト３の開ロバターン４の形状に露光さ
れる。次に、再び、専用現像液（ＮＭＩ）−３）中（で
浸して、ノボラ、り型ポジ形レジスト３を除去すると、
第４図のように、遠紫外光露光された開口用露光部５を
もつＰＭＭＡ２が露出する。なお、紫外光露光後のノボ
ラック型ポジ形レジスト３は、専用現（ｇ！ｉのＮＭＤ
−３に１０分以上浸せば容易に除去される。ついで、第
５図のように、ＰＭＭＡ２を６４μＣ／ａＩＩＩで開口
用露光部５に接する微細開口用露光部６を電子ビーム露
光した後、メチルイソブチルケトン（ＭＩＢＫ）で４分
間現像を行ない、第６図のように、ゲートバンド部およ
び微細パターンの開ロアを有する所定の回路パターンを
得ることができる。1. As shown in FIG.
A) After applying 2 to a thickness of 0.5 μm, heat at 170°C.
Pre-bake for 3Q minutes. Next, this PMMA
On top of 2, 1 μm of novolac type positive photoresist 3 known as 0FPRsoO manufactured by Tokyo Ohka Co., Ltd. is applied.
Pre-bake at 85°C for 30 minutes. Next, as shown in FIG. 2, a relatively large open pattern 4 such as a gate pad is exposed to ultraviolet light, and an organic alkaline developer, for example, a special developer known by the product name NMD-3 manufactured by Tokyo Ohka Co., Ltd. is used. Develop for 1 minute. After that, as shown in Fig. 3, this novolac positive type instrument 3 is used as a mask to expose far ultraviolet light (wavelength 2 seconds).
onm, 17 mW/C11I) for 5 minutes over the entire surface. As a result, the PMMA 2 in the gate/doped portion is exposed in the shape of the open pattern 4 of the novolac positive type instrument 3. Next, remove the novola-type positive resist 3 by immersing it in a special developer (NMI)-3).
As shown in FIG. 4, the PMMA 2 having the aperture exposure section 5 exposed to far ultraviolet light is exposed. In addition, the novolak type positive resist 3 after exposure to ultraviolet light was
It can be easily removed by soaking in -3 for 10 minutes or more. Next, as shown in FIG. 5, the fine aperture exposure area 6 in contact with the aperture exposure area 5 of PMMA2 was exposed to electron beam at 64 μC/aIII, and then developed with methyl isobutyl ketone (MIBK) for 4 minutes. As shown in the figure, a predetermined circuit pattern having a gate band portion and an open lower portion of the fine pattern can be obtained.
発明の効果
本発明により、紫外光露光と電子ビーム露光とを併用す
ることにより、高い生産性でサブミクロンの微細パター
ンを形成することが可能である。Effects of the Invention According to the present invention, by using ultraviolet light exposure and electron beam exposure in combination, it is possible to form submicron fine patterns with high productivity.
第１図〜第６図は、本発明の詳細な説明するだめの工程
順図である。
１ ・・・８１基板、２・・・・・・ポジ形電子ピーム
レジス）（ＰＭＭＡ）、３ ・・・ノボラック型ポジ
形ホトレジスト、４・・・・・・開ロバターン、５，６
・・・・・・開口用露光部、７・・・・・開口。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第
１ｒＡ
第２図1 to 6 are step-by-step diagrams for explaining the present invention in detail. 1...81 substrate, 2...Positive electron beam resist) (PMMA), 3...Novolac type positive photoresist, 4...Open pattern, 5,6
...Exposure section for aperture, 7...Aperture. Name of agent: Patent attorney Toshio Nakao and 1 other person
1rA Figure 2
Claims (1)
２のポジ形ホトレジストを形成する工程、前記第２のポ
ジ形ホトレジストを紫外光露光し、現像する工程、前記
第２のポジ形ホトレジストの現像パターンをマスクとし
て全面遠紫外光露光する工程、前記第２のポジ形ホトレ
ジストの現像パターンを除去する工程、および前記第１
のポジ形レジストを電子ビーム露光し、現像する工程を
そなえたパターン形成方法。forming a first positive photoresist on a substrate and forming a second positive photoresist thereon; exposing the second positive photoresist to ultraviolet light and developing the second positive photoresist; a step of exposing the entire surface to deep ultraviolet light using the developed pattern of the positive photoresist as a mask; a step of removing the developed pattern of the second positive photoresist; and a step of removing the developed pattern of the second positive photoresist.
A pattern forming method that involves exposing a positive resist to electron beams and developing it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59226361A JPS61102739A (en) | 1984-10-26 | 1984-10-26 | Method of forming pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59226361A JPS61102739A (en) | 1984-10-26 | 1984-10-26 | Method of forming pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61102739A true JPS61102739A (en) | 1986-05-21 |
| JPH0471331B2 JPH0471331B2 (en) | 1992-11-13 |
Family
ID=16843942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59226361A Granted JPS61102739A (en) | 1984-10-26 | 1984-10-26 | Method of forming pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61102739A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6373518A (en) * | 1986-09-16 | 1988-04-04 | Matsushita Electronics Corp | Formation of pattern |
| JPH01191416A (en) * | 1988-01-27 | 1989-08-01 | Nec Corp | Pattern forming method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58145125A (en) * | 1982-02-24 | 1983-08-29 | Nec Corp | Formation of resist mask |
-
1984
- 1984-10-26 JP JP59226361A patent/JPS61102739A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58145125A (en) * | 1982-02-24 | 1983-08-29 | Nec Corp | Formation of resist mask |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6373518A (en) * | 1986-09-16 | 1988-04-04 | Matsushita Electronics Corp | Formation of pattern |
| JPH01191416A (en) * | 1988-01-27 | 1989-08-01 | Nec Corp | Pattern forming method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0471331B2 (en) | 1992-11-13 |
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