JPS6191948A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the period in which a contact hole region is exposed to plasma as well as to avoid the adverse effect on element characteristics by a method wherein a tapered contact hole is formed on the insulating layer located on a semiconductor substrate. CONSTITUTION:The first layer of a resist 3 is coated on the insulating layer 2 formed on a semiconductor substrate 1, and the first exposure is selectively performed. Then, the second layer of resist 4 is recoated on the first layer of resist 3 in the thickness same as the first layer of resist film 3 or less without performing a developing process, and an exposure process is performed on the second layer in the area larger than the exposed area of the first layer using the energy less than the exposure of the first layer. Then, the cross-sectional form of the resist 3 of the first layer and the resist 4 of the second layer are pattern-formed by stages by performing a developing process, and the insulating layer is etched using the above-mentioned resist as a mask. As a result, a tapered contact hole can be selectively formed on the insulating layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, particularly in a step of forming a conductive layer on a semiconductor substrate via an insulating layer.
In addition to forming a tapered contact hole in the insulating layer, the method for manufacturing a semiconductor device that prevents the conductive layer from breaking is affected.

(Prior art) Conventionally, as a method of forming a tapered contact hole in an insulating layer on a semiconductor substrate, a method has been used in which wet etching (isotropic etching) and reactive ion etching (anisotropic etching) are combined. .

In this conventional method, P2O3 (second position) is formed on the semiconductor substrate l. Next, a positive type resist 5a44 is applied on the P2O3, selectively exposed to light using a reduction projection exposure method using a rainbow reticle, and developed to form a pattern (FIG. 2(B)).

Dimly dry! After post-baking at 130° C. for 30 minutes in a 2-air atmosphere, the positive patterned P8G2 is masked with the resist 3a to approximately half the film thickness by isotropic wet etching, such as buffer art etching. The cross-sectional shape of the etched fJrJ mark P S G 2' at this time is tapered.

By reactive ion etching using C) (F, also Fi, CF, +H) as an etching gas, the P8G2'' that was partially etched by J-type etching is removed (FIG. 2 (IJ)).

Next, the patterned resist 3a' used as an etching mask is removed.

Through the steps described above, a tapered contact hole is formed in the first insulating layer on the semiconductor substrate.

However, the method of forming a tapered contact hole on the insulating layer on the medium substrate described in ^11 above has the following drawbacks.

(1) In wet etching, there is a wide variation in the film layer of the mlI insulating layer that is removed by etching between the pheno-ikl, the pheno-inside, and the loft. Therefore, when the insulation Jfj remaining after wet etching is etched away by reactive ion etching, in areas where the remaining PEG film thickness is small, the time period after PEG is etched away is exposed to plasma for a long time, and the contact of the semiconductor substrate is removed. (2) The cross-sectional shape of the insulation 1 obtained by wet etching the insulation layer on the semiconductor substrate becomes tapered; IIe = has the disadvantage that the cross-sectional shape of the layer is not tapered at all.

As described above, the manufacturing process of forming a tapered contact hole in the insulating layer on the semiconductor substrate by the conventional method does not necessarily result in a stable prosthesis as a process for fabricating a semiconductor device.

(Object of the Invention) An object of the present invention is to eliminate the drawbacks of the conventional method of forming a tapered contact hole in the insulating layer on the semiconductor substrate and preventing breakage of the conductive layer on the insulating layer. Another object of the present invention is to provide a method for forming a tapered contact hole in the insulating layer on the semiconductor substrate, which allows an extremely reliable wiring structure to be obtained.

(Structure of the Invention) The method according to the present invention includes applying a first layer of positive resist on the insulating layer, for example, the PEG formed on the semiconductor substrate, and applying a reduction projection exposure method to the first reticle. The first exposure is selectively carried out using . Next, a second layer of positive resist, which is the same as the first layer of positive resist, is applied on the first layer of positive resist without developing. Apply the coating in layers. Next, the second layer of positive resist on the first layer of positive resist exposed using the first reticle is reduced and projected using a second reticle having a large contact hole of the first reticle. 1st by exposure method
The second exposure is selectively performed with less energy than the first exposure energy. Next, the first layer of positive resist and the second layer of positive resist are simultaneously developed in one development process, and the first layer of positive resist and the second layer of positive resist are developed. to form a step-like pattern. Thereafter, post-baking was performed for 30 minutes in a dry, zero-air atmosphere at 130°C, and the boundary between the first layer of positive resist and the second layer of positive resist formed in the step shape was smoothly tapered. The pattern is thermally deformed and used as a mask for reactive ion etching.

Next, using the tapered first layer of positive resist and the second layer of positive resist as masks, reactive ion etching is performed using CHFs or CF, +H as an etching gas. A taper is formed by etching away the insulating layer on the semiconductor substrate.

(Effects of the Invention) The contact holes thus formed in the insulating layer on the semiconductor substrate by the method of the present invention have the advantage that they have a smooth tapered cross section and do not use wet etching which has large variations. Therefore, there is an advantage that the time during which the contact hole region on the semiconductor substrate is exposed to plasma can be shortened, and an adverse effect on device characteristics can be avoided.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

14 to 1 (q is a sectional view showing the manufacturing process of this embodiment.

An insulating layer, for example, PSG, is placed on a semiconductor substrate, for example, an 8i substrate 1.
2 to a thickness of about 1 μm using the CVD method (first
Figure (A)). 7. Next, apply the positive resist such as 0FPI (-800 (trade name of Tokyo Ohkasha) 3 on the PSGZ, and use the first reticle 5 with a small projection exposure device to set the illuminance to 350""/ctL e The first exposure is performed under the conditions of exposure time 9QQm86C (FIG. 1(B)).

Next, without developing, the second positive resist 0FPR-8004 having the same quality as the first layer positive resist is applied.
'5c, exposure area 3' of the 1Nth positive resist;
Coat the top and unexposed area 3' (Fig. 1(C))
. At this time, the coating thickness of the second layer of positive resist 4 is equal to or less than the thickness of the first M1 positive resist 3.

Next, using a second reticle 5' having a larger recontact hole area than the first reticle 5, the second reticle 5' is used. j-th positive mv cyst 0FPR-80045c, illuminance 350W, j
A second exposure is performed under the condition of t photoseconds a 50 g m5ec . At this time, the second reticle 5' and the semiconductor substrate l
The positional relationship is the exposure UV that passes through the entire bright area to the second reticle.
The light is a positive type of the 1N6th eye) OFPR-80
0 and the unexposed area 3' (FIG. 1(D)). Furthermore, at this time, a part of the second layer of positive resists 3, 3 is exposed together with the first J@th positive resist 4'.

Next, development is performed, and the positives of the first to
The exposed area of FPR-800 and the second layer of positive type resist film) The exposed area of OFPR-800 is removed at the same time to form a one-step pattern (FIG. 1(g)).

Next, the step-shaped first layer positive type (OFP)
R-8003 and the second layer positive resist OF)'
130 to make R-8004 into a smooth taper shape
Bost baking is carried out in dry air at a temperature of 30°C for 30 minutes to slightly thermally deform the stepped pattern (FIG. 1 tF)).

Next, the first layer positive type resist 0FPR-8003# and the second layer positive type resist 0FPR-8004'@ mask were formed in a tapered shape.

The insulating layer PSG k, CHF on the semiconductor substrate 1.

Or use CF, +H, as etching gas □
The first layer is removed by reactive ion etching.
It is possible to obtain a contact hole with a smooth taper as shown in Figure (q).

The process of etching the aperture kmP8G on the semiconductor substrate into a tapered shape will be described. At the start of etching, the positive resist that serves as a mask is shown in Figure 1 (point 47 in G).
However, when etching begins, the positive resist is worn out and the resist is cut off! P8G begins to be removed. Finally, as shown in FIG. 1 (q), the positive resist is etched back and the insulating layer PE
A taper is formed in G.

Therefore, according to the method of the present invention, the shape of the contact hole is smoother than the conventional method, the conductive layer can be completely separated, and plasma damage to the semiconductor substrate in the contact hole portion is small, making it extremely reliable. Use a material that provides a contact hole with high quality.

In this embodiment, a positive resist is used for the first resist layer and the second Nth resist, but the same effect can be obtained by using a negative resist or other photosensitive organic material. Furthermore, although the reduction projection exposure method is used for exposure in this embodiment, it is also possible to apply an electron beam exposure method.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor device manufacturing method. In addition, in the figure. 1...Semiconductor substrate, for example, 8i substrate% 2t
2Z 2'12'''... Insulating layer e.g. P2O,
3, 3', 3", 37°313 13a#3a"...
...First layer positive resist, 4, 4, 4, 4,
4, 4...Second layer positive resist, 5
...First reticle, 5'... Second reticle, 3... First layer positive resist selectively exposed in the first exposure. , B...The first and second layers before the positive resist recedes during etching.
It is a positive resist with patterned layers.

Claims (1)

[Claims] In a method of selectively etching a contact hole in a tapered shape in an insulating layer formed on a semiconductor substrate by reactive ion etching, a first layer of resist is formed on the insulating layer formed on the semiconductor substrate. , selectively perform a first exposure, and overlay a second layer of resist on the first layer of resist with a film thickness equal to or less than that of the first layer of resist without developing. Apply the coating,
exposing the second layer in a larger area than the first layer with less energy than the first layer;
A method for manufacturing a semiconductor device, characterized in that the cross-sectional shapes of the first layer resist and the second layer resist are patterned in steps by development, and the insulating layer is etched using the various resists as a mask.