JPS6386550A - Formation of multilayer interconnection layer - Google Patents

Formation of multilayer interconnection layer

Info

Publication number
JPS6386550A
JPS6386550A JP23256486A JP23256486A JPS6386550A JP S6386550 A JPS6386550 A JP S6386550A JP 23256486 A JP23256486 A JP 23256486A JP 23256486 A JP23256486 A JP 23256486A JP S6386550 A JPS6386550 A JP S6386550A
Authority
JP
Japan
Prior art keywords
layer
polyimide
cunadrone
cunatron
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23256486A
Other languages
Japanese (ja)
Inventor
Kazuya Kitajima
北嶌 一也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Video Corp
Pioneer Corp
Original Assignee
Pioneer Video Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Video Corp, Pioneer Electronic Corp filed Critical Pioneer Video Corp
Priority to JP23256486A priority Critical patent/JPS6386550A/en
Publication of JPS6386550A publication Critical patent/JPS6386550A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Abstract

PURPOSE:To facilitate an etching process as well as to obtain a multilayer interconnection layer, whose insulation is favorable, with high accuracy by a method wherein a polyimide cunadrone layer is partially cured, a photosensitive polyimide cunadrone layer is formed on the upper surface thereof, a first wiring layer 2 is exposed by etching and the polyimide cunadrone layer is completely cured. CONSTITUTION:A polyimide cunadrone layer 3 is formed on the upper surface of a first wiring layer 2 and thereafter, this polyimide cunadrone layer 3 is partially cured. Then, a photosensitive polyimide cunadrone layer 4 is formed on the upper surface of the cunadrone layer 3 and is exposed by UV irradiation 8 using a photo mask 7. A part just over 5 the first wiring layer 2 is selectively etched by developing. The polyimide cunadrone layer 3 is etched using the photosensitive polyimide cunadrone layer 4 as a mask to expose the first wiring layer 2. Subsequently, the polyimide cunadrone layer 3 and the photosensitive polyimide cunadrone layer 4 are completely cured and a second wiring layer 6 is formed in contact with the exposed part.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線層の形成方法に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of forming a multilayer wiring layer.

〔従来の技術〕[Conventional technology]

一般に、ポリイミドギコナドロン層を用いて基板上に多
層の配線層を形成する場合には以1・の方法が採られて
いる。
Generally, when forming multilayer wiring layers on a substrate using a polyimide giconadron layer, the following method is adopted.

まず、第1の方法としては、基板−1−に第1配線層を
形成し、その上にポリイミドキコナドロン層を形成して
、このポリイミドキコナトしノン層を完全に硬化させた
後、通常のレジス)・を用いてマスク合わせ、露光、現
像を行い、ヒトシジンによりエツチングする。
First, the first method is to form a first wiring layer on the substrate-1-, form a polyimide quiconadron layer on it, completely cure the polyimide quiconadron layer, and then Mask alignment, exposure, and development are performed using a resist (resist), followed by etching with human cydine.

続いてレジストを除去した後、前記の、J−うにして露
出させた第1配線層に接触さUて第2配線層を形成する
Subsequently, after removing the resist, a second wiring layer is formed in contact with the first wiring layer exposed as described above.

第2の方法は、前記ポリイミドキコナト[1ン層を部分
硬化させ、通常のレノストを用いて、マスク合わせ、露
光を行いアルカリ現像液て連続(2て現像、エツチング
する。
The second method involves partially curing the polyimide xiconate layer, masking it using an ordinary lenost, exposing it to light, and continuously developing and etching it with an alkaline developer.

さらにレジスト除去後完全にポリイミドキュナトロン層
を硬化させ、第1の方法と同様に第2配線層を形成する
Further, after removing the resist, the polyimide cunatron layer is completely cured, and a second wiring layer is formed in the same manner as in the first method.

第3の方法は、第7図に示すように、基板2o上に第1
配線層21を形成しく第7図(A )) 、続いて感光
性ポリイミドキュナトロン層22を形成する(第7図(
B))。続いて、ホトマスク24を用いてUV照射25
で感光性ポリイミドキュナトロン層を露光する(第7図
(C))。
In the third method, as shown in FIG.
A wiring layer 21 is formed (FIG. 7(A)), and then a photosensitive polyimide cunatron layer 22 is formed (FIG. 7(A)).
B)). Subsequently, UV irradiation 25 is performed using a photomask 24.
The photosensitive polyimide cunatron layer is exposed to light (FIG. 7(C)).

つぎに、感光性ポリイミドキュナトロン層22上に現像
液23を塗布しく第7図(D))、第1配線層21の真
」二の感光性ポリイミドキュナトロン層22の未露光部
分26を除去する(第7図(E))。
Next, a developer 23 is applied onto the photosensitive polyimide cunatron layer 22 (FIG. 7(D)), and the unexposed portion 26 of the photosensitive polyimide cunatron layer 22 in the second wiring layer 21 is removed. (Figure 7(E)).

このようにして前記第1配線層21を露出せしめた後、
感光性ポリイミドキュナトロン層22を完全に硬化させ
、第2配線層24をこれに接触させて形成する(第7図
(F))。
After exposing the first wiring layer 21 in this way,
The photosensitive polyimide cunatron layer 22 is completely cured, and the second wiring layer 24 is formed in contact therewith (FIG. 7(F)).

〔発明が解決しようとする問題点〕 しかし、前記した従来のものにおいて(」、以下のよう
な欠点がある。
[Problems to be Solved by the Invention] However, the conventional method described above has the following drawbacks.

即ち、第1の方法は高精度のエツチングかり能であるが
、極めて有害なヒドラジンを用いるものであるため、危
険が伴う。また、工程が複雑となる。
That is, although the first method allows for highly accurate etching, it involves danger because it uses hydrazine, which is extremely harmful. Moreover, the process becomes complicated.

第2の方法は、製造工程が簡素化されるという利点はあ
るが、硬化条件いかんでは精度が低下する虞れがある。
Although the second method has the advantage of simplifying the manufacturing process, there is a risk that accuracy may be reduced depending on the curing conditions.

また、レンスト除去に有害な剥離剤が必要であり、この
剥離工程が複雑である。
Further, a harmful stripping agent is required to remove the lens, and this stripping process is complicated.

また、第3の方法では、エツチング工程が極めて簡略化
されるが、後工程で感光剤が蒸発して感光性ポリイミド
キュナトロン層の膜厚が減少し、絶縁が悪化するという
問題がある。
Further, in the third method, although the etching process is extremely simplified, there is a problem that the photosensitive agent evaporates in the subsequent process, the thickness of the photosensitive polyimide cunatron layer decreases, and the insulation deteriorates.

本発明は前記事項に鑑みてなされたもので、エツチング
工程が容易となるのは勿論、有害な薬剤を用いる必要が
なく、しかも高精度で、絶縁も良好な多層配線層の形成
方法とすることを技術的課題とする。
The present invention has been made in view of the above-mentioned matters, and it is an object of the present invention to provide a method for forming a multilayer wiring layer that not only simplifies the etching process but also does not require the use of harmful chemicals, has high precision, and has good insulation. is a technical issue.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は前記技術的課題を解決するために、以下のよう
な構成とした。
In order to solve the above technical problem, the present invention has the following configuration.

即ち、基板上1に第1配線層2を形成し、さらにその上
面にポリイミドキュナトロン層3を形成した後、このポ
リイミドキュナトロン層3を部分硬化させる つぎに、そのポリイミドキュナトロン層3の上面に感光
性ポリイミドキュナトロン層4を形成し、そして、前記
感光性ポリイミドキュナトロン層4にお(Jる前記第1
配線層2の真上に対応する部位5を選択エツチングする
That is, after forming the first wiring layer 2 on the substrate 1 and further forming the polyimide cunatron layer 3 on the upper surface thereof, the polyimide cunatron layer 3 is partially cured, and then the upper surface of the polyimide cunatron layer 3 is cured. A photosensitive polyimide cunatron layer 4 is formed on the photosensitive polyimide cunatron layer 4 (J).
A portion 5 corresponding directly above the wiring layer 2 is selectively etched.

さらに、前記感光性ポリイミドキュナトロン層4をマス
クとして前記ポリイミドキュナトロン層3をエツチング
して前記第1配線層2を露出せしめ、前記ポリイミドキ
ュナトロン層3及び感光性ポリイミドキュナトロン層4
を完全に硬化させ、続いて、この露出部分に接触させて
第2配線層6を形成して多層配線層を製造する。
Furthermore, the polyimide cunatron layer 3 is etched using the photosensitive polyimide cunatron layer 4 as a mask to expose the first wiring layer 2, and the polyimide cunatron layer 3 and the photosensitive polyimide cunatron layer 4 are etched.
is completely cured, and then a second wiring layer 6 is formed in contact with this exposed portion to produce a multilayer wiring layer.

〔作用〕[Effect]

感光性ポリイミドキュナトロン層4は光学的手法により
パターニングされるため、充分な精度が得られ、またポ
リイミドキュナトロン層は部分硬化されるものであるた
めヒドラノン等の有害な薬剤を用いる必要がない。また
レジストを使用しないため、有害な剥離剤を用いる必要
がない。
Since the photosensitive polyimide cunatron layer 4 is patterned by an optical method, sufficient precision can be obtained, and since the polyimide cunatron layer is partially cured, there is no need to use harmful chemicals such as hydranone. Furthermore, since no resist is used, there is no need to use harmful stripping agents.

さらに、ポリイミドキュナトロン層のエツチング工程に
あっては感光性ポリイミドキュナトロン層がマスク層と
なるから、絶縁層としてのポリイミドキュナトロン層が
必要量」二に蝕刻されることはない。
Furthermore, since the photosensitive polyimide cunatron layer serves as a mask layer in the etching process of the polyimide cunatron layer, the polyimide cunatron layer serving as an insulating layer is not etched to a required amount.

〔実施例〕〔Example〕

本発明の実施例を第1図ないし第6図に基づいて説明す
る。
Embodiments of the present invention will be described based on FIGS. 1 to 6.

まず、基板上lにアルミニウム層からなる第1配線層2
を形成し、さらに第1図に示すように、その上面にポリ
イミドキュナトロン層3を形成した後、このポリイミド
キュナトロン層3を部分硬化させる。
First, a first wiring layer 2 made of an aluminum layer is placed on a substrate.
After forming a polyimide cunatron layer 3 on the upper surface of the polyimide cunatron layer 3, as shown in FIG. 1, this polyimide cunatron layer 3 is partially cured.

つぎに、第2図に示すように、そのポリイミドキュナト
ロン層3の上面に感光性ポリイミドキュナトロン層4を
形成する。
Next, as shown in FIG. 2, a photosensitive polyimide cunatron layer 4 is formed on the upper surface of the polyimide cunatron layer 3.

続いて、第3図に示すように、ホトマスク7を用いてU
V照射8で感光性ポリイミドキュナトロン層4を露光す
る。
Subsequently, as shown in FIG.
The photosensitive polyimide cunatron layer 4 is exposed to V radiation 8.

さらに、第4図に示すように、前記感光性ポリイミドキ
ュナトロン層4における前記第1配線層2の真」二に対
応する部位5を現像により選択エツチングする。
Furthermore, as shown in FIG. 4, a portion 5 of the photosensitive polyimide cunatron layer 4 corresponding to the bottom of the first wiring layer 2 is selectively etched by development.

さらに、第5図に示すように、前記感光性ポリイミドキ
ュナトロン層4をマスクとして前記ポリイミドキュナト
ロン層3をエツチングして前記第1配線層2を露出せし
める。続いて、前記ポリイミドキュナトロン層3及び感
光性ポリイミドキュナトロン層4を完全に硬化させる。
Furthermore, as shown in FIG. 5, the polyimide cunatron layer 3 is etched using the photosensitive polyimide cunatron layer 4 as a mask to expose the first wiring layer 2. Subsequently, the polyimide cunatron layer 3 and the photosensitive polyimide cunatron layer 4 are completely cured.

この場合、前記感光性ポリイミドキュナトロン層4の膜
厚は40%減少する。
In this case, the thickness of the photosensitive polyimide cunatron layer 4 is reduced by 40%.

続いて、第6図に示すように、この露出部分に接触させ
て第2配線層6を形成する。
Subsequently, as shown in FIG. 6, a second wiring layer 6 is formed in contact with this exposed portion.

以上述べたように、本発明にあっては、光学的手法によ
るパターニングを採っているため充分な精度が得られ、
またポリイミドキュナトロン層は部分硬化させるだけで
よいからヒドラジノ等の有害な薬剤を用いる必要がない
。また、レンストを使用していないため、有害な剥離剤
を用いる必要がない。
As described above, the present invention employs patterning using an optical method, so sufficient accuracy can be obtained.
Furthermore, since the polyimide cunatron layer only needs to be partially cured, there is no need to use harmful chemicals such as hydrazino. Also, since it does not use Lenst, there is no need to use harmful stripping agents.

さらに、ポリイミドキュナトロン層のエツチング工程に
あっては感光性ポリイミドキュナトロン層がマスク層と
なるから、絶縁層としてのポリイミドキュナトロン層が
必要具」−に蝕刻されることはなく絶縁性も良好となる
Furthermore, in the etching process of the polyimide cunatron layer, the photosensitive polyimide cunatron layer serves as a mask layer, so the polyimide cunatron layer as an insulating layer is not etched into the required material and has good insulation properties. becomes.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、基板上に形成した第1配線層の上面に
ポリイミドキュナトロン層を形成した後、この上面に感
光性ポリイミドキュナトロン層を形成し、そして、前記
感光性ポリイミドキュナトロン層における前記第1配線
層の真上に対応する部位を選択エツチングし、さらに、
当該部分のポリイミドキュナトロン層をエツチングして
前記第1配線層を露出せしめ、続いて、この露出部分に
接触させて第2配線層を形成するものであるから、エツ
チング工程が容易となるのは勿論、有害な薬剤を用いる
必要がなく、しかも高精度で、絶縁も良好な多層配線層
を形成することができる。
According to the present invention, after forming a polyimide cunatron layer on the upper surface of the first wiring layer formed on the substrate, a photosensitive polyimide cunatron layer is formed on the upper surface, and in the photosensitive polyimide cunatron layer, selectively etching a portion directly above the first wiring layer;
The etching process is easy because the first wiring layer is exposed by etching the polyimide cunatron layer in the relevant part, and then the second wiring layer is formed in contact with this exposed part. Of course, there is no need to use harmful chemicals, and a multilayer wiring layer with high precision and good insulation can be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第6図は本発明の実施例を示す多層配線層
の断面図、第7図は従来の多層配線層の製造過程を示す
多層配線層の断面図である。 1・・・基板上、         2・・・第1配線
層、3・・ポリイミドキュナトロン層、 4・・・感光性ポリイミドキュナトロン層、5・・感光
性ポリイミドキュナトロン層における前記第1配線層の
真上に対応する部位、 6・・・第2配線層。 7・・・ホトマスク、        8・・・UV照
射。 第1図 第2図 第3図 第4図 第6図 第7図
1 to 6 are cross-sectional views of a multilayer wiring layer showing an embodiment of the present invention, and FIG. 7 is a cross-sectional view of a multilayer wiring layer showing a conventional manufacturing process of a multilayer wiring layer. DESCRIPTION OF SYMBOLS 1... On the substrate, 2... First wiring layer, 3... Polyimide cunatron layer, 4... Photosensitive polyimide cunatron layer, 5... The first wiring layer in the photosensitive polyimide cunatron layer 6. Second wiring layer. 7... Photomask, 8... UV irradiation. Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 7

Claims (1)

【特許請求の範囲】[Claims] (1)基板上に第1配線層を形成し、さらにその上面に
ポリイミドキュナドロン層を形成した後、このポリイミ
ドキュナドロン層を部分硬化させ、その上面に感光性ポ
リイミドキュナドロン層を形成し、そして、前記感光性
ポリイミドキュナドロン層における前記第1配線層の真
上に対応する部位を選択エッチングし、さらに、感光性
ポリイミドキュナドロン層をマスクとして前記ポリイミ
ドキュナドロン層をエッチングして前記第1配線層を露
出せしめ、前記ポリイミドキュナドロン層及び感光性ポ
リイミドキュナドロン層を完全に硬化させた後、この露
出部分に接触させて第2配線層を形成することを特徴と
する多層配線層の形成方法。
(1) After forming a first wiring layer on the substrate and further forming a polyimide cunadrone layer on its upper surface, this polyimide cunadrone layer is partially cured, and a photosensitive polyimide cunadrone layer is formed on the upper surface. Then, selectively etching a portion of the photosensitive polyimide cunadrone layer corresponding to the first wiring layer, and using the photosensitive polyimide cunadrone layer as a mask, remove the polyimide cunadrone layer. After exposing the first wiring layer by etching and completely curing the polyimide cunadron layer and the photosensitive polyimide cunadron layer, contacting this exposed portion to form a second wiring layer. Characteristic multilayer wiring layer formation method.
JP23256486A 1986-09-30 1986-09-30 Formation of multilayer interconnection layer Pending JPS6386550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23256486A JPS6386550A (en) 1986-09-30 1986-09-30 Formation of multilayer interconnection layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23256486A JPS6386550A (en) 1986-09-30 1986-09-30 Formation of multilayer interconnection layer

Publications (1)

Publication Number Publication Date
JPS6386550A true JPS6386550A (en) 1988-04-16

Family

ID=16941312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23256486A Pending JPS6386550A (en) 1986-09-30 1986-09-30 Formation of multilayer interconnection layer

Country Status (1)

Country Link
JP (1) JPS6386550A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01228132A (en) * 1988-03-08 1989-09-12 Hitachi Ltd Manufacture of semiconductor device
JPH04323828A (en) * 1991-04-24 1992-11-13 Nec Yamagata Ltd Manufacture of semiconductor device
JPH0746755B2 (en) * 1990-11-15 1995-05-17 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Method for manufacturing multilayer thin film structure
US5474956A (en) * 1995-03-14 1995-12-12 Hughes Aircraft Company Method of fabricating metallized substrates using an organic etch block layer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01228132A (en) * 1988-03-08 1989-09-12 Hitachi Ltd Manufacture of semiconductor device
JPH0746755B2 (en) * 1990-11-15 1995-05-17 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Method for manufacturing multilayer thin film structure
JPH04323828A (en) * 1991-04-24 1992-11-13 Nec Yamagata Ltd Manufacture of semiconductor device
US5474956A (en) * 1995-03-14 1995-12-12 Hughes Aircraft Company Method of fabricating metallized substrates using an organic etch block layer
GB2298959A (en) * 1995-03-14 1996-09-18 Hughes Aircraft Co Fabricating metallised substrates
GB2298959B (en) * 1995-03-14 1999-03-24 Hughes Aircraft Co Method of fabricating metallized substrates using an organic etch block layer

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