JPS6057632A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6057632A JPS6057632A JP16555783A JP16555783A JPS6057632A JP S6057632 A JPS6057632 A JP S6057632A JP 16555783 A JP16555783 A JP 16555783A JP 16555783 A JP16555783 A JP 16555783A JP S6057632 A JPS6057632 A JP S6057632A
- Authority
- JP
- Japan
- Prior art keywords
- film
- photoresist film
- photosensitized
- photo
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体基板上に電極層をフォトレジスト膜の
リフトオフ法によって形成する半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an electrode layer is formed on a semiconductor substrate by a photoresist film lift-off method.
従来例の構成とその問題点
トランジスタ、集積回路（ＩＣ）などの半導体装置では
、その電極層形成技術のひとつとして、フォトレジスト
膜の除去に伴なって、その開ロバターンの電極層を残す
、いわゆる、リフトオフ法が用いられる。この電極形成
方法は、半導体基板上にフォトレジスト膜を形成したの
ち、このフォトレジスト膜に電極形成用の開ロバターン
を設け、ついで、表面接合保獲膜の二酸化／リコン膜が
あるときは、これに同形の開ロバターンを設けたのち、
全面に電極層、たとえば、アルミニウム蒸着膜を設け、
その後、フォトレジスト膜を除去する際に、同レジスト
膜上のアルミニウム蒸着膜ヲ０１せて除去することによ
って、電極層のパターン形成を行なうものである。Conventional configurations and their problems In semiconductor devices such as transistors and integrated circuits (ICs), one of the techniques for forming electrode layers is a so-called method in which an electrode layer with an open pattern is left behind when a photoresist film is removed. , a lift-off method is used. This electrode formation method involves forming a photoresist film on a semiconductor substrate, and then providing an open pattern for electrode formation on this photoresist film. After providing an opening pattern of the same shape,
An electrode layer, for example, an aluminum vapor-deposited film is provided on the entire surface,
Thereafter, when the photoresist film is removed, the aluminum vapor deposited film on the photoresist film is also removed to form a pattern for the electrode layer.
ところが、かかるリフトオフ法では、通常のフォトレジ
スト膜露光処理、同現像処理おＪ：ひ適当なベーキング
処理を行なうことによって所望の開ロバターンを得た場
合、この開ロバターンは、はとんどの場合に、上方で広
く、下方で狭い側面形状になっている。そして、このよ
うな開１コバターンのレジスト膜でリフトオフ法を適用
するには、レジスト膜を電極層より厚くしないと、確実
なリフトオフを達成することかむっがしくなり、また、
レジスト膜を厚くすれば、開ロバターンの精度が低下す
るという問題点がある。However, in such a lift-off method, when a desired open pattern is obtained by performing normal photoresist film exposure processing, development processing, and appropriate baking processing, this open pattern is difficult to obtain in most cases. , the side profile is wide at the top and narrow at the bottom. In order to apply the lift-off method to such a resist film of open 1-covertane, the resist film must be made thicker than the electrode layer, otherwise it will be difficult to achieve reliable lift-off.
If the resist film is made thicker, there is a problem in that the accuracy of the opening pattern decreases.
発明の目的
本発明は、」二連の従来例にみられた問題点を解消する
もので、リフトオフ法に好適なフォトレジスト膜の形成
技術を与え、これによって、電極層形成の容易な半導体
装置の製造方法を提供するものである。OBJECTS OF THE INVENTION The present invention solves the problems seen in the two conventional examples, and provides a technique for forming a photoresist film suitable for the lift-off method, thereby providing a semiconductor device in which electrode layers can be easily formed. The present invention provides a method for manufacturing.
発明の構成
本発明は、要約するに、半導体基板上にネガティブ型フ
ォトレジスト膜を形成したのち、電極形成用フォトマス
クを用いて、前記ネガティブ型フォトレジスト膜を感光
領域に未感光部分の残る光量範囲で露光処理し、前記フ
ォトレジスト膜にオーバーハング状の側面形状の開口部
を形成する工程と、前記開口部および前記７オトレジス
ト膜上に電極層を形成したのち、前記フォトレジスト膜
を除去するリフトオフ工程とをそなえた半導体装置の製
造方法であり、これにより、フォトレジスト膜開口部の
側面形状は、」三方で狭く、下方で広くなり、リフトオ
フによって、同レジスト膜上の電極層を除去するのに好
都合なものになる。Configuring the Invention To summarize, the present invention is to form a negative photoresist film on a semiconductor substrate, and then apply the negative photoresist film to the photosensitive area by using a photomask for forming an electrode to reduce the amount of light remaining in the unexposed area. A step of forming an opening with an overhang-like side surface shape in the photoresist film by exposing the photoresist film within a range, and forming an electrode layer on the opening and the seven photoresist films, and then removing the photoresist film. A method for manufacturing a semiconductor device that includes a lift-off process, whereby the side shape of the photoresist film opening is narrow on three sides and wide at the bottom, and the electrode layer on the resist film is removed by lift-off. It becomes convenient for
実施例の説明
第１図〜第４図は、本発明の実施例で、ＮＰＮプレーす
形トランジスタの電極層形成工程を示Ｊ一工程順断面図
である。この図を参照して、以下に、実施例を詳しく述
べる。DESCRIPTION OF EMBODIMENTS FIGS. 1 to 4 are cross-sectional views showing steps for forming an electrode layer of an NPN transistor according to an embodiment of the present invention. Examples will be described in detail below with reference to this figure.
捷ず、第１図のように、Ｎ−）形エミッタ領域１、Ｐ形
ベース領域２およびＮ形コレクタ領域３をおおって、表
面部に二酸化シリコン膜４を有する半導体基板上に、架
橋型ネガティブフォトレジスト膜５を厚さ約３７１ｍに
形成する。そして、フォトマスク６を介在させて、フォ
トレジスト膜６を紫外線照射によって露光処理する。こ
のとき、紫外線照射時間あるいは紫外線照射強度を制御
して、フォトレジスト膜５の露光量を、通常照射強度の
３０〜６０％に減少させた条件で、同フォトレジスト膜
５０表面側（上方）を感光させ、その底面層（下方）に
未感光部分の残る範囲に規制する。As shown in FIG. 1, a cross-linked negative film is deposited on a semiconductor substrate having a silicon dioxide film 4 on its surface, covering an N- type emitter region 1, a P-type base region 2, and an N-type collector region 3. A photoresist film 5 is formed to a thickness of about 371 m. Then, the photoresist film 6 is exposed to ultraviolet rays with a photomask 6 interposed therebetween. At this time, the surface side (upper side) of the photoresist film 50 is exposed under the condition that the UV irradiation time or the UV irradiation intensity is controlled to reduce the exposure amount of the photoresist film 5 to 30 to 60% of the normal irradiation intensity. Expose the layer to light, and limit the area so that an unexposed area remains on the bottom layer (lower side).
こうして、露光量を制御して感光させたフォトレジスト
膜５は、その感光変質（重合硬化）部が断面逆台形にな
り、現像処理後、第２図のように、逆台形断面’ｒ！す
る、いわゆる、オーバーハング状のフォトレジスト膜パ
ターンになる。In this way, the photoresist film 5 exposed to light by controlling the exposure amount has an inverted trapezoidal cross section in the photosensitive altered (polymerized and hardened) portion, and after the development process, as shown in FIG. 2, the inverted trapezoidal cross section 'r! This results in a so-called overhang-like photoresist film pattern.
次に、第２図のように、パターン形成したフォトレジス
ト膜６をマスクとして、二酸化ノリコン膜４を同形パタ
ーンに食刻し、電極コンタクト用開口を形成する。Next, as shown in FIG. 2, using the patterned photoresist film 6 as a mask, the noricon dioxide film 4 is etched into a uniform pattern to form electrode contact openings.
ついで、第３図のように、電極層としてのアルミニウム
膜７を蒸着形成する。この場合、アルミニウム膜７は、
電極コンタクト用開口を通じて、半導体基板上のエミッ
タ領域１およびベース領域２０面に接触されるとともに
、フォトレジスト膜５のマスクパターン上へも蒸着堆積
されるが、フォトレジスト膜６のオーパーツ・ング形状
によって、その段差部では、両方のアルミニウム膜が確
実に分離される。そこで、フォトレジスト膜５を、剥離
用液に浸すことにより、剥離用液の浸透性もよく、容易
に剥離除去することができる。Then, as shown in FIG. 3, an aluminum film 7 as an electrode layer is formed by vapor deposition. In this case, the aluminum film 7 is
Through the electrode contact opening, the surfaces of the emitter region 1 and base region 20 on the semiconductor substrate are contacted, and the photoresist film 5 is deposited by vapor deposition on the mask pattern. As a result, both aluminum films are reliably separated at the stepped portion. Therefore, by immersing the photoresist film 5 in a stripping solution, the stripping solution has good permeability and can be easily stripped and removed.
こうして、第４図のように、半導体基板上へのアルミニ
ウム膜７による電極層形成が完了（〜、ＮＰＮプレーナ
形トランジスタが得ら扛る。In this way, as shown in FIG. 4, the formation of the electrode layer of the aluminum film 7 on the semiconductor substrate is completed (an NPN planar transistor is obtained).
本発明の実施は、プレーナ形トランジスタの製造工程に
限らず、半導体回路素子の多くの場合に、その電極層形
成過程に適用できる。The implementation of the present invention is applicable not only to the manufacturing process of planar transistors but also to the process of forming electrode layers in many cases of semiconductor circuit elements.
発明の効果
本発明によれば、ネガティブ型フォトレジスト膜に電極
形成相開ロバターンを形成する際に、同フォトレジスト
膜を感光領域に未感光部分の残る光量範囲で露光処理す
ることにより、このフォトレジスト膜を現像処理したと
きに、その開］］部側面がオーパーツ・ング状になり、
したがって、このフォトレジスト膜を電極層形成時のリ
フトオフに利用す几ば、確実、容易に電極層形成が行な
われる０Effects of the Invention According to the present invention, when forming an electrode-forming phase-open pattern on a negative photoresist film, the photoresist film is exposed to light within a light amount range that leaves unexposed areas in the exposed area. When the resist film is developed, the side surface of the opening becomes like an oarpart ring.
Therefore, if this photoresist film is used for lift-off when forming an electrode layer, the electrode layer can be formed reliably and easily.
第１図ないし第４図は本発明の実施例を示す工程順断面
図である０
１・・・ ・エミッタ領域、２・・・ ベース領域、３
・・・コレクタ領域、４− ・・二酸化シリコン膜、５
・・・・ネガティブ型フォトレジスト膜、６ ・・・フ
ォトマスク、７−・アルミニウム膜。1 to 4 are cross-sectional views showing the embodiments of the present invention in the order of steps. 0 1... Emitter region, 2... Base region, 3
...Collector region, 4- ...Silicon dioxide film, 5
. . . Negative photoresist film, 6 . . Photomask, 7-. Aluminum film.
Claims (1)
たのち、電極形成用フォトマスクを用いて、前記ネガテ
ィブ型フォトレジスト膜を感光領域に未感光部分の残る
光量範囲で露光処理し、前記フォトレジスト膜にオーパ
ーツ・ング状の・側面形状の開口部を形成する工程と、
前記開口部および前記フォトレジスト膜上に電極層を形
成したのち、前記フォトレジスト膜を除去するリフトオ
フ工程とをそなえた半導体装置の製造方法。After forming a negative type 7 photoresist film on a semiconductor substrate, the negative type photoresist film is exposed to light using a photomask for electrode formation in a light amount range that leaves unexposed areas in the photosensitive area, so that the photoresist film is a step of forming an opening with an opart ring-like side shape;
A method for manufacturing a semiconductor device, comprising: forming an electrode layer on the opening and the photoresist film, and then removing the photoresist film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16555783A JPS6057632A (en) | 1983-09-08 | 1983-09-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16555783A JPS6057632A (en) | 1983-09-08 | 1983-09-08 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6057632A true JPS6057632A (en) | 1985-04-03 |
| JPH0410738B2 JPH0410738B2 (en) | 1992-02-26 |
Family
ID=15814621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16555783A Granted JPS6057632A (en) | 1983-09-08 | 1983-09-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6057632A (en) |
-
1983
- 1983-09-08 JP JP16555783A patent/JPS6057632A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0410738B2 (en) | 1992-02-26 |
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